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KM6164000B中文资料

Document Title

256Kx16 bit Low Power CMOS Static RAM

Revision History

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.00.1

1.02.0

3.04.04.01

Remark

Advance Preliminary

Final Final

Final

History

Initial draft

Revise

- Die name change ; A to B Finalize

Revise

- Operating current update and release. I CC (Read/Write) = 30/60 → 15/75mA I CC1(Read/Write) = 30/60 → 15/75mA I CC2 = 160 → 130mA

Revise

- Change datasheet format

- Remove I CC write value from table.Revise

- Change test load at 55ns: 100pF → 50pF Errarta correction

Draft Data

June 28, 1996September 19, 1996

December 17, 1996February 17, 1997

February 17, 1998June 22, 1998August 8, 1998

256Kx16 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The KM616V4000B families are fabricated by SAMSUNG ′s advanced CMOS process technology. The families support various operating temperature ranges and small package types for user flexibility of system design. The families also support low data retention voltage for battery back-up opera-tion with low data retention current.

FEATURES

? Process Technology : TFT ? Organization : 256Kx16

? Power Supply Voltage : 4.5~5.5V ? Low Data Retention Voltage : 2V(Min)? Three state output and TTL Compatible ? Package Type : 44-TSOP2-400F/R

PIN DESCRIPTION

Name

Function

Name

Function

CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground

WE Write Enable Input UB Upper Byte(I/O 9~16)A 0~A 17Address Inputs LB Lower Byte (I/O 1~8)I/O 1~I/O 16

Data Inputs/Outputs

N.C

No Connection

PRODUCT FAMILY

1. The parameter is measured with 50pF test load.

Product Family Operating Temperature Vcc Range Speed(ns)Power Dissipation

PKG Type

Standby (I SB1, Max)Operating (I CC2, Max)KM6164000BL-L Commercial(0~70°C) 4.5~5.5V 551)/7020μA 130mA

44-TSOP2-F/R

KM6164000BLI-L

Industrial(-40~85°C)

4.5~

5.5V

70/100

50μA

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

A4A3A2A1A0CS I/OI I/O2I/O3I/O4Vcc Vss I/O5I/O6I/O7I/O8WE A17A16A15A14A5A6A7UB I/O16I/O15I/O14I/O13Vss Vcc I/O12I/O11I/O10I/O9N.C A8A9A1044-TSOP2Forward 44-TSOP2Reverse

44434241403938373635343332313029282726252423

12345678910111213141516171819202122

A5A6A7OE LB I/O16I/O15I/O14I/O13Vss Vcc I/O12I/O11I/O10I/O9N.C A8A9A10A1144434241403938373635343332313029282726252423

12345678910111213141516171819202122

A13

A12

A11A12

A4A3A2A1A0I/OI I/O2I/O3I/O4Vcc Vss I/O5I/O6I/O7I/O8WE A17A16A15A14A13

Clk gen.

Row select

A8A9A10A5A6A4A7A13A14A0A1A15A16A17A2I/O 1~I/O 8

A3Data cont Data cont Data cont

I/O 9~I/O 16

Vcc Vss

A12

Precharge circuit.

Memory array 1024 rows

256×16 columns

I/O Circuit Column select

WE OE UB CS

LB Control logic

PRODUCT LIST

Commercial Temperature Product(0~70°C)Industrial Temperature Products(-40~85°C)Part Name

Function

Part Name

Function

KM6164000BLT-5L KM6164000BLT-7L KM6164000BLR-5L KM6164000BLR-7L

44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-R, 55ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr

KM6164000BLTI-7L KM6164000BLTI-10L KM6164000BLRI-7L KM6164000BLRI-10L

44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-F, 100ns, LL-pwr 44-TSOP2-R, 70ns, .LL-pwr 44-TSOP2-R, 100ns, LL-pwr

ABSOLUTE MAXIMUM RATINGS 1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol Ratings Unit Remark

Voltage on any pin relative to Vss V IN ,V OUT -0.5 to 7.0V -Voltage on Vcc supply relative to Vss V CC -0.5 to7.0V -Power Dissipation P D 1.0W -Storage temperature T STG -65 to 150°C -Operating Temperature T A 0 to 70°C KM6164000BL-L -40 to 85

°C KM6164000BLI-L

Soldering temperature and time

T SOLDER

260°C, 10sec(Lead Only)

FUNCTIONAL DESCRIPTION

1. X means don ′t care. (Must be in low or high state)

CS OE WE LB UB I/O 1~8I/O 9~16Mode Power H X 1)X 1)X 1)X 1)High-Z High-Z Deselected Standby L H H X 1)X 1)High-Z High-Z Output Disabled Active L X 1)X 1)H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X 1)L L H Din High-Z Lower Byte Write Active L X 1)L H L High-Z Din Upper Byte Write Active L

X 1)

Din

Word Write

Active

RECOMMENDED DC OPERATING CONDITIONS 1)

Note:

1. Commercial Product : T A =0 to 70°C, otherwise specified Industrial Product : T A =-40 to 85°C, otherwise specified

2. Overshoot : V CC +

3.0V in case of pulse width ≤ 30ns 3. Undershoot : -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5V Ground

Vss 000V Input high voltage V IH 2.2-Vcc+0.52)

V Input low voltage

V IL

-0.53)

0.8

CAPACITANCE 1) (f=1MHz, T A =25°C)

1. Capacitance is sampled, not 100% tested

Item

Symbol Test Condition

Min Max Unit Input capacitance C IN V IN =0V -8pF Input/Output capacitance

C IO

V IO =0V

DC AND OPERATING CHARACTERISTICS

1. Industrial Product = 50μA

Item

Symbol

Test Conditions

Min Typ Max Unit

Input leakage current I LI V IN =Vss to Vcc

-1-1μA Output leakage current I LO CS=V IH or OE=V IH or WE=V IL, V IO =Vss to Vcc -1-1μA Operating power supply I CC I IO =0mA, CS=V IL , V IN =V IL or V IH , Read --15mA Average operating current

I CC1Cycle time=1μs, 100% duty, I IO =0mA CS ≤0.2V, V IN ≤0.2V or V IN ≥Vcc-0.2V

Read --15mA Write

--75I CC2

Cycle time=Min, 100% duty, I IO =0mA, CS=V IL, V IN =V IH or V IL

--130mA Output low voltage V OL I OL =2.1mA --0.4V Output high voltage V OH I OH =-1.0mA

2.4--V Standby Current (TTL)

I SB CS=V IH, Other inputs=V IL or V IH --3mA Standby Current(CMOS)I SB1

CS ≥Vcc-0.2V, Other inputs=0~Vcc

201)

μA

C L 1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns

Input and output reference voltage : 1.5V Output load (See right) :C L =100pF+1TTL

C L =50pF+1TTL

AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product : T A=0 to 70°C, Industrial product : T A =-40 to 85°C)

Parameter List

Symbol

Speed Bins

Units

55ns 70ns 100ns Min

Max Min Max Min Max Read

Read cycle time t RC 55-70-100-ns Address access time t AA -55-70-100ns Chip select to output t CO -55-70-100ns Output enable to valid output t OE -25-35-50ns Chip select to low-Z output

t LZ 10-10-10-ns Output enable to low-Z output t OLZ 5-5-5-ns UB, LB enable to low-Z output t BLZ 5-5-5-ns Chip disable to high-Z output t HZ 020025030ns OE disable to high-Z output t OHZ 020025030ns UB, LB disable to high-Z output t BHZ 020025030ns Output hold from address change t OH 10-10-10-ns LB, UB valid to data output t BA -25-35-50ns Write

Write cycle time

t WC 55-70-100-ns Chip select to end of write t CW 45-60-80-ns Address set-up time t AS 0-0-0-ns Address valid to end of write t AW 45-60-80-ns Write pulse width

t WP 45-55-70-ns Write recovery time t WR 0-0-0-ns Write to output high-Z t WHZ 020025030ns Data to write time overlap t DW 25-30-40-ns Data hold from write time t DH 0-0-0-ns End write to output low-Z t OW 5-5-5-ns LB, UB valid to end of write

t BW

-60

--80

ns DATA RETENTION CHARACTERISTICS

1. Industrial Product : 20μA

Item

Symbol Test Condition

Min Typ Max Unit Vcc for data retention V DR CS ≥Vcc-0.2V 2.0- 5.5V Data retention current I DR Vcc=3.0V

--151)μA Data retention set-up time t SDR See data retention waveform

0--ms

Recovery time

t RDR

Address

Data Out

Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS=OE=V IL , WE=V IH , UB or/and LB=V IL )

TIMING WAVEFORM OF READ CYCLE(2) (WE=V IH )

Data Valid

High-Z

t RC

Address

UB, LB

Data out

t AA

t RC

t OH

t AA t CO

t BA

t OE

t OLZ t BLZ

t LZ t OHZ

t BHZ

t HZ

NOTES (READ CYCLE)

1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

Data Undefined

UB, LB

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

t WC

t CW(2)

t WR(4)

t AW

t BW

t WP(1)

t AS(3)

t DH t DW

t WHZ

t OW t WC

t CW(2)

t AW

t BW

t WP(1)

t DH

t DW

t WR(4)

High-Z

Data Valid

t AS(3)

Address

Data Valid

UB, LB

Data in

Data out

High-Z High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) NOTES (WRITE CYCLE)

1. A wri t e occurs during the overlap(t WP ) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-tion when CS goes high and WE goes high. The t WP is measured from the beginning of write to the end of write.

2. t CW is measured from the CS going low to end of write.

3. t AS is measured from the address valid to the beginning of write.

4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as CS or WE going high.

t WC

t CW(2)

t BW

t WP(1)

t DH t DW

t WR(4)

t AW

DATA RETENTION WAVE FORM

CS controlled

V CC 4.5V

2.2V V DR

CS GND

t AS(3)

PACKAGE DIMENSIONS

Unit : millimeter(inch)

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)