AT89S52单片机应用中英文翻译
本科毕业设计（论文）AT89S52单片机应用中英文翻译
专业名称：电气工程及其自动化
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二O一二年六月九日
AT89S52 MCU Applications
Function Characteristic Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
Pin Description
VCC ：Supply voltage.
GND ：Ground.
Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.
Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.
Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.
RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each
access to exter-nal data memory.
EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2：Output from the inverting oscillator amplifier.
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information o n the timers’ operation, please click on the document link below:
https://www.wendangku.net/doc/021798456.html,/dyn/resources/prod_documents/DOC4316.PDF
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and stabilize.
Idle Mod
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
AT89S52单片机应用
功能特征描述
AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能：8k 字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。
引脚描述
VCC ：电源。
GND:接地。
P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。
P1口：P1 口是一个具有内部上拉电阻的8 位双向I/O 口，p1 输出缓冲器能驱动4 个TTL 逻辑电平。对P1 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表1所示。在flash编程和校验时，P1口接收低8位地址字节。
P2口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2 输出缓冲器能驱动4 个TTL 逻辑电平。对P2 端口写“1”时，内部上拉电阻把端口拉高，此时可以
作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电（I IL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2 口送出高八位地址。在这种应用中，P2 口使用很强的内部上拉发送1。在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。
表1 P1口第二功能
表2 P3口第二功能
P3口：P3 口是一个有内部上拉电阻的8 位双向I/O 口，p2 输出缓冲器能驱动4 个TTL 逻辑电平。对P3 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（I IL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如2表所示。在flash
编程和校验时，P3口也接收一些控制信号。
RST：复位输入。晶振工作时，RST脚持续2 个机器周期高电平将使单片机复位。看门狗计时完成后，RST 脚输出96 个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。
ALE/PROG：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8 位地址的输出脉冲。在flash编程时，此引脚(PROG)也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。这一位置“1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。
PSEN：外部程序存储器选通信号(PSEN)是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时，PSEN在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN将不被激活。
EA/VPP：访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，EA必须接GND。为了执行内部程序指令，EA应该接VCC。在flash编程期间，EA也接收12伏VPP电压。
XTAL1：振荡器反相放大器和内部时钟发生电路的输入端。
XTAL2：振荡器反相放大器的输出端。
程序存储器
如果EA引脚接地，程序读取只从外部存储器开始。对于89S52，如果EA接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。
数据存储器
AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH 的地址时，寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指令访问0A0H（P2口）存储单元MOV 0A0H , #data。使用间接寻址方式访问高128 字节
RAM。例如，下面的间接寻址方式中，R0 内容为0A0H，访问的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。MOV @R0 , #data。堆栈操作也是简介寻址方式。因此，高128字节数据RAM也可用于堆栈空间。
看门狗定时器
WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器（WDTRST）构成。WDT 在默认情况下无法工作；为了激活WDT，户用必须往WDTRST 寄存器（地址：0A6H）中依次写入01EH 和0E1H。当WDT激活后，晶振工作，WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出，它将驱动RSR引脚一个高个电平输出。
在掉电模式下，晶振停止工作，这意味这WDT也停止了工作。在这种方式下，用户不必喂狗。有两种方式可以离开掉电模式：硬件复位或通过一个激活的外部中断。通过硬件复位退出掉电模式后，用户就应该给WDT 喂狗，就如同通常AT89S52 复位一样。通过中断退出掉电模式的情形有很大的不同。中断应持续拉低很长一段时间，使得晶振稳定。当中断拉高后，执行中断服务程序。为了防止WDT在中断保持低电平的时候复位器件，WDT 直到中断拉低后才开始工作。这就意味着WDT 应该在中断服务程序中复位。为了确保在离开掉电模式最初的几个状态WDT不被溢出，最好在进入掉电模式前就复WDT。在进入待机模式前，特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数。默认状态下，在待机模式下，WDIDLE＝0，WDT继续计数。为了防止WDT在待机模式下复位AT89S52，用户应该建立一个定时器，定时离开待机模式，喂狗，再重新进入待机模式。
定时器0和定时器1
在AT89S52 中，定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样。为了获得更深入的关于UART 的信息，可参考ATMEL 网站（https://www.wendangku.net/doc/021798456.html,）。从这个主页，选择“Products”，然后选择“8051-Architech Flash Microcontroller”，再选择“Product Overview”即可。
定时器2
定时器2是一个16位定时/计数器，它既可以做定时器，又可以做事件计数器。
其工作方式由特殊寄存器T2CON中的C/T2位选择（如表2所示）。定时器2有三种工作模式：捕捉方式、自动重载（向下或向上计数）和波特率发生器。如表 3 所示，工作模式由T2CON中的相关位选择。定时器2 有2 个8位寄存器：TH2和TL2。在定时工作方式中，每个机器周期，TL2 寄存器都会加1。由于一个机器周期由12 个晶振周期构成，因此，计数频率就是晶振频率的1/12。
表3 定时器2工作模式
在计数工作方式下，寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1。在这种方式下，每个机器周期的S5P2期间采样外部输入。一个机器周期采样到高电平，而下一个周期采样到低电平，计数器将加1。在检测到跳变的这个周期的S3P1 期间，新的计数值出现在寄存器中。因为识别1－0的跳变需要2个机器周期（24个晶振周期），所以，最大的计数频率不高于晶振频率的1/24。为了确保给定的电平在改变前采样到一次，电平应该至少在一个完整的机器周期内保持不变。
中断
AT89S52 有6个中断源：两个外部中断（INT0和INT1），三个定时中断（定时器0、1、2）和一个串行中断。每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2 的标志位TF2 在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。
晶振特性
AT89S52 单片机有一个用于构成内部振荡器的反相放大器，XTAL1 和XTAL2 分别是放大器的输入、输出端。石英晶体和陶瓷谐振器都可以用来一起构成自激振荡器。从外部时钟源驱动器件的话，XTAL2 可以不接，而从XTAL1 接入。由于外部时钟信号经过二分频触发后作为外部时钟电路输入的，所以对外部时钟信号的占空比没有其它要求，最长低电平持续时间和最少高电平持续时间等还是要符合要求的。掉电模式
在掉电模式下，晶振停止工作，激活掉电模式的指令是最后一条执行指令。片上RAM和特殊功能寄存器保持原值，直到掉电模式终止。掉电模式可以通过硬件复位和外部中断退出。复位重新定义了SFR 的值，但不改变片上RAM 的值。在V CC未恢复到正常工作电压时，硬件复位不能无效，并且应保持足够长的时间以使晶振重新工作和初始化。
空闲模式
在空闲工作模式下，CPU 处于睡眠状态，而所有片上外部设备保持激活状态。这种状态可以通过软件产生。在这种状态下，片上RAM和特殊功能寄存器的内容保持不变。空闲模式可以被任一个中断或硬件复位终止。由硬件复位终止空闲模式只需两个机器周期有效复位信号，在这种情况下，片上硬件禁止访问内部RAM，而可以访问端口引脚。空闲模式被硬件复位终止后，为了防止预想不到的写端口，激活空闲模式的那一条指令的下一条指令不应该是写端口或外部存储器。
机械手机械设计论文中英文资料对照外文翻译
中英文资料对照外文翻译 机械设计 摘要： 机器由机械和其他元件组成的用来转换和传输能量的装置。比如：发动机、涡轮机、车、起重机、印刷机、洗衣机和摄影机。许多机械方面设计的原则和方法也同样适用于非机械方面。术语中的“构造设计”的含义比“机械设计”更加广泛，构造设计包括机械设计。在进行运动分析和结构设计时要把产品的维护和外形也考虑在机械设计中。在机械工程领域中，以及其它工程领域，都需要机械设备，比如：开关、凸轮、阀门、船舶以及搅拌机等。 关键词：设计流程设计规则机械设计 设计流程 设计开始之前就要想到机器的实用性，现有的机器需要在耐用性、效率、重量、速度，或者成本上得到改善。新的机器必需能够完全或部分代替以前人的功能，比如计算、装配、维修。 在设计的初级阶段，应该充分发挥设计人员的创意，不要受到任何约束。即使有一些不切实际的想法，也可以在设计的早期，即在绘制图纸之前被改正掉。只有这样，才不致于阻断创新的思路。通常,必须提出几套设计方案,然后进行比较。很有可能在这个计划最后指定使用某些不在计划方案内的一些想法的计划。 一般当产品的外型和组件的尺寸特点已经显现出来的时候，就可以进行全面的设计和分析。接着还要客观的分析机器性能、安全、重量、耐用性，并且成本也要考虑在内。每一个至关重要的部分要优化它的比例和尺寸，同时也要保持与其它组成部分的平衡。 选择原材料和工艺的方法。通过力学原理来分析和实现这些重要的特性，如稳定和反应的能量和摩擦力的利用，动力惯性、加速度、能量；包括材料的弹性强度、应力和刚度等物理特性，以及流体的润滑和驱动器的流体力学。设计的过程是一个反复与合作的过程，无论是正式的还是非正式的，对设计者来说每个阶段都很重要。。产品设计需要大量的研究和提升。许多的想法,必须通过努力去研究成为一种理念,然后去使用或放弃。
英文文献翻译
中等分辨率制备分离的 快速色谱技术 W. Clark Still,* Michael K a h n , and Abhijit Mitra Departm(7nt o/ Chemistry, Columbia Uniuersity,1Veu York, Neu; York 10027 ReceiLied January 26, 1978 我们希望找到一种简单的吸附色谱技术用于有机化合物的常规净化。这种技术是适于传统的有机物大规模制备分离，该技术需使用长柱色谱法。尽管这种技术得到的效果非常好，但是其需要消耗大量的时间，并且由于频带拖尾经常出现低复原率。当分离的样本剂量大于1或者2g时，这些问题显得更加突出。近年来，几种制备系统已经进行了改进，能将分离时间减少到1-3h，并允许各成分的分辨率ΔR f≥（使用薄层色谱分析进行分析）。在这些方法中，在我们的实验室中，媒介压力色谱法1和短柱色谱法2是最成功的。最近，我们发现一种可以将分离速度大幅度提升的技术，可用于反应产物的常规提纯，我们将这种技术称为急骤色谱法。虽然这种技术的分辨率只是中等（ΔR f≥），而且构建这个系统花费非常低，并且能在10-15min内分离重量在的样本。4 急骤色谱法是以空气压力驱动的混合介质压力以及短柱色谱法为基础，专门针对快速分离，介质压力以及短柱色谱已经进行了优化。优化实验是在一组标准条件5下进行的，优化实验使用苯甲醇作为样本，放在一个20mm*5in.的硅胶柱60内，使用Tracor 970紫外检测器监测圆柱的输出。分辨率通过持续时间（r）和峰宽（w,w/2）的比率进行测定的（Figure 1），结果如图2-4所示，图2-4分别放映分辨率随着硅胶颗粒大小、洗脱液流速和样本大小的变化。
会计内部控制中英文对照外文翻译文献
会计内部控制中英文对照外文翻译文献(文档含英文原文和中文翻译)
内部控制透视：理论与概念 摘要：内部控制是会计程序或控制系统，旨在促进效率或保证一个执行政策或保护资产或避免欺诈和错误。内部是一个组织管理的重要组成部分。它包括计划、方法和程序使用，以满足任务，目标和目的，并在这样做，支持基于业绩的管理。内部控制是管理阶层的平等与控制可以帮助管理者实现资源的预期的有效管理的结果通过。内部控制应减少或违规错误的风险关联未被发现的，但设计和建立有效的内部控制不是一个简单的任务，不可能是一个实现通过快速修复短套。在此讨论了内部文件的概念的不同方面的内部控制和管制。 关键词：内部控制，管理控制，控制环境，控制活动，监督 1、介绍 环境需要新的业务控制变量不为任何潜在的股东和管理人士的响应因子为1，另外应执行/她组织了一个很大的控制权。控制是管理活动的东西或以上施加控制。思想的产生和近十年的发展需要有系统的商业资源和控制这种财富一个新的关注。主题之一热一回合管制的商业资源是分析每个控制成本效益。 作为内部控制和欺诈的第一道防线，维护资产以及预防和侦查错误。内部控制，我们可以说是一种控制整个系统的财务和其他方面的管理制定了为企业的顺利运行;它包括内部的脸颊，内部审计和其他形式的控制。 COSO的内部控制描述如下。内部控制是一个客观的方法用来帮助确保实现。在会计和组织理论，内部控制是指或目标目标的过程实施由组织的结构，工作和权力流动，人员和具体的管理信息系统，旨在帮助组织实现。这是一种手段，其中一个组织的资源被定向，监控和测量。它发挥着无形的（重要的作用，预防和侦查欺诈和保护组织的资源，包括生理（如，机械和财产）和乙二醇，声誉或知识产权，如商标）。在组织水平，内部控制目标与可靠性的目标或战略的财务报告，及时反馈业务上的成就，并遵守法律，法规。在具体的交易水平，内部控制是指第三方采取行动以实现一个具体目标（例如，如何确保本组织的款项，在申请服务提供有效的。）内部控制程序reduce程变异，导
机械设计外文翻译(中英文)
机械设计理论 机械设计是一门通过设计新产品或者改进老产品来满足人类需求的应用技术科学。它涉及工程技术的各个领域，主要研究产品的尺寸、形状和详细结构的基本构思，还要研究产品在制造、销售和使用等方面的问题。 进行各种机械设计工作的人员通常被称为设计人员或者机械设计工程师。机械设计是一项创造性的工作。设计工程师不仅在工作上要有创造性，还必须在机械制图、运动学、工程材料、材料力学和机械制造工艺学等方面具有深厚的基础知识。如前所诉，机械设计的目的是生产能够满足人类需求的产品。发明、发现和科技知识本身并不一定能给人类带来好处，只有当它们被应用在产品上才能产生效益。因而，应该认识到在一个特定的产品进行设计之前，必须先确定人们是否需要这种产品。 应当把机械设计看成是机械设计人员运用创造性的才能进行产品设计、系统分析和制定产品的制造工艺学的一个良机。掌握工程基础知识要比熟记一些数据和公式更为重要。仅仅使用数据和公式是不足以在一个好的设计中做出所需的全部决定的。另一方面，应该认真精确的进行所有运算。例如，即使将一个小数点的位置放错，也会使正确的设计变成错误的。 一个好的设计人员应该勇于提出新的想法，而且愿意承担一定的风险，当新的方法不适用时，就使用原来的方法。因此，设计人员必须要有耐心，因为所花费的时间和努力并不能保证带来成功。一个全新的设计，要求屏弃许多陈旧的，为人们所熟知的方法。由于许多人墨守成规，这样做并不是一件容易的事。一位机械设计师应该不断地探索改进现有的产品的方法，在此过程中应该认真选择原有的、经过验证的设计原理，将其与未经过验证的新观念结合起来。 新设计本身会有许多缺陷和未能预料的问题发生，只有当这些缺陷和问题被解决之后，才能体现出新产品的优越性。因此，一个性能优越的产品诞生的同时，也伴随着较高的风险。应该强调的是，如果设计本身不要求采用全新的方法，就没有必要仅仅为了变革的目的而采用新方法。 在设计的初始阶段，应该允许设计人员充分发挥创造性，不受各种约束。即使产生了许多不切实际的想法，也会在设计的早期，即绘制图纸之前被改正掉。只有这样，才不致于堵塞创新的思路。通常，要提出几套设计方案，然后加以比较。很有可能在最后选定的方案中，采用了某些未被接受的方案中的一些想法。
外文翻译--如何监测内部控制
附录A
附录B 如何监测内部控制 内部控制是任何组织有效运行的关键,董事会、执行长和内部审计人员都为实现这个企业的目标而工作;该内部控制系统是使这些团体确保那些目标的达成的一种手段。控制帮助一个企业有效率地运转。此外,运用一种有效的风险系统,风险可被降低到最小。同时,控制促进经营和与经营有关的信息的可靠性。全美反舞弊性财务报告委员会发起组织(COSO；1992) 在它发布的具有开创性的文件《内部控制整合框架》中,将内部控制定义为：企业风险管理是一个过程，受企业董事会、管理层和其他员工的影响，包括内部控制及其在战略和整个公司的应用，旨在为实现经营的效率和效果、财务报告的可靠性以及法规的遵循提供合理保证。该委员会还指出,一个的内部控制的系统包括五个要素。它们是：控制环境、风险评估、信息和沟通、控制活动、监控。 COSO的定义及五个要素已被证明确实对不同的团体,如董事会和首席执行官起到作用。这些群体对内部控制系统的监管以及系统设计与运行有责任。而且,内部审计人员已经发现COSO的指导是有用的。这群人员可能会被董事会或管理层要求去测试控制。COSO最近发布的一份讨论文件，指出五个要素监控,其中的五个要素的确定在1992 frame work COSO原本。中国发展简报的题为《内部控制-整合框架：内部控制体系监督指南》(COSO，2007)。在文件中,COSO 强调监控的重要性，以及这些信息常常被没有充分利用。 因为董事会、执行长,和内部审计人员都在一个公司的内部控制中扮演着重要角色，内部控制的各要素,包括监测,都对所有的团体有着非常重要的意义。同时,外审计人员对监测有兴趣。《萨班斯-奥克斯利法案》（2002）为外部审计师创建了一个新的监督体制。所有的五个要素,包括监测,必须加以考虑。另外,内部控制审计必须结合对财务报告的检查。在一体化审计之前，在首席执行官的领导下，也许也在内部审计活动的支持下的管理，评估了内控制体系的有效性。随后外部审计人员对控制出具意见。起监督角色的董事会，将阅读内部审计、管理层和首席执行官出具的报告。文件关于监测对每一个团体的指导起了帮助,因为他们分别为各自的角色而劳动。 第一，什么是监测。监测的组成可评估内部控制系统在过去一段时间发挥效用的质量。其对控制功能的评估有助于企业确定其控制在有效地运作中。在执行监测活动时，相关人员参与审查系统的设计及其运行效果。这种检查必须进行及时,目的是为了提供给企业最大的利益。管理层负责做出适当的行动以回应这些结果。当事人对内部控制有兴趣,可以充分依赖这个内部控制系统,如果合适的监
机械专业外文翻译中英文翻译
外文翻译 英文原文 Belt Conveying Systems Development of driving system Among the methods of material conveying employed，belt conveyors play a very important part in the reliable carrying of material over long distances at competitive cost．Conveyor systems have become larger and more complex and drive systems have also been going through a process of evolution and will continue to do so．Nowadays，bigger belts require more power and have brought the need for larger individual drives as well as multiple drives such as 3 drives of 750 kW for one belt(this is the case for the conveyor drives in Chengzhuang Mine)．The ability to control drive acceleration torque is critical to belt conveyors’ performance．An efficient drive system should be able to provide smooth，soft starts while maintaining belt tensions within the specified safe limits．For load sharing on multiple drives．torque and speed control are also important consideratio ns in the drive system’s design. Due to the advances in conveyor drive control technology，at present many more reliable．Cost-effective and performance-driven conveyor drive systems cov ering a wide range of power are available for customers’ choices[1]. 1 Analysis on conveyor drive technologies 1．1 Direct drives Full-voltage starters．With a full-voltage starter design，the conveyor head shaft is direct-coupled to the motor through the gear drive．Direct full-voltage starters are adequate for relatively low-power, simple-profile conveyors．With direct fu11-voltage starters．no control is provided for various conveyor loads and．depending on the ratio between fu11- and no-1oad power requirements，empty starting times can be three or four times faster than full load．The maintenance-free starting system is simple，low-cost and very reliable．However, they cannot control starting torque and maximum stall torque；therefore．they are
中小企业内部控制_外文参考文献
中小企业内部控制_外文参考文献 安徽工业大学毕业设计外文翻译 Private Enterprises of the intenal control issues Pulin Chang Economic Review. 2008, (5) Third, the promotion of private SMEs in the internal control system strategy (A) change management and business owners the concept of development. The majority of private small and medium enterprises in the family business, the success of these enterprises depends largely on internal control or entrepreneur leadership attention and level of implementation. Over the years, by traditional Chinese culture, business owners believe in Sincerity, fraternal loyalty permeate many aspects of enterprise management, strengthen internal controls that will affect the organization the members of distrust, resulting in internal control. Many private business owners that rely on business to do business benefits out of, rather than out of the internal financial management control; that the market is the most important internal control will be bound himself and staff development. Understanding of the bias, so that these leaders neglected the internal control system on the production and operation activities. Internal control can really become the leader of the internal needs of enterprise internal control system is the key to whether a mere formality. The internal control to make the internal needs of the enterprise depends largely on two points: First, determine
外文翻译英文
A Distributed Approach for Track Occupancy Detection Abstract This paper investigates the problem of track occupancy detection in distributed settings. Track occupancy detection determines which tracks are occupied in a railway system. For each track, the Neyman–Pearson structure is applied to reach the local decision. Globally, it is a multiple hypotheses testing problem. The Bayesian approach is employed to minimize the probability of the global decision error. Based on the prior probabilities of multiple hypotheses and the approximation of the prior probabilities of multiple hypotheses and the approximationofthereceiving operation characteristic curve of the local detector, a person-by-person optimization method is implemented to obtain the fusion rule and the local strategies off line. The results are illustrated through an example constructed from in situ devices. Key Words:Track occupancy detection,Neyman–Pearson, Generalized likelihood ratio test, Bayesian approach,Distributed detection 1Introduction With respect to the majority of railway systems in China, a quasi-moving block method is employed to specify the safe zone of a train. A key piece of knowledge to be determined is the set of track segments that are occupied, i.e., track occupancy detection. Then the speed restriction curves for the following trains are calculated accordingly. When there are misdetections, collisions may happen; additionally, false alarms may lead to declines of line capacity. Track occupancy detection is achieved by a set of track circuits. The track circuit is a crucial device mainly composed of a transmitter–receiver pair and a track segment. The measurement is the receiving signal at the end of the track. For each segment, a decision is made locally and individually, which leads to frequent ambiguities on which tracks are occupied for the whole line. It means that the false alarm rate of the line increases greatly. Besides, for the next generation of railway systems, a moving block method is adopted. Such a method requires the exact position and velocity of the train. However, those data are not provided in the current detection mechanism.
机械图纸中英文翻译汇总
近几年，我厂和英国、西班牙的几个公司有业务往来，外商传真发来的图纸都是英文标注，平时阅看有一定的困难。下面把我们积累的几点看英文图纸的经验与同行们交流。 1标题栏 英文工程图纸的右下边是标题栏（相当于我们的标题栏和部分技术要求），其中有图纸名称（TILE）、设计者（DRAWN）、审查者（CHECKED）、材料（MATERIAL）、日期（DATE）、比例（SCALE）、热处理（HEAT TREATMENT）和其它一些要求，如： 1)TOLERANCES UNLESS OTHERWISE SPECIFIAL 未注公差。 2)DIMS IN mm UNLESS STATED 如不做特殊要求以毫米为单位。 3)ANGULAR TOLERANCE±1°角度公差±1°。 4)DIMS TOLERANCE±0.1未注尺寸公差±0.1。 5)SURFACE FINISH 3.2 UNLESS STATED未注粗糙度3.2。 2常见尺寸的标注及要求 2.1孔（HOLE）如： （1）毛坯孔：3"DIAO+1CORE 芯子3"0+1; （2）加工孔：1"DIA1"; （3）锪孔：锪孔(注C＇BORE=COUNTER BORE锪底面孔); （4）铰孔：1"/4 DIA REAM铰孔1"/4; （5）螺纹孔的标注一般要表示出螺纹的直径，每英寸牙数（螺矩）、螺纹种类、精度等级、钻深、攻深，方向等。如： 例1.6 HOLES EQUI-SPACED ON 5"DIA (6孔均布在5圆周上（EQUI-SPACED=EQUALLY SPACED均布） DRILL 1"DIATHRO＇ 钻1"通孔（THRO＇=THROUGH通） C/SINK22×6DEEP 沉孔22×6 例2.TAP7"/8-14UNF-3BTHRO＇ 攻统一标准细牙螺纹，每英寸14牙，精度等级3B级 （注UNF=UNIFIED FINE THREAD美国标准细牙螺纹） 1"DRILL 1"/4-20 UNC-3 THD7"/8 DEEP 4HOLES NOT BREAK THRO钻 1"孔，攻1"/4美国粗牙螺纹，每英寸20牙，攻深7"/8,4孔不准钻通（UNC=UCIFIED COARSE THREAD 美国标准粗牙螺纹）
外文翻译(英文)
Title: Modelling of transport costs and logistics for on-farm milk segregation in New Zealand dairying Material Source: Computers and Electronics in Agriculture Author: A. E. Dooley, Parker, H. T. Blair Abstract On-farm milk segregation to keep milk with high value properties separate from bulk milk will affect transport logistics. Separate milk collection, either as independent runs for different milk types,or storage of distinct milk types in the truck and trailer units, may increase the length and number of runs required. Two contrasting regions,with different farm sizes and roading networks were modelled,at two stages of lactation over 20 years. Thirty farms in each region were modelled with 0, 25, 50 and 100% of farms per region changing milk types over a transition period of up to 18 years. Genetic algorithm software was used to search for the order of the farm milk collection pick-ups which gave an optimal, least cost solution for milk collection for each prescribed set of inputs. Milk collection costs within scenario were variable over time depending on the amounts of the different milk types, increasing whenever another run was required, then decreasing over time as the milk load increased. Milk collection cost is small relative to milk income, with the status quo (SQ) cost for milk collection being less than NZ$9.61/kl for the North Island and NZ$13.53/kl for the South Island farm sets. The increased transport costs associated with collecting two milk types ranged from 4.5 to 22.0% more for the different scenarios. The extra cost to an average size North Island farm changing systems (25% farms changing), compared to an equivalent status quo farm, would be between NZ$307 and NZ$1244 per year. Fewer farms changing to differentiated milk production increased the costs per kilolitre of differentiated milk. Keywords: Milk transport; Scheduling; Milk segregation; Collection costs 1.Introduction
机械外文翻译中英文
英文资料 Limits and Tolerances The breakage of the machine spare parts ,generally always from the surface layer beginning of .The function of the product ,particularly its credibility and durable ,be decided by the quantity of spare parts surface layer to a large extent. Purpose that studies the machine to process the surface quantity be for control the machine process medium various craft factor to process the surface quantity influence of regulation, in order to make use of these regulations to control to process the process, end attain to improve the surface quantity, the exaltation product use the function of purpose . The machine processes the surface quantity to use the influence of the function to the machine (A) The surface quantity to bear to whet the sexual influence 1.Rough degree of surface to bear to whet the sexual influence A just process vice-of two contact surfaces of good friction, the first stage is rough only in the surface of the peak department contact ,the actual contact area is much smaller than theoretical contact area, in contact with each other the peak of the units have very great stress, to produce actual contact with the surface area of plastic deformation, deformation and peak between the Department of shear failure, causing serious wear. Parts wear may generally be divided into three stages, the initial stage of wear and tear, normal wear and tear all of a sudden intense phase of stage wear. Parts of the surface roughness of the surface wear big impact. In general the smaller the value of surface roughness, wear better. However, surface roughness value is too small, lubricants difficult to store, contact between the adhesive-prone elements, wear it to increase. Therefore, the surface roughness of a best value, the value and parts of the work related to increased work load, the initial wear increased, the best rough surface is also increased. 2.Cold Working hardening the surface of the wear resistance Processing the Cold Work hardening the surface of the friction surface layer of metal microhardness increase, it will generally improve the wear resistance. Cold Working but not a higher degree of hardening, wear resistance for the better, because too much will lead to hardening of the Cold Working excessive loose organization of
外文翻译中英对照版
VOLUME 30 ISSUE 2 October 2008 Journal of Achievements in Materials and Manufacturing Engineering Copyright by International OCSCO World Press. All rights reserved.2008 151 Research paper 2008年十月期2卷30 材料与制造工程成果期刊 版权所有：国际OCSCO 世界出版社。一切权利保有。2008 ？？151研究论文 1. Introduction Friction stir welding (FSW) is a new solid-state welding method developed by The Welding Institute (TWI) in 1991 [1]. The weld is formed by the excessive deformation of the material at temperatures below its melting point, thus the method is a solid state joining technique. There is no melting of the material, so FSW has several advantages over the commonly used fusion welding techniques [2-10]. 1.导言摩擦搅拌焊接（FSW）是焊接学？会于1991年研发的一种新型固态焊接方法。这种焊接？是由材料在低于其熔点的温度上过量变形形成，因此此技术是一种固态连接技术。材料不熔化，所以FSW 相比常用的熔化焊接技术有若干优势。例如，在焊接区无多孔性或破裂，工件（尤其薄板上）没有严重扭曲，并且在连接过程中不需要填料、保护气及昂贵的焊接准备there is no significant distortion of the workpieces (particularly in thin plates), and there is no need for filler materials, shielding gases and costly weld preparation during this joining process. FSW被认为是对若干材料例如铝合金、镁合金、黄铜、钛合金及钢最显著且最有潜在用途的焊接技术FSW is considered to be the most remarkable and potentially useful welding technique for several materials, such as Al-alloys, Mg-alloys, brasses, Ti-alloys, and steels [1-16]. 然而，在FSW过程中，用不合适的焊接参数能引起连接处失效，并且使FSW连接处的力学性能恶化。However, during FSW process using inappropriate welding parameters can cause defects in the joint and deteriorate the mechanical properties of the FSW joints [2, 3]. 此技术起初就主要是为低熔点材料如铝合金、镁合金及铜合金而广泛研究的。The technique has initially been widely investigated for mostly low melting materials, such as Al, Mg and Cu alloys. 此技术已被证明是很有用的，尤其在连接用于航空航天用途的如高合金2XXX及7XXX系列铝合金等难熔高强度的铝合金。It has proven to be very useful, particularly in the joining of the difficult-to-fusion join high strength Al-alloys used in aerospace applications, such as highly alloyed 2XXX and 7XXX series aluminium alloys. 做出Al-5086 H32型板摩擦搅拌对焊的高强度、抗疲劳及断裂的力学性能？。The difficulty of making high-strength, fatigue and fracture resistant Mechanical properties of friction stir butt-welded Al-5086 H32 plate G. .am a,*, S. Gü.lüer b, A. .akan c, H.T. Serinda. a a Mustafa Kemal University, Faculty of Engineering and Architecture, 31040 Antakya, Turkey a 土耳其安塔卡亚31040，Mustafa Kemal大学建筑工程系 b General Directorate of Highways of Turkey, Ankara, Turkey b 土耳其安卡拉土耳其高速公路总理事会？ c Abant Izzet Baysal University, Faculty of Engineering an d Architecture, 14280 Bolu, Turkey c 土耳其Bolu 14280 Abant Izzet Baysal 大学建筑工程系 * Corresponding author: E-mail address: gurelcam@https://www.wendangku.net/doc/021798456.html, *相关作者电子邮箱地址：gurelcam@https://www.wendangku.net/doc/021798456.html, Received 30.06.2008; published in revised form 01.10.2008
外文翻译--中小型民营企业内部控制研究
中文5900字 本科毕业设计（论文） 外文参考文献译文及原文 学院 专业 年级班别 学号 学生姓名 指导教师 年月日
中小民营企业内部控制研究 Research on the Internal Control of Small and Medium-sized Private Enterprises 目录 摘要 (1) 1 选题背景 (2) 2内部控制理论的概述 (3) 2.1 内部控制的根本性质 (3) 2.2内部控制的责任 (3) 3 确保内部控制的充分性 (5) 4 先天的内部控制 (9) 5 结论 (11) Abstract (12) 1Background Topics (13) 2 Internal control theory outlined (15) 2.1 The Fundamental Nature Of Intaral Control (15) 2.2 Responsibillty For Internal Control (15) 3 Ensuring that the internal control adequacy (17) 4 Inherent limitations of internal control (22) 5 Conclusion (25)
摘要 内部控制这个概念已经不是一个新概念。这篇文章将研究每个公共部门财政经理和董事会成员应该了解的关于内部控制的内容。在分析了虚假的财政报告的根本原因以后，Treadway 委员会把大部分的责任归咎于内部控制管理的不足。作为回应，建立Treadway委员会的各个组织成立了一个赞助组织委员会（COSO），设法补救的Treadway委员会揭露出来的问题。 COSO为了确保此架构足够及全面的内部控制，确定了5个重要组成部分：1、控制环境；2、风险评估；3、政策及程序；4、沟通；5、监测与追踪。一个健全的架构与内部控制是必要的，同时必须意识到这类框架是难于达到一个完美的境界。内部控制在本质上是一种管理责任。