PL611S-27-XXXTI中文资料

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(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
FEATURES
? ? ? ? Advanced One Time Programmable (OTP) PLL design Programmable PLL or direct oscillation operation Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) Output Frequency up to o 65MHz @ 1.8V operation o 9/MHz @ 2.5V operation o 125MHz @ 3.3V operation Reference Input Frequency: 1MHz to 200MHz Accepts >0.1V reference signal input voltage Low current consumption, <10 A when PDB is activated One programmable I/O pin can be configured as Output Enable (OE), Frequency Switching (FSEL), or Power Down (PDB) input. Disabled outputs programmable as HiZ or Active Low. Single 1.8V, 2.5V, or 3.3V ± 10% power supply Operating temperature range from 0°C to 70°C Available in 6-pin SOT23 & DFN GREEN/RoHS Compliant packages
DESCRIPTION
The PL611s-27 is a general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL product family. Designed to fit in a small 6-pin DFN, or 6-pin SOT package for high performance applications, the PL611s-27 offers very low phase noise, jitter, and power consumption, while offering 2 clock outputs. The Frequency Switching (FSEL) capability of PL611s-27 allows for programming two sets of frequencies, while the power down feature of PL611s-27, when activated, allows the IC to consume less than 10 A of power. PL611s-27’s programming flexibility allows generating any output using a Reference input signal.
? ? ? ?
? ? ? ?
PACKAGE PIN CONFIGURATION
CLK1
PL611s-27
1 2 3
6 5 4
CLK0 VDD OE, PDB, FSEL
PL611s-27 PL611s-27 PL611s-27 PL611s-27
FIN CLK1 GND
1 2 3
6 5 4
OE, PDB, FSEL VDD CLK0
GND FIN
DFNDFN-6L
(2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm)
SOT23SOT23-6L 23
(3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm
BLOCK DIAGRAM
FIN
F ref R-counter
(8-Bit) M-counter (11-Bit)
Phase Detector
Charge Pump
Loop Filter
Fvco= Fref * (2 * M / R)
VCO
P-counter (5-Bit)
Fout=FVCO/(2*P)
CLK1 CLK0
Programmable Function
Programming Logic
OE, PDB, FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 1

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: ? Low: 4mA ? Std: 8mA (default) ? High: 16mA Programmable Input/Output One output pin can be configured as: ? ? ? ? OE - input PDB - input FSEL – input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
CLK1 GND FIN
Pin Assignment DFN SOT Pin# Pin #
2 3 1 1 2 3
Type
O P I
Description
Programmable Clock Output GND connection Reference input pin This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down (PDB) input or Frequency Switching (FSEL) input. This pin has an internal 60K pull up resistor.
OE, PDB, FSEL
6
4
I
The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. State 0 1 (default) OE Disable CLK Normal mode PDB Power Down Mode Normal mode FSEL Frequency ‘2’ Frequency ‘1’
VDD CLK0
5 4
5 6
P O
VDD connection Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE 1 0 N/A N/A PDB N/A N/A 1 0 Osc. On On On Off PLL On Off On Off CLK0 On HiZ or Active Low On HiZ or Active Low CLK1 On On On HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 2

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-27 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-27 accepts a reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 55MHz. This flexible design allows the PL611s-27 to deliver any PLL generated frequency, F REF (Ref Clk) frequency or F REF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-27 are mentioned below: PLL Programming The PLL in the PL611s-27 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. Clock Output (CLK0) CLK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF (Ref Clk Frequency) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. Clock Output (CLK1) The CLK1 feature allows the PL611s-27 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference (Ref Clk) Frequency FREF / 2 CLK0 CLK0 / 2 When using the OE function CLK1 will remain “Always On” and will not be disabled when OE is pulled low. When using the PDB function CLK1 will be disabled along with CLK0. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic “1”. The OE feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. Power-Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL611s-27 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10 A of power. The PDB pin incorporates a 60k pull up resistor giving a default condition of logic “1”. The PDB feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-27 to switch between two pre-programmed outputs allowing the device “On the Fly” frequency switching. The FSEL pin incorporates a 60k pull up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 3

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention @ 85°C Storage Temperature Ambient Operating Temperature* TS 10 -65 -40 150 85
SYMBOL
V DD VI VO
MIN.
MAX.
7 V DD + 0.5 V DD + 0.5 260
UNITS
V V V °C Year °C °C
- 0.5 - 0.5 - 0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V DD =3.3V Input (FIN) Frequency @ V DD =2.5V @ V DD =1.8V Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz @ V DD =3.3V Output Frequency @ V DD =2.5V @ V DD =1.8V Settling Time Output Enable Time Output Rise Time Output Fall Time Duty Cycle At power-up (after V DD increases over 1.62V) OE Function; Ta=25o C, 15pF Load PDB Function; Ta=25o C, 15pF Load 15pF Load, 10/90% V DD , High Drive, 3.3V 15pF Load, 90/10% V DD , High Drive, 3.3V V DD /2 45 1.2 1.2 50 70 0.9 0.1 1
CONDITIONS
MIN.
TYP.
MAX.
200 166 133 V DD VDD 125 90 65 2 10 2 1.7 1.7 55
UNITS
MHz
Vpp V pp MHz MHz MHz ms ns ms ns ns % ps
Period Jitter,Pk-to-Pk* With capacitive decoupling between V DD and (measured from 10,000 samples) GND. * Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 4

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Stand By Current, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive Output Current, Standard Drive Output Current, High Drive
SYMBOL
I DD I DD I DD I DD V DD V OL V OH I OSD I OSD I OHD
CONDITIONS
@ V DD =3.3V, 27MHz, load=15pF @ V DD =2.5V, 27MHz, load=15pF @ V DD =1.8V, 27MHz, load=15pF When PDB=0
MIN.
TYP.
5.5 3.8 1.8*
MAX.
UNITS
mA mA mA
<10 1.62 3.63 0.4 V DD – 0.4 4 8 16
A V V V mA mA mA
I OL = +4mA Standard Drive I OH = -4mA Standard Drive V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 5

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
LAYOUT RECOMMENDATIONS
DFN-6L Evaluation Board The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Multiple VDD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1μF for designs using crystals < 50MHz and 0.01μF for designs using crystals > 50MHz.
Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer
( Typical buffer impedance 20 ? ) 50? line
To CMOS Input
Series Resistor
Use value to match output buffer impedance to 50 ? trace. Typical value 30 ?
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 6

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load .
Crystal
Cst XIN 1 Cpt 8 Cpt XOUT
CST – Series Capacitor, used to lower circuit load to match crystal load . Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors , Used to raise the circuit load to match the crystal load. Lowers frequency offset .
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 7

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC
Pin1 Dot
E
H
D
A2 A A1 e b C L
DFN-6L
D1
Symbol A A1 A3 b e D E D1 E1 L
Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
b
e Pin 6 ID Chamfer E1 E
D
L Pin1 Dot A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 8

元器件交易网https://www.wendangku.net/doc/0a2062225.html,
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL TM Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range
PL611s-27-XXX X X X
PART NUMBER
3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L T=SOT23-6L Part/Order Number PL611s-27-XXXGC-R PL611s-27-XXXTC-R
?
NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking? XXX 27XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SOT23 (Tape and Reel)
Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at https://www.wendangku.net/doc/0a2062225.html,/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 https://www.wendangku.net/doc/0a2062225.html, Rev 2/25/07 Page 9