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HY57V651620BLTC-10中文资料

4 Banks x 1M x 16 Bit Synchronous DRAM

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

DESCRIPTION

The Hyundai HY57V651620 is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory appli-cations which require large memory density and high bandwidth. HY57V651620 is organized as 4banks of 1,048,576x16.

HY57V651620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

?Single 3.3V ??0.3V power supply

?All device pins are compatible with LVTTL interface ?

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch

All inputs and outputs referenced to positive edge of system clock

?Data mask function by UDQM, LDQM ?

Internal two banks operation

?Auto refresh and self refresh ?4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst

- 1, 2, 4 and 8 for Interleave Burst

?Programmable CAS Latency ; 1, 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power Organization Interface Package

HY57V651620TC-8125MHz Normal

4Banks x 1Mbits

x16

LVTTL

400mil 54pin TSOP II

HY57V651620TC-10100MHz HY57V651620TC-1283MHz HY57V651620LTC-8125MHz Low power

HY57V651620LTC-10100MHz HY57V651620LTC-12

83MHz

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock The system clock input. All other inputs are registerd to the SDRAM on the rising edge of CLK.

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh.

CS Chip Select Command input enable or mask except CLK, CKE and DQM BA0,BA11Bank Address Select either one of banks during both RAS and CAS activity.

A0 ~ A1Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10

RAS, CAS, WE Row Address Strobe, Col-

umn Address Strobe, Write

Enable

RAS, CAS and WE define the operation.

Refer function truth table for details

LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and masks input data in write mode DQ0 ~ DQ15Data Input/Output Multiplexed data input / output pin

V DD/V SS Power Supply/Ground Power supply for internal circuit and input buffer

V DDQ/V SSQ Data Output Power/Ground Power supply for DQ

NC No Connection No connection

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION (TA=0?é to 70?é)

Note :

1.All voltages are referenced to V SS = 0V

AC OPERATING CONDITION (TA=0?é to 70?é, V DD =3.3V ??0.3V, V SS =0V)

Note :

1. Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature T A 0 ~ 70?éStorage Temperature

T STG -55 ~ 125?éVoltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power Dissipation

P D 1W Soldering Temperature ?¤Time

T SOLDER

260?¤10

?é?¤ Sec

Parameter

Symbol Min Typ Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6V 1Input high voltage V IH 2.0 3.0V DD + 0.4

V 1Input low voltage

V IL

-0.3

0.8

Parameter

Symbol Value Unit Note

AC input high / low level voltage

V IH / V IL 2.4/0.4V Input timing measurement reference level voltage Vtrip 1.4V Input rise / fall time

tR / tF 1V/ns Output timing measurement reference level

Voutref 1.4V Output load capacitance for access time measurement CL

CAPACITANCE (TA=25?é, f=1MHz)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I (TA=0?é to 70?é, V DD =3.3V ??0.3V)

Note :

1.V IN = 0 to 3.6V, All other pins not under test = 0V

2.D OUT is disabled, V OUT =0 to

3.6V

Parameter

Symbol Min Max Unit Input capacitance

A0 ~ A11, BA0, BA1

C I125pF CLK, CKE, CS, RAS, CAS, WE, UDQM, LDQM

CI 225pF Data input / output capacitance

DQ0 ~ DQ15

C I/O

Parameter

Symbol

Min.Max Unit Note Input leakage current I LI -11uA 1Output leakage current I LO -11uA 2

Output high voltage V OH 2.4-V I OH

= -2mA Output low voltage

V OL

-0.4

I OL =+2mA

DC CHARACTERISTICS II (TA=0?é to 70?é, V DD =3.3V ??0.3V, V SS =0V)

Note :

1.I DD1 and I DD5 depend on output loading and cycle rates. Specified values are measured with the output open.3.HY57V651620TC-8/10/124.HY57V651620LTC-8/10/12

Paramter

Symbol

Test Condition

Speed

Unit

Note

-8

-10-12Operating Current

I DD1Burst Length=1, One bank active

tRAS ??tRAS(min),tRP ??tRP(min), IO=0mA 90

8570

Precharge Standby Current in power down mode

I DD2P CKE ??V IL (max), tCK = 15ns 2

I DD2PS

CKE ??V IL (max), tCK = ∞

Precharge Standby Current in non power down mode

I DD2N

CKE ??V IH (min), CS ??V IH (min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ??V DD -0.2V or ??0.2V 15

I DD2NS CKE ??V IH (min), tCK = ∞Input signals are stable.15Active Standby Current in power down mode

I DD3P CKE ??V IL (max), tCK = 15ns 5

I DD3PS

CKE ??V IL (max), tCK = ∞

Active Standby Current in non power down mode

I DD3N

CKE ??V IH (min), CS ??V IH (min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ??V DD -0.2V or ??0.2V 35

I DD3NS

CKE ??V IH (min), tCK = ∞Input signals are stable 35Burst Mode Operating Current

I DD4tCK ??tCK(min),

tRAS ??tRAS(min), IO=0mA All banks active

CL=31009080

CL=2

807060

Auto Refresh Current I DD5tRRC ??tRRC(min), All banks active 160mA 2Self Refresh Current

I DD6

CKE ??0.2V

2mA 3500

AC CHARACTERISTICS I

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns.

Paramter

Symbol

-8

-10

-12

Unit

Note

Min

Max

Min Max

System clock cycle time

CAS Latency = 3

tCK3

1000

CAS Latency = 2

tCK2121315ns Clock high pulse width tCHW 3-3-3-ns 1Clock low pulse width

tCLW 3-3

-3-ns 1

Access time from clock

CAS Latency = 3

tAC3

-6

-9

CAS Latency = 2

tAC2-68-9ns Data-out hold time tOH 3-3-3-ns Data-Input setup time tDS 2-3-3-ns 1Data-Input hold time tDH 1-1-1-ns 1Address setup time tAS 2-3-3-ns 1Address hold time tAH 1-1-1-ns 1CKE setup time tCKS 2-2-3-ns 1CKE hold time tCKH 1-1-1-ns 1Command setup time tCS 2-2-3-ns 1Command hold time

tCH 1-1-1-ns 1

CLK to data output in low Z-time tOLZ 1-1-1-ns CLK to data output in high Z-time

CAS Latency = 3tOHZ3-6-8-9ns CAS Latency = 2

tOHZ2

-6

-8

-9

AC CHARACTERISTICS II

Paramter Symbol

-8-10-12

Unit Note Min Max Min Max Min Max

RAS cycle time Operation tRC72-80-90-ns Auto Refresh tRRC96-96-96-ns RAS to CAS delay tRCD20-24-30-ns RAS active time tRAS48100K50100K60100K ns RAS precharge time tRP24-30-30-ns RAS to RAS bank active delay tRRD16-20-24-ns CAS to CAS delay tCCD1-1-1-CLK Write command to data-in delay tWTL0-0-0-CLK Data-in to precharge command tDPL1-1-1-CLK Data-in to active command tDAL4-4-4-CLK DQM to data-out Hi-Z tDQZ2-2-2-CLK DQM to data-in mask tDQM0-0-0-CLK MRS to new command tMRD2-2-2-CLK

Precharge to data output Hi-Z CAS Latency = 3tPROZ33-3-3-CLK CAS Latency = 2tPROZ22-2-2-CLK

Power down exit time tPDE1-1-1-CLK Self refresh exit time tSRE1-1-1-CLK Refresh Time tREF64-64-64-ms

DEVICE OPERATING OPTION TABLE

HY57V651620TC-8

HY57V651620TC-10

HY57V651620TC-12

CAS Latency

tRCD tRAS tRC tRP tAC tOH 125MHz 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz 3CLKs 2CLKs 5CLKs 8CLKs 3CLKs 6ns 3ns 83MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns 66MHz

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz 3CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 83MHz 2CLKs 2CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 66MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 8ns 3ns 50MHz

2CLKs

3CLKs

5CLKs

2CLKs

8ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 83MHz 2CLKs 3CLKs 5CLKs 8CLKs 3CLKs 9ns 3ns 66MHz 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 9ns 3ns 50MHz 2CLKs 2CLKs 3CLKs 5CLKs 2CLKs 9ns 3ns 33MHz

2CLKs

1CLK

2CLKs

3CLKs

1CLK

9ns

3ns

COMMAND TRUTH TABLE

Note :

V = Valid, X = Dont care, H = Logic High, L= Logic Low.

Command

CKEn-1CKEn CS RAS CAS WE DQM ADDR

A10/AP BA Note

Mode Register Set H X L L L L X

OP code

No Operation H X

H H H Bank Active H

Read

V Read with Autoprecharge H Write

Write with Autoprecharge H Precharge All Bank

Precharge selected Bank L V

Burst Stop H X

H H

X X UDQM, LDQM H X V X Auto Refresh

H H L L L H X X

Self Refresh

Entry

L L L H X

Exit

L H H H Precharge power down

Entry

L H H H

Exit

L H H H Clock Suspend

Entry H L

Exit