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MB15F02SLPFV1中文资料

DS04-21356-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual Serial Input

PLL Frequency Synthesizer

MB15F02SL

s DESCRIPTION

The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a 500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation.

The supply voltage range is between 2.4 V and 3.6 V . The MB15F02SL uses the latest BiCMOS process. As a result,the supply current is typically 3 mA at 2.7 V . A refined charge pump supplies a well-balanced output current of 1.5mA or 6 mA. The charge pump current is selectable by serial data.

MB15F02SL is ideally suited for wireless mobile communications, such as GSM and PDC.

s FEATURES

?High frequency operation:RF synthesizer: 1200 MHz max

IF synthesizer: 500 MHz max

?Low power supply voltage: V CC = 2.4 to 3.6 V

?Ultra Low power supply current:I CC = 3.0 mA typ. (V CC = 2.7 V, Ta = +25°C, in IF, RF locking state)

I CC = 3.5 mA typ. (V CC = 3.0 V, Ta = +25°C, in IF, RF locking state)

?Direct power saving function:Power supply current in power saving mode

Typ. 0.1 μA (V CC = 3.0 V, Ta = +25°C), Max. 10 μA (V CC = 3.0 V)

?Dual modulus prescaler: 1200 MHz prescaler (64/65, 128/129)/500 MHz prescaler (8/9 or 16/17)?Serial input 14-bit programmable reference divider: R = 3 to 16,383?Serial input programmable divider consisting of:- Binary 7-bit swallow counter: 0 to 127

- Binary 11-bit programmable counter: 3 to 2,047?Software selectable charge pump current ?On-chip phase control for phase comparator ?Operating temperature: Ta = –40 to +85°C

MB15F02SLPFV1中文资料

MB15F02SL s PIN ASSIGNMENTS

MB15F02SLPFV1中文资料

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MB15F02SL

s PIN DESCRIPTIONS

Pin no.Pin

name I/O Descriptions

SSOP-16BCC-16

116GND RF–Ground for RF-PLL section.

21OSC IN I The programmable reference divider input. TCXO should be connected

with a AC coupling capacitor.

32GND IF–Ground for the IF-PLL section.

43fin IF I Prescaler input pin for the IF-PLL.

Connection to an external VCO should be via AC coupling.

54V CCIF–Power supply voltage input pin for the IF-PLL section.

65LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout).

The output signal is selected by LDS bit in a serial data. LDS bit = “H” ; outputs fout signal

LDS bit = “L” ; outputs LD signal

76PS IF I Power saving mode control for the IF-PLL section. This pin must be set at “L” during Power-ON. (Open is prohibited.)

PS IF = “H” ; Normal mode

PS IF = “L” ; Power saving mode

87Do IF O Charge pump output for the IF-PLL section.

Phase characteristics of the phase detector can be selected via programming of the FC-bit.

98Do RF O Charge pump output for the RF-PLL section.

Phase characteristics of the phase detector can be selected via programming of the FC-bit.

109PS RF I Power saving mode control for the RF-PLL section. This pin must be set at “L” during Power-ON. (Open is prohibited.)

PS RF = “H” ; Normal mode

PS RF = “L” ; Power saving mode

1110Xfin RF I Prescaler complementary input for the RF-PLL section.

This pin should be grounded via a capacitor.

1211V CCRF–Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RF-PLL is lost.

1312fin RF I Prescaler input pin for the RF-PLL.

Connection to an external VCO should be via AC coupling.

1413LE I Load enable signal inpunt (with a schmitt trigger input buffer.)

When the LE bit is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data.

1514Data I Serial data input (with a schmitt trigger input buffer.)

Data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in the serial data.

1615Clock I Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)

One bit of data is shifted into the shift register on a rising edge of the clock.

3

MB15F02SL s BLOCK DIAGRAM

MB15F02SLPFV1中文资料

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5

MB15F02SL

s ABSOLUTE MAXIMUM RATINGS

WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

s RECOMMENDED OPERATING CONDITIONS

WARNING:The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

Parameter

Symbol Rating Unit Remark

Min.Max.Power supply voltage V CC –0.5 +4.0V Input voltage V I –0.5V CC +0.5V Output voltage V O GND V CC V Storage temperature

Tstg

–55

+125

°C

Parameter

Symbol Value

Unit Remark

Min.Typ.Max.Power supply voltage V CC 2.4 3.0 3.6V Input voltage

V I GND –V CC V Operating temperature

Ta

–40

+85

°C

6

MB15F02SL

s ELECTRICAL CHARACTERISTICS

(V CC = 2.4 V to 3.6 V , T a = –40 to +85°C)

(Continued)

Parameter

Symbol Condition

Value

Unit Min.Typ.Max.Power supply current*1

I CCIF *1

fin IF = 500 MHz, V CCIF = 2.7 V (V CCIF = 3.0 V)

– 1.2(1.5)–mA I CCRF *1

fin RF = 1200 MHz, V CCRF = 2.7 V (V CCRF = 3.0 V)– 1.8(2.0)–mA Power saving current

I PSIF PS IF = PS RF = “L”–0.1*210μA I PSRF PS IF = PS RF = “L”–0.1*210μA Operating frequency

fin IF *3

fin IF IF PLL 50–500MHz fin RF *3fin RF RF PLL

100–1200MHz OSC IN fosc –

3–40MHz Input sensitivity

fin IF *8

Pfin IF IF PLL, 50 ? system –15

–+2dBm fin RF Pfin RF RF PLL, 50 ? system

–15–

+2dBm OSC IN

V OSC –

0.5V CC Vp-p “H” level input voltage Data,Clock,LE V IH Schmitt trigger input V CC ×0.7 + 0.4

––V

“L” level input voltage V IL Schmitt trigger input

––V CC × 0.3 – 0.4

“H” level input voltage PS IF ,PS RF

V IH –V CC × 0.7

––V

“L” level input voltage V IL –––V CC × 0.3“H” level input current

Data,Clock,LE,

PS IF , PS RF I IH *4––1.0–+1.0μA

“L” level input current I

IL *4

––1.0–+1.0“H” level input current OSC IN

I IH –0–+100μA

“L” level input current I IL *4–

–100–0“H” level output voltage LD/fout

V OH

V CC = 3.0 V , I OH = –1 mA V CC – 0.4

––

V

“L” level output voltage V OL

V CC = 3.0 V , I OL = 1 mA ––0.4“H” level output voltage Do IF Do RF V DOH V CC = 3.0 V , I DOH = –0.5 mA V CC – 0.4

––

V

“L” level output voltage

V DOL V CC = 3.0 V , I DOL = 0.5 mA ––0.4High impedance cutoff current

Do IF Do RF I OFF V CC = 3.0 V ,

V OFF = 0.5 V to V CC – 0.5 V –– 2.5nA

“H” level output current LD/fout

I OH *4

V CC = 3.0 V –––1.0

mA “L” level output current

I OL *4

V CC = 3.0 V

1.0

––

7

MB15F02SL

(Continued)

(V CC = 2.4 to 3.6 V , T a = –40 to +85°C)

*1:Conditions; fosc = 12 MHz, T a = +25°C, in locking state.

*2:V CCIF = V CCRF = 3.0 V , fosc = 12.8 MHz, T a = +25°C, in power saving mode.

*3:AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.*4:The symbol “–” (minus) means direction of current flow.*5:V CC = 3.0 V , T a = +25°C (|I 3| – |I 4|)/[(|I 3| + |I 4|)/2] × 100(%)

*6:V CC = 3.0 V , T a = +25°C [(|I 2| – |I 1|)/2]/[(|I 1| + |I 2|)/2] × 100(%) (Applied to each I DOL , I DOH )

*7:V CC = 3.0 V , [|I DO(+85°C) – I DO(–40°C)|/2]/[|I DO(+85°C) + I DO(–40°C)|/2] × 100(%) (Applied to each I DOL , I DOH )*8:

Prescaler divided ratio Charge pump current fin IF Vfin IF (min)

16/17 1.5 mA mode 50 MHz fin 500 MHz –15 dBm

6.0 mA mode 50 MHz fin 300 MHz –15 dBm

300 MHz < fin 500 MHz –10 dBm

8/9 1.5 mA mode 50 MHz fin 300 MHz*–15 dBm

300 MHz < fin 500 MHz –15 dBm

6.0 mA mode 50 MHz fin 300 MHz*–15 dBm

300 MHz < fin 500 MHz –10 dBm

* : V CC = 2.7 V to 3.6 V at 500 MHz,

V CC = 2.4 V to 3.6 V , T a = –40

MB15F02SLPFV1中文资料

°C to +85°C at fin < 500 MHz

Parameter

Symbol Condition

Value

Unit

Min.Typ.Max.“H” level output current

Do IF Do RF

I DOH

*4

V CC = 3.0 V ,V DOH = V CC /2,

T a = +25°C CS bit = “H”––6.0–mA CS bit = “L”––1.5–“L” level output current

I DOL V CC = 3.0 V ,

V DOL = V CC /2,T a = +25°C CS bit = “H”– 6.0–CS bit = “L”

– 1.5–Charge pump current rate

I DOL /I DOH

I DOMT *5V DO = V CC /2

–3–%vs V DO I DOVD *60.5 V ≤ V DO ≤ V CC – 0.5 V –10–%vs Ta

I DOTA *7–40°C ≤ Ta ≤ +85°C,V DO = V CC /2

10

%

8

MB15F02SL

s FUNCTIONAL DESCRIPTION

The divide ratio can be calculated using the following equation:

f VCO = {(M × N) + A} × f OSC ÷ R (A < N)f VCO :Output frequency of external voltage controlled oscillator (VCO)M :Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)N :Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)A :Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)f OSC :Reference oscillation frequency R :Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

Serial Data Input

Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.Serial data of binary data is entered through Data pin.

On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.

Table 1. Control Bit

Shift Register Configuration

Control bit Destination of serial data

CN1CN2L L The programmable reference counter for the IF-PLL H L The programmable reference counter for the RF-PLL

L H The programmable counter and the swallow counter for the IF-PLL H

H

The programmable counter and the swallow counter for the RF-PLL

Programmable Reference Counter

MSB

Data Flow

CN1,2: Control bit [T able 1]R1 to R14: Divide ratio setting bits for the programmable reference counter (3 to 16,383)[T able 2]T1, 2: T est purpose bit [T able 3]CS : Charge pump currnet select bit [T able 9]X : Dummy bits (Set “0” or “1”)

NOTE: Data input with MSB first.

1234567891011121314151617181920212223C N 1

C N 2

T 1

T 2

R 1

R 2

R 3

R 4

R 5

R 6

R 7

R 8

R 9

R 10R 11R 12R 13R 14

C S

X X X X

LSB

9

MB15F02SL

Table 2. Binary 14-bit Programmable Reference Counter Data Setting

Note: Divide ratio less than 3 is prohibited.

Table 3. Test Purpose Bit Setting

Divide ratio

(R)

R14R13R12R11R10R9R8R7R6R5R4R3R2R1300000000000011400000000000100???????????????16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

T1T2LD/fout pin state L L Outputs fr IF .H L Outputs fr RF .L H Outputs fp IF .H

H

Outputs fp RF .

Programmable Counter

LSB

MSB

Data Flow

CN1, CN2: Control bit

[T able 1]N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)[T able 4]A1 to A7: Divide ratio setting bits for the swallow counter (0 to 127)[T able 5]SW IF /SW RF : Divide ratio setting bit for the prescaler

[T able 6] (8/9 or 16/17 for the SW IF , 64/65 or 128/129 for the SW RF )FC IF /FC RF : Phase control bit for the phase detector (IF: FC IF , RF: FC RF )[T able 7]LDS

: LD/fout signal select bit

[T able 8]

NOTE: Data input with MSB first.

1234567891011121314151617181920212223

CN1CN2LDS

SW IF /SW RF FC IF /

FC RF

A1A2A3A4A5A6A7N1N2N3N4N5N6N7N8N9N10N11

10

MB15F02SL

Table 4. Binary 11-bit Programmable Counter Data Setting

Note: Divide ratio less than 3 is prohibited.

Table 5. Binary 7-bit Swallow Counter Data Setting

Note: Divide ratio (A) range = 0 to 127

Table 6. Prescaler Data Setting

Table 7. Phase Comparator Phase Switching Data Setting

Note:? Z = High-impedance

? Depending upon the VCO and LPF polarity, FC bit should be set.

Table 8. LD/fout Output Select Data Setting

Divide ratio

(N)

N11N10N9N8N7N6N5N4N3N2N1300000000011400000000100????????????2047

1

1

1

1

1

1

1

1

MB15F02SLPFV1中文资料

1

1

1

Divide ratio

(A)

A7A6A5A4A3A2A10000000010000001????????127

1

1

1

1

1

1

1

SW = “H”

SW = “L”Prescaler divide ratio

IF-PLL 8/916/17RF-PLL

64/65

128/129

FC IF, FC RF = “H”

FC IF , FC RF = “L”

Do IF, Do RF

fr > fp H L fr = fp Z Z fr < fp L H VCO polarity

(1)

(2)

LDS LD/fout output signal

H fout

(fr IF /fr RF , fp IF /fp RF ) signals

L

LD signal

MB15F02SL

Table 9. Charge Pump Current Setting

CS Current value

H±6.0 mA

L±1.5 mA

Power Saving Mode (Intermittent Mode Control Circuit)

Table 10. PS Pin Setting

PS pin Status

H Normal mode

L Power saving mode

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.

Setting the PS pin high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.

T o prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation.

Note:? When power (V CC) is first applied, the device must be in standby mode, PS = Low, for at least 1 μs.

? PS pin must be set at “L” for Power-ON.

MB15F02SLPFV1中文资料

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MB15F02SL

s SERIAL DATA INPUT TIMING

MB15F02SLPFV1中文资料

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MB15F02SL s PHASE COMPARATOR OUTPUT WAVEFORM

MB15F02SLPFV1中文资料

N otes:?Phase error detection range = –2π to +2π

?Pulses on Do IF/RF signals are output to prevent dead zone.

?LD output becomes low when phase error is t WU or more.

?LD output becomes high when phase error is t WL or less and continues to be so for three cycles or more.

?t WU and t WL depend on OSC IN input frequency as follows.

t WU > 2/fosc: i. e. t WU > 156.3 ns when fosc = 12.8 MHz

t WU < 4/fosc: i. e. t WL < 312.5 ns when fosc = 12.8 MHz

13

MB15F02SL

s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSC IN)

MB15F02SLPFV1中文资料

14

MB15F02SL

s TYPICAL CHARACTERISTICS

1. fin input impedance

MB15F02SLPFV1中文资料

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MB15F02SL

2.OSC IN input sensitivity

MB15F02SLPFV1中文资料

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MB15F02SL 3. Do output current (RF-PLL)

MB15F02SLPFV1中文资料

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MB15F02SL

4.Do output current (IF-PLL)

MB15F02SLPFV1中文资料

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MB15F02SL 5.fin input impedance

MB15F02SLPFV1中文资料

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