NAND02GW3B2DN6E
Preliminary Data
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
April 2008 Rev 31/69
NAND02G-B2D
2-Gbit, 2112-byte/1056-word page
multiplane architecture, 1.8 V or 3 V , NAND flash memories
Features
■
High density NAND flash memory –Up to 2 Gbits of memory array
–Cost-effective solution for mass storage applications ■
NAND interface
–x8 or x16 bus width
–Multiplexed address/data ■Supply voltage: 1.8 V or 3.0 V device ■
Page size
–x8 device: (2048 + 64 spare) bytes –x16 device: (1024 + 32 spare) words ■
Block size
–x8 device: (128K + 4K spare) bytes –x16 device: (64K + 2K spare) words ■
Multiplane architecture
–Array split into two independent planes –Program/erase operations can be
performed on both planes at the same time ■
Page read/program
–Random access: 25μs (max)–Sequential access: 25ns (min)–Page program time: 200μs (typ)
–Multiplane page program time (2 pages): 200μs (typ)■
Copy back program with automatic EDC (error detection code)■Cache read mode
■
Fast block erase
–Block erase time: 1.5ms (typ)
–Multiblock erase time (2 blocks): 1.5ms (typ)
■Status register ■Electronic signature ■Chip Enable ‘don’t care’■Serial number option
■
Data protection:
–Hardware program/erase disabled during power transitions
–Non-volatile protection option ■ONFI 1.0 compliant command set
■
Data integrity
–100,000 program/erase cycles (with ECC)–10 years data retention ■
ECOPACK ? packages
Table 1.
Device summary
Reference
Part number NAND02G-B2D
NAND02GR3B2D
NAND02GW3B2D NAND02GR4B2D (1)1.x 16 organization only available for MCP products.
NAND02GW4B2D
(1)
https://www.wendangku.net/doc/093376265.html,
Contents NAND02G-B2D
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Contents
1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.6Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.7Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.8Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.9Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.10V DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.11
V SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.3Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.4Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.5Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.6
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216.1.2
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NAND02G-B2D Contents
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6.3Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.2Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.9Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11.1Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11.2P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 36
6.11.3P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.4Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.5SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.12Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.13Read EDC status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.14Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.15Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.16Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.4Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.5Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48 10Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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11DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 6311.2
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6513Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6714
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
NAND02G-B2D List of tables
5/69 List of tables
Table 1.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2.Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5.Address insertion (x8 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6.Address insertion (x16 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7.Address definition (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8.Address definition (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table https://www.wendangku.net/doc/093376265.html,mands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10.Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11.Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12.Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13.EDC status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14.Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15.Electronic signature byte 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 16.Electronic signature byte 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 17.Electronic signature byte 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 18.Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 19.Parameter page data structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 20.Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 21.Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48 Table 22.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 23.Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 24.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 25.DC characteristics (1.8V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 26.DC characteristics (3V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 27.AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 28.AC Characteristics for operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 29.TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65 Table 30.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 31.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 32.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
List of figures NAND02G-B2D
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List of figures
Figure 1.Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 2.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 3.TSOP48 connections for NAND02G-B2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 4.VFBGA63 connections for NAND02G-B2D devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5.Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 6.Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 7.Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 8.Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 9.Cache read (random) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 10.Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 11.Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 12.Multiplane page program waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 13.Copy back program (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 14.Copy back program (with readout of data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 15.Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 16.Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 17.Block erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 18.Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 19.Page organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 20.Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 21.Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 22.Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 23.Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 51Figure https://www.wendangku.net/doc/093376265.html,mand latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 25.Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 26.Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 27.Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 28.Sequential data output after read AC waveforms (EDO mode) . . . . . . . . . . . . . . . . . . . . . 56Figure 29.Read Status register or read EDC Status register AC waveform. . . . . . . . . . . . . . . . . . . . 57Figure 30.Read status enhanced waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 31.Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 32.Read ONFI signature waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 33.Page read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Figure 34.Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 35.Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 36.Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 37.Program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 38.Program/erase disable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 39.Read parameter page waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 40.Ready/busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 41.Ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 42.Resistor value versus waveform timings for ready/busy signal . . . . . . . . . . . . . . . . . . . . . 64Figure 43.Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 44.TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 65Figure 45.
VFBGA63 9.5x 12mm - 6x 8 active ball array, 0.80mm pitch, package outline . . . . . . . 66
NAND02G-B2D Description
7/69 1 Description
The NAND02G-B2D devices are part of the NAND flash 2112-byte/1056-word page family
of non-volatile flash memories. They use NAND cell technology and have a density of
2Gbits.
These devices have a memory array that is split into 2 planes of 1024 blocks each. This
multiplane architecture makes it possible to program 2 pages at a time (one in each plane),
or to erase 2 blocks at a time (one in each plane). This feature reduces the average program
and erase times by 50%.
The NAND02G-B2D devices operate from a 1.8 V or 3 V voltage supply. Depending on
whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare)
or 1056 words (1024 + 32 spare), respectively.
The address lines are multiplexed with the data input/output signals on a multiplexed x8
input/output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles with ECC (error correction
code) on. T o extend the lifetime of NAND flash devices, the implementation of an ECC is
mandatory.
A write protect pin is available to provide hardware protection against program and erase
operations.
The devices feature an open-drain ready/busy output that identifies if the P/E/R
(program/erase/read) controller is currently active. The use of an open-drain output allows
the ready/busy pins from several memories to connect to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a page program operation fails, the data can be programmed in another page
without having to resend the data to be programmed. An embedded error detection code is
automatically executed after each copy back operation: 1 error bit can be detected for every
528bits. With this feature it is no longer necessary to use an external 2-bit ECC to detect
copy back operation errors.
The devices have a cache read feature that improves the read throughput for large files.
During cache reading, the device loads the data in a Cache register while the previous data
is transferred to the I/O buffers to be read.
The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly
downloaded by a microcontroller. This is possible because Chip Enable transitions during
the latency time do not stop the read operation.
The NAND02G-B2D devices support the ONFI 1.0 specification.
Description
NAND02G-B2D
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Two further features are available as options:
●Extra non-volatile protection
●
An individual serial number that acts as an unique identifier.
More information is available, upon completion of an NDA (non-disclosure agreement), and are, therefore, not described in this datasheet. For more details of this option contact your nearest Numonyx sales office.
The devices are available in the TSOP48 (12x 20mm) and VFBGA63 (9.5x 12mm) packages.
For information on how to order these options, refer to T able 31: Ordering information scheme . Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’1’.
Table 2: Product description lists the part numbers and other information for all the devices in the family.
Table 2.
Product description
Part number
Density
Bus width
Page size
Block size
Memory array Operating
voltage
Timings
Package
Sequential access time (min)Random access time (max)Page Program (typ)Block Erase (typ)
NAND02GR3B2D
2Gb
x8
2048+64bytes
128K+4K bytes
64 pages x 2048 blocks
1.7 to
1.95V
45ns 25μs
200μs
1.5ms
VFBGA63
NAND02GW3B2D
2.7 to
3.6V 25ns
TSOP48VFBGA63 NAND02GR4B2D
x16
1024+ 32words
64K+2K words
1.7 to 1.95V 45ns NAND02GW4B2D
2.7 to
3.6V
25ns
NAND02G-B2D Description
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Description
NAND02G-B2D
10/69
Table 3.
Signal names
Signal Function
Direction I/O0-7Data input/outputs, address inputs, or command inputs (x8/x16 devices)
Input/output I/O8-15Data input/outputs (x16 devices)Input/output AL Address Latch Enable Input CL Command Latch Enable Input E Chip Enable Input R Read Enable
Input RB Ready/Busy (open-drain output)Output W Write Enable Input WP Write Protect Input V DD Supply voltage Power supply V SS Ground
Ground NC Not connected internally N/A DU
Do not use
N/A
NAND02G-B2D Description
11/69
Description
NAND02G-B2D
12/69
NAND02G-B2D Memory array organization
13/69 2 Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series. It
is organized into blocks where each block contains 64 pages. The array is split into two
areas, the main area and the spare area. The main area of the array is used to store data,
and the spare area typically stores error correction codes, software flag, or bad block
identification.
In x8 devices, the pages are split into a 2048-byte main area and a spare area of 64bytes.
In x16 devices, the pages are split into a 1024-word main area and a spare area of
32words. Refer to Figure5: Memory array organization.
Bad blocks
In the x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad
blocks, which are blocks that contain one or more invalid bits whose reliability is not
guaranteed. Additional bad blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section8.1: Bad block
management for more details).
There are a minimum of 2008 and a maximum of 2048 valid blocks. These numbers include
both the bad blocks that are present when the device is shipped and the bad blocks that
could develop later on.
These blocks need to be managed using bad blocks management, block replacement, or
error correction codes (refer to Section8: Software algorithms).
Memory array organization NAND02G-B2D
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NAND02G-B2D Signal descriptions
15/69 3 Signal
descriptions
See Figure2: Logic diagram, and T able3: Signal names for a brief overview of the signals
connected to this device.
3.1 Inputs/outputs
(I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2 Inputs/outputs
(I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3 Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4 Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5
sense amplifiers. When Chip Enable is Low, V IL, the device is selected. If Chip Enable goes
High, V IH, while the device is busy, the device remains selected and does not go into
standby mode.
3.6
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid t RLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
Signal descriptions NAND02G-B2D
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3.7 data latches. Both addresses and data are latched on the rising edge of Write Enable.During power-up and power-down a recovery time of 10μs (min) is required before the command interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.
3.8 Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, V IL , the device does not accept any program or erase operations.
It is recommended to keep the Write Protect pin Low, V IL , during power-up and power-down.
3.9 Ready/Busy (RB)
P/E/R controller is currently active.
When Ready/Busy is Low, V OL , a read, program or erase operation is in progress. When the operation completes, Ready/Busy goes High, V OH .
The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low then indicates that one or more of the memories is busy.
During power-up and power-down a minimum recovery time of 10μs is required before the V OL .
Refer to Section 11.1: Ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor.
3.10 V DD supply voltage
V DD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V DD is below V LKO (see
Table 26) to protect the device from any involuntary program/erase during power transitions.Each device in a system should have V DD decoupled with a 0.1μF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents.
3.11 V SS ground
Ground, V SS, is the reference for the power supply. It must be connected to the system ground.
NAND02G-B2D Bus operations
17/69 4 Bus
operations
There are six standard bus operations that control the memory, as described in this section.
See Table4: Bus operations for a summary of these operations.
Typically, glitches of less than 5ns on Chip Enable, Write Enable, and Read Enable are
ignored by the memory and do not affect bus operations.
4.1 Command
input
Command input bus operations give commands to the memory.
Commands are accepted when Chip Enable is Low, Command Latch Enable is High,
Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge
of the Write Enable signal.
Only I/O0 to I/O7 input commands.
See Figure24 and T able27 for details of the timings requirements.
4.2 Address
input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to Table5: Address insertion (x8 devices) and T able6: Address
insertion (x16 devices)).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input addresses.
See Figure25 and T able27 for details of the timings requirements.
4.3 Data
input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure26 and T able27 and Table28 for details of the timings requirements.
4.4 Data
output
Data output bus operations read the data in the memory array, the Status register, the
electronic signature,and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
Bus operations NAND02G-B2D
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If the Read Enable pulse frequency is lower then 33MHz (t RLRL higher than 30ns), the output data is latched on the rising edge of Read Enable signal (see Figure 27).
For higher frequencies (t RLRL lower than 30ns), the EDO (extended data out) mode must be used. In this mode, Data Output bus operations are valid on the input/output bus for a time of t RLQX after the falling edge of Read Enable signal (see Figure 28).See Table 28 for details on the timings requirements.
4.5 Write protect
Write protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low, the device does not accept program or erase operations, and, therefore, the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6 Standby
When Chip Enable is High the memory enters standby mode, the device is deselected, outputs are disabled, and power consumption is reduced.
Table 4.
Bus operations
Bus operation E AL CL R W WP I/O0 - I/O7I/O8 - I/O15(1)
1.Only for x 16 devices.
Command input V IL V IL V IH V IH Rising X (2)2.WP must be V IH when issuing a Program or Erase command.
Command X Address input V IL V IH V IL V IH Rising X Address X Data input V IL V IL V IL V IH Rising V IH Data input Data input Data output V IL V IL V IL Falling V IH X Data output
Data output
Write protect X X X X X V IL X X Standby
V IH
X
X
X
X
V IL /V DD
X
X
Table 5.
Address insertion (x 8 devices)
Bus cycle (1)1.Any additional address input cycles are ignored.
I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O01st A7A6A5A4A3A2A1A02nd V IL V IL V IL V IL A11A10A9A83rd A19A18A17A16A15A14A13A124th A27A26A25A24A23A22A21A205th
V IL
V IL
V IL
V IL
V IL
V IL
V IL
A28
NAND02G-B2D Bus operations
19/69 Table 6.Address insertion (x16 devices)
Bus
cycle(1)
1.Any additional address input cycles are ignored.
I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0 1st A7A6A5A4A3A2A1A0 2nd V IL V IL V IL V IL V IL A10A9A8 3rd A18A17A16A15A14A13A12A11 4th A26A25A24A23A22A21A20A19 5th V IL V IL V IL V IL V IL V IL V IL A27 Table 7.Address definition (x8 devices)
Address Definition
A0 - A11Column address
A12 - A17Page address
A18 - A28Block address
A18 = 0First plane
A18 = 1Second plane
Table 8.Address definition (x16 devices)
Address Definition
A0 - A10Column address
A11 - A16Page address
A17 - A27Block address
A17 = 0First plane
A17 = 1Second plane
Command set NAND02G-B2D
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5 Command set
All bus write operations sent to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal is High. Device operations are selected by writing specific commands to the Command register. The two-step command sequences for program and erase operations are imposed to maximize data security.Table 9 summarizes the commands.
Table 9.
Commands
Command
(1)
https://www.wendangku.net/doc/093376265.html,mands in bold are referring to ONFI 1.0 specifications.Bus write operations
Commands accepted during busy
1st cycle 2nd cycle 3rd cycle
4th cycle
Read
00h 30h ––Random Data Output 05h E0h ––Cache Read (sequential)31h –––Enhanced Cache Read (random)00h 31h ––Exit Cache Read 3Fh –––Y es (2)
2.Only during cache read busy.
Page Program
(sequential input default)80h 10h ––Random Data Input 85h –––Multiplane Page Program (3)80h 11h 81h 10h Multiplane Page Program 80h 11h 80h 10h Copy Back Read 00h 35h ––Copy Back Program
85h 10h ––Multiplane Copy Back Program (3)https://www.wendangku.net/doc/093376265.html,mand maintained for backward compatibility.
85h 11h 81h 10h Multiplane Copy Back Program 85h 11h 85h 10h Block Erase
60h D0h ––Multiplane Block Erase (3)60h 60h D0h –Multiplane Block Erase 60h D1h 60h D0h Reset
FFh –––Y es
Read Electronic Signature 90h –––Read Status register 70h –––Y es Read Status Enhanced 78h –––Y es
Read Parameter Page ECh –––Read EDC Status register
7Bh
–
–
–