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M070WSB50-09L-120-3.5-NT-V1.0

P RODUCT S PECIFICATION M ODEL:M070WSB50-09L

<◇>P RELIMINARY S PECIFICATION

<◆>A PPROVAL S PECIFICATION

C USTOMER

A PPROVED BY

D ATE:

D ESIGNED C HECKED A PPROVED

P REPAREDBY:

S HENZHEN X IAN C HUANG T ECHNOLOGY C O.,L TD

D AFU I NDUSTRIAL Z ON

E L ONGHUA D ISTRICT S HENZHEN C ITY G UANLAN S TREET LONGITUDINAL ROAD

S ILICON V ALLEY P OWER N EW M ATERIAL I NDUSTRIAL P ARK BUILDING A11

Version Revise Date Page Content Modified by

V1.0 2015.02.05 - First

Issued. ChenQi

T ABLE OF C ONTENTS

N O. C ONTENTS P AGE

REVISION STATUS (2)

TABLE OF CONTENTS (3)

1. GENERAL DESCRIPTION (4)

2. MECHANICAL SPECIFICATION (5)

3. PIN DESCRIPTION (6)

4. ELECTRICAL CHARACTERISTICS (8)

5.INPUT SIGNAL TIMING (13)

6. OPTICAL CHARACTERISTICS (16)

7.QUALITY ASSURANCE SYSTEM (19)

8. PRECAUTION RELATING PRODUCT HANDLING (20)

9. PACKAGE DRAWING (21)

1.G ENERAL D ESCRIPTION

1.1D ESCRIPTION

M070WSB50-09L is a color active matrix thin film transistor (TFT) TN liquid crystal display

(LCD) that uses amorphous silicon TFT as a switching device. It is composed of a TFT LCD

panel, Driver IC ,FPC and Backlight.

1.2F EATURES:

No. Item Specification Unit

1 Panel

Size 7” inch

2 Number of Pixels 1024×RGB (3) ×600 pixels

3 Active Area 154.21(H)x 85.92(V) mm

4 Pixel

Pitch 0.1506(H)×0.1432(V) mm

5 Outline Dimension 165(W) x 100(H) x3.5(D) mm

Colors 16.7M -

6 Number

7 Display Mode Normally White -

Direction 6o’clock -

8 Viewing

9 Pixel Arrangement RGB vertical stripe -

10 Luminance

(cd/m^2) 120(TYP.) nit

Ratio 600(TYP.)

11 Contrast

Treatment Anti-glare -

12 Surface

13 Interface TTL -

LED -

14 Backlight White

Temperature -10~50 ℃

15 Operation

16 Storage

Temperature -20~60 ℃

17 Weight TBD g

2.M ECHANICAL S PECIFICATION

3.P IN D ESCRIPTION

FPC Connector is used for the module electronics interface. The recommended model is FH12A-50S-0.5SH manufactured by Hirose.

No. Symbol Function Remark

1 A Power for LED backlight (Anode)

2 A Power for LED backlight (Anode)

3 K Power for LED backlight (Cathode)

4 K Power for LED backlight (Cathode)

ground

5 GND Power

voltage

6 VCOM Common

Power

7 VDD Digital

8 MODE DE/SYNC mode select. Normally pull high Note1

Input

Enable

9 DE Data

10 VS Vertical sync input. Negative polarity

11 HS Horizontal sync input. Negative polarity

data(MSB)

12 B7 Blue

data

13 B6 Blue

data

14 B5 Blue

data

15 B4 Blue

16 B3 Blue

data

17 B2 Blue

data

18 B1 Blue

19 B0 Blue

data(LSB)

data(MSB)

20 G7 Green

21 G6 Green

data

22 G5 Green

data

23 G4 Green

data

24 G3 Green

data

25 G2 Green

data

26 G1 Green

data(LSB)

27 G0 Green

data(MSB)

28 R7 Red

data

29 R6 Red

data

30 R5 Red

data

31 R4 Red

data

32 R3 Red

data

33 R2 Red

data

34 R1 Red

data(LSB)

35 R0 Red

Ground

36 GND Power

input

37 DCLK Clock

Ground

38 GND Power

No No No No

No Re No 39

40 41 42 43 44 45 46 47 48 49 50

ote: I/O de I---Inpu ote1：DE/S H:DE L:HS ote2：Glob rese ote3：H: n ote4：U/D Sc UPDN GND VDD GND VDD ote5：Defi efer to the ote6：Dith DIT L/R UPDN VGH VGL AVDD RESET NC VCOM DITH GND NC NC

efinition.

ut pin, O--SYNC mode E mode. SD/VSD mo bal reset pi et circuit fo normal ope R/L Funct can Contro N nition of s e figure as hering setti TH="L" 6bit --Output pi e select .n ode in. Active l or stability eration, L: tion Descri ol Input

SHL VDD GND GND VDD scanning di below:

ing: DITH= resolution Le U in, P--- Po normally pu ow to ente . Normally standby m iption R D D D D irection. "H" 8bit re n (last 2 bi eft or Right Up / Down Positive P Negative P Analo Global No co Commo Ditheri Powe No co No co wer/Groun ull high er reset sta y pull high.

mode esolution (its of input t Display C Display Co Power for T Power for og Power reset pin.onnection on Voltage ing setting er Ground onnection onnection

nd, N--- No ate. Sugge Sca Up to D Down t Up to D Down t (default se t data trun ontrol ontrol TFT TFT

. e g o Connecti st to conne anning Dire Down, Left to Up, Righ Down, Righ to Up, Left etting) ncated)

ion ect with an ection

t to Right ht to Left ht to Left t to Right

Note2Note3 Note4 Note5

n RC

3 4 5

4.E LECTRICAL C HARACTERISTICS

4.1A BSOLUTE M AXIMUM R ATINGS

Ta = 25℃±2 Item Symbol Min. Max. Unit Conditions Digital Supply Voltage VDD -0.5 3.96 V

TFT Gate on voltage VGH -0.3 42 V

TFT Gate off voltage VGL VGH-42 0.3 V

Analog power supply

voltage

AVDD -0.5 14.85 V

4.2TFT LCD M ODULE

4.2.1 Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Conditions Digital Supply Voltage VDD 3.0 3.3 3.6 V

TFT Gate on voltage VGH 17 18 19 V

TFT Gate off voltage VGL -7 -6 -5 V

TFT Common electrode

voltage

VCOM 3.1 3.4 3.7 V Analog power supply

voltage

AVDD 9.4 9.6 9.8 V

4.2.2 Current Consumption

Item Symbol Condition

Values

Unit Remark Min. Typ. Max.

Gate on power Current I VGH VGH =18 V - 0.5 1 mA Note2 Gate off power current I VGL VGL=-6V - 0.5 1 mA Note2 Digital power current IVDD VDD = 3.3V - 30 45 mA

Note2 Analog power current IAVDD AVDD =9.6V - 35 45 mA

Note2

4.4DC E LECTRICAL C HARACTERISTICS

4.4.1TTL M ODE DC E LECTRICAL C HARACTERISTICS

VDD=2.3~3.6V,AVDD=8~13.5V,GND=AGND=0V, TA=20℃～+85℃

Parameter Symbol

Spec.

Unit Condition Min. Typ. max

Power supply

voltage

VDD 2.3 - 3.6 V - Power supply

voltage

AVDD 6.5 - 13.5 V -

Power supply voltage AVDDL

6.5 - 13.5 V Full

range

application

4 - 6.7

5 V Half AVDD application

Power supply voltage AGNDH

0 V

Full

range

application

4 - 6.7

5 V Half AVDD application

Low level input voltage VIL 0 - 0.3VDD V For

digital

circuit

High level input voltage VIH 0.7VDD - VDD V For

digital

circuit

Output low voltage VOL - -

GND+

0.4

V IOL

=400μA

Output high voltage VOH

VDD-

0.4

- - V IOH

=-400μA

Pull low/high resistance Ri 200 250 300 kA

For the digital input pin

@VDD=3.3V

Input leakage current Ii - - ±1

uA For

digital

circuit

Digital

Operation current Idd - 12 20 mA

Dual gate mode or Cascade

mode

slave, Fclk=50MHz, LD=48KHz,

VDD=3.3V, No load

Digital stand-by current Ist1 - 10 50 μA

Clock & all functions are

stopped

Analog

Operating current Idda - 8 10 mA

No load, Fclk=50MHz,LD=48KHz

@ AVDD=10V, V1=8V, V14=0.4V

Analog Stand-by current Ist2

10 50 μA

No load, clock & all functions

are

stopped

Input level of V1~V7 Vref1

0.4

AVDD

AVDD-

0.1

Gamma correction voltage

input

Input level of

V8~V14 Vref2 0.1 -

0.6

AVDD V

Gamma correction voltage

input

Output

Voltage deviation Vod1 - ±20 ±35 mV

Vo=AGND+0.1V~AGND+0.5V &

Vo=AVDD-0.5V~AVDD-0.1V

Output

Voltage deviation Vod2 - ±15 ±20 mV Vo

=AGND+0.5V~AVDD-0.5V

Output

Voltage Offset between Chips Voc - - ±20 mV Vo

=AGND+0.5V~AVDD-0.5V

Dynamic

Range of Output Vdr 0.1 - AVDD-

0.1 V SO1~SO1200

Sinking

Current of Outputs IOLy 80 - - μA

SO1~SO1200; Vo=0.1V vs.

1.0V, AVDD=13.5V

Driving

Current of Outputs IOHy 80 - - μA

SO1~SO1200 ;Vo=0.1V vs.

12.5V,AVDD=13.5V

Resistance of Gamma Table Rg 0.7*Rn

1.0*Rn 1.3*Rn ΩRn: Internal gamma resistor

.5P OWER O To prev below mu Power o Power o ote: Low le Low le

ON/OFF vent the de ust be follo on: VDD, G off: V1 to V evel=3FH, evel=00H,

S EQUENCE evice dama owed. GND → AVD V14 → AVD when NBW

when NBW

age from la DD, AGND DD, AGND →W=L (Norma

W=H (Norm atch up, th → V1 to V

VDD, GN

ally white)mally black

he power o V14 ND

)

on/off seq quence sho own

4.6B ACK L IGHT

Item Symbol

Values

Unit Remark Min. Typ. Max.

LED Current ILED 80 mA 12LEDS Forward Voltage VF 9.0 9.9 10.5 V IF=80mA.12LEDS Reverse Current Ir - - 50 uA VR=10V,1LED Power dissipation Pd 840 mW 12LEDS Peak forward current Ifp 100 mA 1LED Reverse voltage VR 10 V 1LED

4.6.1I NTERNAL C IRCUIT D IAGRAM

5. 5V G DC D V V H H Da D D O 5.I NPUT S 5.1AC E L 5.1.1 TT Paramete VDD Power Slew rat RB pulse w CLK cycle CLK pulse VSD setup t VSD hold ti HSD setup t HSD hold t ata set-up Data hold t DE setup ti DE hold ti Output sta time

5.2D ATA I 5.2.1 TTL Vertical T Horizonta IGNAL T I LECTRICAL TL Mode AC er Sym r On

te width time duty time ime time ime time time ime me able

NPUT F OR L M ODE D ATA Timing

al Timing

MING

C HARACTE C Electrica mbol Min T POR - T GRB 50 T cph 14 T cwh 40 T vst 5 T vhd 5 T hst 5 T hhd 5 T dsu 5 T dhd 5 T esu 5 T ehd 5 T sst - RMAT

A I NPUT F OR ERISTICS

al Charact Spec.

. Typ. M - - - 50 - - - - - - - - -

RMAT

teristics

Unit Max.

20 ms - us - ns 60 % - ns - ns - ns - ns - ns - ns - ns ns 6 us

D0[7D0[710% to Co From 0V DCL 7:0], D1[7:07:0], D1[7:0o 90% targ R=10K o Du ondition V to 90% V K=65MHz

0], D2[7:00], D2[7:0

get voltage ohm(Cascad ual gate

DD ] to DCLK ] to DCLK

e.CL=90pF,de)

5.3P ARALLEL RGB INPUT TIMING TABLE 5.3.1DE MODE

Parameter Symbol

Spec.

Unit Min. Typ. Max.

DCLK Frequency fclk 40.8 51.2 67.2 MHz Horizontal Display Area thd 1024 DCLK HSD Period th 1114 1344 1400 DCLK HSD Blanking thb+ thfp 90 320 376 DCLK Vertical Display Area tvd 600 T H VSD Period tv 610 635 800 T H VSD Blanking tvbp+ tvfp 10 35 200 T H

5.3.2HV MODE

Horizontal Timing

Parameter Symbol

Spec.

Unit Min. Typ. Max.

DCLK Frequency fclk 44.9 51.2 63 MHz Horizontal Display Area thd 1024 DCLK HS Period th 1200 1344 1400 DCLK HS Pulse Width thpw 1 - 140 DCLK HS Back Porch thbp 160 DCLK HS Front Porch thfp 16 160 216 DCLK

Vertical Timing

Parameter Symbol

Spec.

Unit Min. Typ. Max.

Vertical Display Area tvd 600 T H VS Period tv 624 635 750 T H VS Pulse Width tvpw 1 - 20 T H S Back Porch tvbp 23 T H VS Front Porch tvfp 1 12 127 T H

.4T IMING D 5.4.1I NPUT 5.4.2V ERT

5.4.3 V ERT

IAGRAM

T C LOCK AN TICAL T IMING TICAL T IMING D D ATA T IM G D IAGRAM H G D IAGRAM D MING D IAGRA HV (D UAL GA DE (D UAL G AM

ATE )

GATE )

6.O PTICAL C HARACTERISTICS

Ta=25℃±2 Item Symbol Condition Min. Typ. Max. Unit Note Contrast Ratio CR Θ = 0°　600 800 - Note1

Note4

Luminance YL 100

120

cd/m2 Note1 Note6 Note7

Luminance Uniformity IV-M70 75 %

Response Time

(Rising + Falling) T RT Ta= 25℃

Θ = 0°　

- 25 40 ms

Note1

Note3

Viewing Angle range

Left Θ

CR > 10

- 45 - degree

Note2 Right Θ -

degree

Up Φ- 25 - degree

Down Φ- 35 - degree

Color Chromaticity (CIE1931) White

0.260 0.310 0.360

Note1

Note5

Note7 y

0.280 0.330 0.380

Red

0.526 0.576 0.626

0.301 0.351 0.401 Green

0.272 0.322 0.372

0.540 0.590 0.640

Blue

0.100 0.150 0.200

0.070 0.120 0.170

NTSC 51 % Note1: Definition of optical measurement system

No No

ote2: Defin Viewi ote3: Defin The “Wh outp phot

nition of vi ng angle is nition of Re response t ite” state put intensi to detecto P h o t o d e t e c t o r o u t p u t

(R e l a t i v e v a l u e

)

iewing ang

esponse ti

time is def and “Blac ty changed r output in 100%90%

10%

W hite

F gle range a 6 o'clock dir me

fined as th ck” state. d from 90%ntensity ch e (TFT OFF)O Fig. 6-3 Defi and measur rection

he LCD opt Rise time % to 10%. hanged fro Black (TF ON

inition of re rement sys ical switch (TON) is th And fall t m 10% to 9FT ON)

esponse tim stem

hing time i he time be ime (TOFF 90%.

W hite (TFT O OFF me

interval be etween ph F) is the ti OFF)

ergo-80). etween hoto detect ime betwe tor een

No No No No

ote4: Defin “White “Blac Vwhit ote5: Defin Colo ote6: All in pane ote7: Defin Activ cent Lumin Bma Bmin

nition of co Contrast r e state “: T k state”: T te: To be d nition of co or coordina nput termi el. The LED nition of Lu ve area is ter of each nance Unifo x: The me n: The mea ontrast rat ratio(CR)= The state i The state i determined olor chrom ates measu inals LCD p D driving c uminance divided in h measurin ormity (U) =L----Activ easured ma asured min tio

is that the is that the d Vblack: T maticity (CI ured at cen panel mus ondition is Uniformity nto 9 mea g area.

Lmin/ Lma ve area len aximum lum nimum lum e LCD shou LCD shoul To be dete IE1931)

nter point st be groun s IL=80mA y

suring are ax

ngth, W---minance o minance of

ld drive by ld drive by ermined. of LCD.

nd while m

eas.Every m - Active ar f all measu all measu

y Vwhite. y Vblack.

measuring t measuring rea width

urement p rement po

the center point is p position.

osition. r area of t placed at t the

the

.Q UALITY

7.1T E

HighTemp

Low Temp

High Tempe

ow Tempe

High Tem

Humidi

Ther

Imag

ote1:Condi

Opera

imme

7.2V IB

Test ite

Packing S

(non-oper

Packing Vib

(non-oper

7.3ESD

Test

Electro

Dischar

(non-op

. LCD glas

2. IF conne

Y A SSURA

EMPERATUR

est Item

peratureSt

perature St

erature Op

mperature

ity Operat

rmal Shock

ge Sticking

ition of im

ation with

ediately.aft

BRATION&

Shock

ration)

bration

ration)

item

o Static

rge Test

peration)

s and meta

ector pins

ANCE S YS

RE AND H U

torage

peration

High

ion

age stickin

test patte

ter 5 mins

S HOCK

980m/s2

Freque

Stroke:1

x,y,z 2

200pF

al bezel

STEM

UMIDITY

Test

Ta=6

Ta=-2

Ta=5

Ta=-

Ta=50℃

72Hrs(no

-20℃(0.5

ng test :25

ern sustaine

,the mura

Condit

2,6ms, ±x,

direct

ency range

.0mm,swe

hours for

Cond

150pF，

Contact:±4

F，0?，±2

t Condition

60℃; 72hr

20℃; 72hr

50℃; 72Hr

10℃; 72hr

，90%RH

o condensa

5h) ~ 60℃(

10cycles

5℃ ; 4hrs

5 ±2

ed for 4hr

must be d

ions

,y,z 3time

tion

e:10 HZ~50

eep:10 HZ ~

each direc

ditions

330?，

4KV,Air:±8K

200V conta

H，

ation)

(0.5h)

IEC

s,then cha

disappeare

es for

0HZ

~50HZ

ction

act test

IEC60

GB/

Start with

End with

C60068-2-1

ange to gra

ed complet

IEC60

Remark

0068-2-1：

B2423.2-20

0068-2-1：

B2423.1-20

0068-2-1：

B2423.2-20

0068-2-1：

B2423.1-20

0068-2-78

/T2423.3-2

h cold temp

high temp

4:1984,GB

Note1

ay pattern

tely

Remark

0068-2-27

B/T2423.5-

0068-2-32

/T2423.8-

Remark

IEC6100

GB/T17

2007

008

2007

008

2007

008

2007

008

：2001

2006

perature

perature，

B2423.22-2

：1987

-1995

：1990

1995

0-4-2：200

7626.2-200

，

2002

8.P RECAUTION R ELATING P RODUCT H ANDLING

8.1S AFETY

(1) Do not swallow any liquid crystal, even if there is no proof that liquid crystal ispoisonous.

(2) If the LCD panel breaks, be careful not to get liquid crystal to touch your skin.

(3) If skin is exposed to liquid crystal, wash the area thoroughly with alcohol or soap.

8.2S TORAGE C ONDITIONS

(1) Store the panel or module in a dark place where the temperature is 23±5°C andthe humidity is below 50±20%RH.

(2) Store in anti-static electricity container.

(3) Store in clean environment, free from dust, active gas, and solvent.

(4)Do not place the module near organics solvents or corrosive gases.

(5) Do not crush, shake, or jolt the module.

8.3H ANDLING P RECAUTIONS

(1) Avoid static electricity which can damage the CMOS LSI.

(2) The polarizing plate of the display is very fragile. So, please handle it verycarefully.

(3) Do not give external shock.

(4) Do not apply excessive force on the surface.

(5) Do not wipe the polarizing plate with a dry cloth, as it may easily scratch theSurface of plate.

(6) Do not use ketonics solvent & Aromatic solvent, use with a soft cloth soaked with

a cleaning naphtha solvent.

(7) Do not operate it above the absolute maximum rating.

(8) Do not remove the panel or frame from the module.

(9)When the module is assembled, it should be attached to the system firmly,Be careful

not to twist and bend the module.

(10)Wipe off water droplets or oil immediately. If you leave the droplets for a longtime, staining and discoloration may occur.

(11) If the liquid crystal material leaks from the panel,it should be kept away from theeyes or mouth.In case of contact with hands,legs or clothes, it must be washedaway thoroughly with soap.

8.4W ARRANTY

(1)The period is within twelve months since the date of shipping out under normal using and storage conditions.

(2) Do not repaired or modified the LCM . It may cause function to lose efficacy ,XianChuang does not warrant the LCM.

(3) All process and material comply ROHS.