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LTC2239IUH中文资料

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Low Noise 3V ADC

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

■Sample Rate: 80Msps

■Single 3V Supply (2.7V to 3.4V)■Low Power: 211mW

■61.6dB SNR at 70MHz Input ■85dB SFDR at 70MHz Input ■No Missing Codes

■Flexible Input: 1V P-P to 2V P-P Range ■575MHz Full Power Bandwidth S/H ■Clock Duty Cycle Stabilizer ■Shutdown and Nap Modes ■

Pin Compatible Family

125Msps: LTC2253 (12-Bit), LTC2251 (10-Bit)105Msps: LTC2252 (12-Bit), LTC2250 (10-Bit)80Msps: LTC2229 (12-Bit), LTC2239 (10-Bit)65Msps: LTC2228 (12-Bit), LTC2238 (10-Bit)40Msps: LTC2227 (12-Bit), LTC2237 (10-Bit)25Msps: LTC2226 (12-Bit), LTC2236 (10-Bit)10Msps: LTC2225 (12-Bit)

■

32-Pin (5mm × 5mm) QFN Package

The LTC ?2239 is a 10-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2239 is perfect for de-manding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals well beyond the Nyquist frequency.DC specs include ±0.1LSB INL (typ), ±0.1LSB DNL (typ)and ±0.5LSB INL, ±0.5LSB DNL over temperature. The transition noise is a low 0.08LSB RMS .

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

D9???D0REFL

SNR vs Input Frequency,

–1dB, 2V Range

APPLICATIO S

■Wireless and Wired Broadband Communication ■Imaging Systems

■Ultrasound

■Spectral Analysis

■

Portable Instrumentation

INPUT FREQUENCY (MHz)

55S N R (d B F S )

565859606562501002239 G09

57636461150

200

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ABSOLUTE AXI U RATI GS

W W W

U PACKAGE/ORDER I FOR ATIO

W OV DD = V DD (Notes 1, 2)

Supply Voltage (V DD ).................................................4V Digital Output Ground Voltage (OGND).......–0.3V to 1V Analog Input Voltage (Note 3).....–0.3V to (V DD + 0.3V)Digital Input Voltage....................–0.3V to (V DD + 0.3V)Digital Output Voltage................–0.3V to (OV DD + 0.3V)Power Dissipation............................................1500mW Operating Temperature Range

LTC2239C ...............................................0°C to 70°C LTC2239I.............................................–40°C to 85°C Storage Temperature Range..................–65°C to 125°C

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T A = 25°C. (Note 4)

PARAMETER

CONDITIONS

MIN TYP MAX UNITS Resolution (No Missing Codes)●

10Bits Integral Linearity Error Differential Analog Input (Note 5)●–0.5±0.10.5LSB Differential Linearity Error Differential Analog Input ●–0.5±0.10.5LSB Offset Error (Note 6)●–12±212mV Gain Error External Reference ●

–2.5

±0.5 2.5

%FS Offset Drift ±10μV/°C Full-Scale Drift Internal Reference ±30ppm/°C External Reference ±5ppm/°C Transition Noise

SENSE = 1V

0.08

LSB RMS

CO VERTER CHARACTERISTICS

T JMAX = 125°C, θJA = 34°C/W EXPOSED PAD IS GND (PIN 33)MUST BE SOLDERED TO PCB

3231302928272625

9101112TOP VIEW

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

13141516

17181920212223248

765432

1A IN +A IN

–

REFH REFH REFL REFL V DD GND D6D5D4OV DD OGND D3D2D1

V D D

V C M

S E N S E

M O D E

O F

D 9

D 8D 7

C L K

S H D N

O E

N C

N C N C

N C

D 0

ORDER PART NUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.

LTC2239CUH LTC2239IUH

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: https://www.wendangku.net/doc/0b5609689.html,/leadfree/

QFN PART MARKING*

2239

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR

Signal-to-Noise Ratio

5MHz Input 61.6dB 40MHz Input ●

61.6dB 70MHz Input 61.6dB 140MHz Input

61.6dB SFDR

Spurious Free Dynamic Range 5MHz Input 85

dB 2nd or 3rd Harmonic

40MHz Input ●6985dB 70MHz Input 85dB 140MHz Input

80dB SFDR

Spurious Free Dynamic Range 5MHz Input 85

dB 4th Harmonic or Higher

40MHz Input ●7585dB 70MHz Input 85dB 140MHz Input

85dB S/(N+D)

Signal-to-Noise Plus Distortion Ratio

5MHz Input 61.6

dB 40MHz Input ●6061.6dB 70MHz Input 61.6dB 140MHz Input

61.5dB I MD

Intermodulation Distortion f IN1 = 28.2MHz, f IN2 = 26.8MHz 85dB Full Power Bandwidth

Figure 8 Test Circuit

575

MHz

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 4)

DY A IC ACCURACY

W PARAMETER CONDITIONS MIN TYP MAX UNITS

V CM Output Voltage I OUT = 0

1.475

1.500 1.525

V V CM Output Tempco ±25ppm/°C V CM Line Regulation 2.7V < V DD < 3.4V 3mV/V V CM Output Resistance

–1mA < I OUT < 1mA 4

I TER AL REFERE CE CHARACTERISTICS

U U U

(Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

V IN Analog Input Range (A IN + – A IN –)

2.7V < V DD <

3.4V (Note 7)●±0.5 to ±1V V IN,CM Analog Input Common Mode (A IN + + A IN –)/2Differential Input (Note 7)●1 1.5 1.9V Single Ended Input (Note 7)●0.5 1.5

2V I IN Analog Input Leakage Current 0V < A IN +, A IN – < V DD ●–11μA I SENSE SENSE Input Leakage 0V < SENSE < 1V

●–33μA I MODE MODE Pin Leakage

●

–3

μA t AP Sample-and-Hold Acquisition Delay Time 0ns t JITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2ps RMS

CMRR

Analog Input Common Mode Rejection Ratio

A ALOG I PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T A = 25°C. (Note 4)

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DIGITAL I PUTS A D DIGITAL OUTPUTS

U The ● denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T A = 25°C. (Note 4)

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.

Note 4: V DD = 3V, f SAMPLE = 80MHz, input range = 2V P-P with differential drive, unless otherwise noted.

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111.Note 7: Guaranteed by design, not subject to test.

Note 8: V DD = 3V, f SAMPLE = 80MHz, input range = 1V P-P with differential drive.

Note 9: Recommended operating conditions.

TI I G CHARACTERISTICS

W The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T A = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f s Sampling Frequency (Note 9)

●180MHz t L

CLK Low Time

Duty Cycle Stabilizer Off ● 5.9 6.25500ns Duty Cycle Stabilizer On ●5 6.25500ns (Note 7)

t H

CLK High Time

Duty Cycle Stabilizer Off ● 5.9 6.25500ns Duty Cycle Stabilizer On ●

6.25500

ns (Note 7)t AP Sample-and-Hold Aperture Delay 0

t D

CLK to DATA Delay C L = 5pF (Note 7)● 1.4 2.7 5.4ns Data Access Time After OE ↓C L = 5pF (Note 7)● 4.310ns BUS Relinquish Time

(Note 7)

●

3.38.5

ns Pipeline 5

Cycles

Latency

Typical DNL, 2V Range

Typical INL, 2V Range

8192 Point FFT, f IN = 5MHz,–1dB, 2V Range

TYPICAL PERFOR A CE CHARACTERISTICS

U W

CODE

–1.0

I N L E R R O R (L S B )

–0.8–0.4–0.201.00.4

256

5122239 G01

–0.60.6

0.80.2768

1024

CODE

–1.0

D N L

E R R O R (L S B )

–0.8–0.4–0.201.00.4

256

5122239 G02

–0.60.60.80.2768

1024

FREQUENCY (MHz)

0A M P L I T U D E (d B )

–60–40–200352239 G03

–80–100–70–50–30–10–90–110–120

5152510

203040

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TYPICAL PERFOR A CE CHARACTERISTICS

U W

8192 Point FFT, f IN = 30MHz,–1dB, 2V Range

8192 Point FFT, f IN = 70MHz,–1dB, 2V Range

8192 Point FFT, f IN = 140MHz,–1dB, 2V Range

Grounded Input Histogram

SNR vs Input Frequency,–1dB, 2V Range

8192 Point 2-Tone FFT,f IN = 28.2MHz and 26.8MHz,–1dB, 2V Range

SFDR vs Input Frequency,–1dB, 2V Range

SNR and SFDR vs Sample Rate,2V Range, f IN = 5MHz, –1dB

SNR and SFDR vs Clock Duty Cycle

FREQUENCY (MHz)

A M P L I T U D E (d

B )

–60–40

–20035

2239 G04

–80–100–70–50–30

–10–90–110–120

152510

2030

FREQUENCY (MHz)

A M P L I T U D E (d

B )

–60–40

–20035

2239 G05–80–100–70–50–30

–10–90–110–120

152510

203040

FREQUENCY (MHz)

A M P L I T U D E (d

B )

–60–40–200352239 G06

–80–100–70–50–30–10–90–110–120

5152510

203040

FREQUENCY (MHz)

0A M P L I T U D E (d B )

–60–40–200352239 G07

–80–100–70–50–30

–10–90–110–120

5152510

203040CODE

100000120000140000

2239 G08

8000060000510

511131072

512

004000020000

C O U N T

INPUT FREQUENCY (MHz)

S N R (d B F S )

56585960656250

1002239 G09

57636461150

200

INPUT FREQUENCY (MHz)

0859*******

2239 G10

807550

100

200

7065

S F D R (d B F S )

SAMPLE RATE (Msps)

0S N R

A N D S F D R (d

B F S )

90100

802239 G11

1020304050607090100110

CLOCK DUTY CYCLE (%)

S N R A N

D S F D R (d B F S )

7580

8560

2239 G12

706540

6055

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TYPICAL PERFOR A CE CHARACTERISTICS

U W

SNR vs Input Level, f IN = 70MHz,2V Range

I OVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, O VDD = 1.8V

I VDD vs Sample Rate, 5MHz Sine Wave Input, –1dB

SFDR vs Input Level, f IN = 70MHz,2V Range

INPUT LEVEL (dBFS)

–50

S N R (d B c A N D d B F S )

304050–20

2239 G13

20100–40

–30

dBFS dBc

–10607080INPUT LEVEL (dBFS)

–50

0S F D R (d B c A N D d B F S )

10304050–30

–10

902239 G14

20–40

–206070

dBFS

dBc

80SAMPLE RATE (Msps)

050

I V D D (m A )

556570

851050702239 G15

60804090100

20306080SAMPLE RATE (Msps)

I O V D D (m A )

134571********* G16

264090

100

20306080

PI FU CTIO S

A IN+ (Pin 1): Positive Differential Analog Input.

A IN- (Pin 2): Negative Differential Analog Input.

REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

V DD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.

GND (Pin 8): ADC Power Ground.

CLK (Pin 9): Clock Input. The input sample starts on the positive edge.

SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-ing SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to V DD results in normal operation with the outputs at high impedance. Connecting SHDN to V DD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to V DD and OE to V DD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output E nable Pin. Refer to SHDN pin function.NC (Pins 12 to 15): Do Not Connect These Pins.

D0 – D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D9 is the MSB.

OGND (Pin 20): Output Driver Ground.

OV DD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.

OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred.

MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V DD selects 2’s complement output format and turns the clock duty cycle stabilizer on. V DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to V CM selects the internal reference and a ±0.5V input range. V DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±V SENSE. ±1V is the largest valid input range.

V CM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

82239fa

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FU CTIO AL BLOCK DIAGRA

U U

Figure 1. Functional Block Diagram

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TI I G DIAGRA

U W W

ANALOG INPUT

CLK

D0-D9, OF

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DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC.Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

THD = 20Log (√(V22

+ V32

+ V42

+ . . . Vn 2

)/V1)where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

APPLICATIO S I FOR ATIO

W U

U If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer func-tion can create distortion products at the sum and differ-ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,etc. The 3rd order intermodulation products are 2fa + fb,2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.Input Bandwidth

The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.Aperture Delay Time

The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit.Aperture Delay Jitter

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNR JITTER = –20log (2π ? f IN ? t JITTER )

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CONVERTER OPERATION

As shown in Figure 1, the LTC2239 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section).For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended.The LTC2239 has two phases of operation, determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC,a reconstruction DAC and an interstage residue amplifier.In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high,the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation.

Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2239CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C SAMPLE ) through NMOS transistors. The capacitors shown attached to each input (C PARASITIC ) are the summation of all other capaci-tance associated with each input.

During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage.When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Figure 2. Equivalent Input Circuit

A IN A IN 2239 F02

APPLICATIO S I FOR ATIO

W U

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APPLICATIO S I FOR ATIO

W U

U Single-Ended Input

For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the har-monic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, A IN +should be driven with the input signal and A IN – should be connected to 1.5V or V CM .Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The V CM output pin (Pin 31) may be used to provide the common mode bias level.V CM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The V CM pin must be bypassed to ground close to the ADC with a 2.2μF or greater capacitor.Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic performance of the LTC2239 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F ENCODE ); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100? or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2239 being driven by an RF transformer with a center tapped secondary. The second-ary center tap is DC biased with V CM , setting the ADC input signal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100? for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain band-width of most op amps will limit the SFDR at high input frequencies.

ARE 0402 PACKAGE SIZE

2239 F03

Figure 4. Differential Drive with an Amplifier

2239 F04

Figure 3. Single-Ended to Differential Conversion Using a Transformer

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APPLICATIO S I FOR ATIO

W U

U Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.Reference Operation

Figure 9 shows the LTC2239 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage refer-ence can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to V DD selects the 2V range; tying the SENSE pin to V CM selects the 1V range.

Figure 5 shows a single-ended input circuit. The imped-ance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required.The 25? resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.

For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun trans-former gives better high frequency response than a flux coupled center tapped transformer. The coupling capaci-2239 F09

Figure 9. Equivalent Reference Circuit

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APPLICATIO S I FOR ATIO

W U

U Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise perfor-mance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 0.7dB.Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11).

The noise performance of the LTC2239 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical, such as when digitiz-ing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.

The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally,the reference is used with a difference amplifier to gener-ate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, V CM . This provides a high frequency low impedance path to ground for internal and external circuitry.

The difference amplifier generates the high and low refer-ence for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE.It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1μF ceramic capacitor.

Figure 10. 1.5V Range ADC

CLEAN 2239 F11

Figure 11. Sinusoidal Single-Ended CLK Drive

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Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PE CL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solu-tion. The nature of the received signals also has a large bearing on how much SNR degradation will be experi-enced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact.

The transformer shown in the example may be terminated with the appropriate termination for the signaling in use.The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differ-ential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depend-ing on transmission line length may require a 10? to 20?ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mecha-nism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2239 is 80Msps.For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V DD or 2/3V DD using external resistors.The lower limit of the LTC2239 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating fre-quency for the LTC2239 is 1Msps.

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CLEAN IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

Figure 13. LVDS or PECL CLK Drive Using a Transformer

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U DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2239 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373CMOS latch. For full speed operation the capacitive load should be kept under 10pF.

Lower OV DD voltages will also help reduce interference from the digital outputs.Data Format

Using the MODE pin, the LTC2239 parallel digital output

can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3V DD selects offset binary output format. Connecting MOD E

to 2/3V DD or V DD selects 2’s complement output format.An external resistor divider can be used to set the 1/3V DD or 2/3V DD logic values. Table 2 shows the logic states for the MODE pin.

Figure 14. Digital Output Buffer

Table 2. MODE Pin Function

Clock Duty MODE Pin Output Format Cycle Stablizer

0Offset Binary Off 1/3V DD Offset Binary On 2/3V DD 2’s Complement On V DD

2’s Complement

Off

Table 1. Output Codes vs Input Voltage

A IN + – A IN –D9 – D0D9 – D0(2V Range)OF (Offset Binary)(2’s Complement)>+1.000000V 111 1111 111101 1111 1111+0.998047V 011 1111 111101 1111 1111+0.996094V 011 1111 111001 1111 1110+0.001953V 010 0000 000100 0000 0001 0.000000V 010 0000 000000 0000 0000–0.001953V 001 1111 111111 1111 1111–0.003906V 001 1111 111011 1111 1110–0.998047V 000 0000 000110 0000 0001–1.000000V 000 0000 000010 0000 0000<–1.000000V

00 0000 0000

10 0000 0000

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output buffer. Each buffer is powered by OV DD and OGND, iso-lated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50? to external circuitry and may eliminate the need for external damping resistors.

Overflow Bit

When OF outputs a logic high the converter is either overranged or underranged.

2239 F12

μF

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U Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OV DD , should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OV DD should be tied to that same 1.8V supply.OV DD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OV DD . The logic outputs will swing between OGND and OV DD .Output Enable

The outputs may be disabled with the output enable pin, OE .OE high disables all data outputs including OF. The data ac-cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op-eration. The output Hi-Z state is intended for use during long periods of inactivity.Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to V DD and OE to V DD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to V DD and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Grounding and Bypassing

The LTC2239 requires a printed circuit board with a clean,unbroken ground plane. A multilayer board with an inter-nal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the V DD , OV DD , V CM , REFH, and REFL pins. Bypass capaci-tors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402ceramic capacitor is recommended. The large 2.2μF ca-pacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capaci-tors must be kept short and should be made as wide as possible.

The LTC2239 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.Heat Transfer

Most of the heat generated by the LTC2239 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

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U Clock Sources for Undersampling

Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required,a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times,as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers

must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the source to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device.If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply.For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi-layer PCBs.

The differential pairs must be close together, and dis-tanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

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