cy6264-RAM-datasheet
PRELIMINARY
8K x 8 Static RAM
CY6264
Features
?55, 70 ns access times
?CMOS for optimum speed/power
?Easy memory expansion with CE 1, CE 2, and OE fea-tures
?TTL-compatible inputs and outputs
?Automatic power-down when deselected
Functional Description
The CY6264 is a high-performance CMOS static RAM orga-nized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE 1), an active HIGH chip enable (CE 2), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic pow-er-down feature (CE 1), reducing the power consumption by
over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the writ-ing/reading operation of the memory. When CE 1 and WE in-puts are both LOW and CE 2 is HIGH, data on the eight data input/output pins (I/O 0 through I/O 7) is written into the memory location addressed by the address present on the address pins (A 0 through A 12). Reading the device is accomplished by selecting the device and enabling the outputs, CE 1 and OE active LOW, CE 2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad-dressed by the information on address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram Pin Configuration
CY6264-1
A 1A
2
A 3A
4
A 5A 6A
7
A 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage T emperature .................................–65°C to +150°C Ambient Temperature with
Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential...............–0.5V to +7.0V DC Voltage Applied to Outputs
in High Z State [1]............................................–0.5V to +7.0V DC Input Voltage [1].........................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage.......................................... >2001V (per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature V CC Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
6264-55
6264-70Unit Min.Max.
Min.Max.
V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.4
2.4
V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA
0.40.4V V IH Input HIGH Voltage 2.2V CC 2.2V CC V V IL Input LOW Voltage [1]–0.50.8–0.50.8V I IX Input Load Current GND < V I < V CC –5+5–5+5μA I OZ Output Leakage Current
GND < V I < V CC ,Output Disabled –5+5–5
+5μA I OS Output Short Circuit Current [2]V CC = Max.,V OUT = GND –300–300mA I CC V CC Operating Supply Current V CC = Max.,I OUT = 0 mA
100100mA I SB1Automatic CE 1
Power–Down Current Max. V CC , CE 1 > V IH,Min. Duty Cycle=100%2020mA I SB2
Automatic CE 1
Power–Down Current
Max. V CC , CE 1 > V CC – 0.3V,V IN > V CC – 0.3V or V IN < 0.3V
15
15mA
Shaded area contains advanced information.
Capacitance [3]
Parameter
Description
Test Conditions
Max.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz,V CC = 5.0V
7pF C OUT
Output Capacitance
7
pF
Notes:
1.Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
2.Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3.T ested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481?
3.0V
5V OUTPUT
R1 481?
R2255?
30pF
GND
90%
90%10%
<5ns
<5ns
5V OUTPUT
CY6264-3
R2255?
5pF
CY6264-4
(a)(b)
OUTPUT
1.73V
INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE
10%
Equivalent to:
THéVENIN EQUIVALENT ALL INPUT PULSES
167?
Switching Characteristics Over the Operating Range[4]
Parameter Description
6264-556264-70
Unit Min.Max.Min.Max.
READ CYCLE
t RC Read Cycle Time5570ns t AA Address to Data Valid5570ns t OHA Data Hold from Address Change55ns t ACE1CE1 LOW to Data Valid5570ns t ACE2CE2 HIGH to Data Valid4070ns t DOE OE LOW to Data Valid2535ns t LZOE OE LOW to Low Z35ns t HZOE OE HIGH to High Z[5]2030ns t LZCE1CE1 LOW to Low Z[6]55ns t LZCE2CE2 HIGH to Low Z35ns t HZCE CE1 HIGH to High Z[5, 6]
CE2 LOW to High Z
2030ns t PU CE1 LOW to Power-Up00ns t PD CE1 HIGH to Power-Down2530ns WRITE CYCLE[7]
t WC Write Cycle Time5070ns t SCE1CE1 LOW to Write End4060ns t SCE2CE2 HIGH to Write End3050ns t AW Address Set-Up to Write End4055ns t HA Address Hold from Write End00ns t SA Address Set-Up to Write Start00ns t PWE WE Pulse Width2540ns t SD Data Set-Up to Write End2535ns t HD Data Hold from Write End00ns t HZWE WE LOW to High Z[5]2030ns t LZWE WE HIGH to Low Z55ns Shaded area contains advanced information.
Notes:
4.T est conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I OL/I OH and 30-pF load capacitance.
5.t HZOE, t HZCE, and t HZWE are specified with C L = 5 pF as in part (b) of AC T est Loads. Transition is measured ±500 mV from steady-state voltage.
6.At any given temperature and voltage condition, t HZCE is less than t LZCE for any given device.
7.The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Switching Waveforms
Notes:
8.Device is continuously selected. OE, CE = V IL . CE 2 = V IH.9.Address valid prior to or coincident with CE transition LOW.10.WE is HIGH for read cycle.
11.Data I/O is High Z if OE = V IH , CE 1 = V IH , or WE = V IL .
Read Cycle No.1ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t RC
t AA
t OHA
CY6264-5
[8, 9]
Read Cycle No.250%
50%
DATA VALID
t RC
t ACE
t DOE
t LZOE
t LZCE
t PU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t HZOE
t HZCE
t PD
OE
HIGH DATA OUT
V CC SUPPLY CURRENT
CE 1
OE CE 2CY6264-6
[10, 11]
Write Cycle No.1(WE Controlled)DATA UNDEFINED
HIGH IMPEDANCE
t HD
t HZWE
t SD
t LZWE
t PWE
t SA
t HA
t AW
t SCE2
t SCE1
t WC
DATA IN
DATA I/O
ADDRESS
CE 1OE
WE
CE 2
CY6264-7
DATA IN VALID [9, 11]
Note:
12.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
Write
Cycle
No.2
(CE
Controlled)
t WC
DATA
UNDEFINED
HIGH IMPEDANCE
t AW t SA
t PWE
t HA
t HD
t HZWE
t SD
CY6264-8
CE 2
WE
DATA IN
DATA I/O
ADDRESS
t SCE2t SCE1
CE 1
DATA IN VALID [9, 11, 12]
Typical DC and AC Characteristics
?5525125
1.21.00.8
VOLTAGE
120140100
6040200.0
1.0
2.0
3.0
4.0
Typical DC and AC Characteristics (continued)
3.02.52.01.51.00.50.0
1.0
2.0
3.0
4.0
TIME
0.0 5.0
0.0
1000
0.50
V CC =4.5V T A =25°C
V CC =5.0V T A =25°C V CC =0.5V
Truth Table
CE 1CE 2WE OE Input/Output Mode
H X X X High Z Deselect/Power-Down
X L X X High Z Deselect L H H L Data Out Read L H L X Data In Write L
H
H
H
High Z
Deselect
Address Designators
Address Name Address Function
Pin Number
A4X32A5X43A6X54A7X65A8X76A9Y17A10Y48A11Y39A12Y010A0Y221A1X023A2X124A3
X2
25
Ordering Information
Speed
(ns)Ordering Code Package
Name Package Type
Operating
Range
55CY6264-55SC S2328-Lead 330-Mil SOIC[13]Commercial 70CY6264-70SC S2328-Lead 330-Mil SOIC[13]Commercial 55CY6264-55SNC S2228-Lead 300-Mil SOIC Commercial 70CY6264-70SNC S2228-Lead 300-Mil SOIC Commercial Shaded area contains advanced information.
Note:
13.Not recommended for new designs.
Document #: 38-00425-A
Package Diagrams
Package Diagrams (continued)
? Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress