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UCLAMP0501T中文资料

UCLAMP0501T中文资料

PROTECTION PRODUCTS PROTECTION PRODUCTS - MicroClamp TM Low Profile μClamp TM 1-Line ESD protection

Description

Features

Dimensions

Schematic & PIN Configuration

The μClamp TM series of TVS arrays are designed to pro-tect sensitive electronics from damage or latch-up due to ESD. It is designed to replace multilayer varistors (MLVs) in portable applications such as cell phones, note-book computers, and other portable electronics. It fea-tures large cross-sectional area junctions for conducting high transient currents. They offer desirable character-istics for board level protection including fast response time, low operating and clamping voltage, and no device degradation.

The μClamp TM 0501T is in a 2-pin, RoHS/WEEE compli-ant, SLP1006P2T package. It measures 1.0 x 0.6 mm with a nominal height of only 0.4mm. The leads are spaced at a pitch of 0.65mm and are finished with lead-free NiPdAu. Each device will protect one line operating at 5 volts. It gives the designer the flexibility to protect single lines in applications where arrays are not practical. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4

(±15kV air, ±8kV contact discharge). The combination of small size and high ESD surge capability makes them ideal for use in portable applications such as cellular phones, digital cameras, and MP3 players.

Applications

Mechanical Characteristics

Cellular Handsets & Accessories Personal Digital Assistants (PDAs) Notebooks & Handhelds Portable Instrumentation Digital Cameras Peripherals

MP3 Players

Transient protection for data lines to

IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)Cable Discharge Event (CDE)

Ultra-small package (1.0 x 0.6 x 0.4mm) Protects one data line Low clamping voltage Working voltage: 5V Low leakage current

Solid-state silicon-avalanche technology

SLP1006P2T package RoHS/WEEE Compliant

Nominal Dimensions: 1.0 x 0.6 x 0.4 mm Lead Finish: NiPdAu

Molding compound flammability rating: UL 94V-0 Marking : Marking code, cathode band Packaging : Tape and Reel

UCLAMP0501T中文资料

Absolute Maximum Rating

g

n i t a R l o b m y S e u l a V s t i n U )

s μ02/8=p t (r e w o P e s l u P k a e P P k p 52s t t a W (t n e r r u C e s l u P k a e P m u m i x a M )s μ02/8=p t I p p 2s p m A )

r i A (2-4-00016C E I r e p D S E )t c a t n o C (2-4-00016C E I r e p D S E V D S E 02-/+51-/+V k e r u t a r e p m e T g n i t a r e p O T J 521+o t 55-C °e

r u t a r e p m e T e g a r o t S T G

T S 0

51+o t 55-C

°

UCLAMP0501T中文资料

Typical Characteristics

Non-Repetitive Peak Pulse Power vs. Pulse Time

UCLAMP0501T中文资料

UCLAMP0501T中文资料

1020304050607080901001100255075100

125150

Ambient Temperature - T A (o

C)

% o f R a t e d P o w e r o r I P P

Power Derating Curve

Clamping Voltage vs. Peak Pulse Current

Forward Voltage vs. Forward Current

UCLAMP0501T中文资料

UCLAMP0501T中文资料

Junction Capacitance vs. Reverse Voltage

ESD Clamping

(8kV Contact per IEC 61000-4-2)

5

10

15

0.5

1

1.5

2

2.5

3

Peak Pulse Current - I PP (A)

C l a m p i n g V o l t a g e - V C (V )

1234567

80

1

234567891011121314

Forward Current - I F (A)

F o r w a r d V o l t a g e - V F V )

UCLAMP0501T中文资料

00.10.20.30.40.50.60.70.80.911.10

1

23

4

5

Reverse Voltage - V R (V)

C J (V R ) / C J (V R =0)

0.01

0.1

1

10

0.1

1

10

100

Pulse Duration - tp (us)

P e a k P u l s e P o w e r - P P P (k W )

Note: Data is taken with a 10x attenuator

Insertion Loss S21

START

. 030 MHz 3 STOP 000 .000 000 MHz

CH1 S21 LOG

6 dB / REF 0 dB

1: -3.0037dB 572.149 MHz

2: -5.0581 dB 800.00 MHz

3: -5.8299 dB 900.00 MHz

4: -23.207

1.80000 GHz

5: -13.452

2.50000 GHz

0 dB -6 dB -12 dB -18 dB -24 dB -30 dB -36 dB

1

GHz 100 MHz 3 GHz 10 MHz 1 MHz

1

2

3

4

5

Typical Characteristics

Applications Information

Device Connection Options

Circuit Diagram This device is designed to protect one data or power

supply line. The device is unidirectional and may be

UCLAMP0501T中文资料

The cathode band should be placed towards the line

that is to be protected.

Circuit Board Layout Recommendations for Suppres-

sion of ESD.

Good circuit board layout is critical for the suppression

of ESD induced transients. The following guidelines are

recommended:

z Place the TVS near the input terminals or connec-

tors to restrict transient coupling.

z Minimize the path length between the TVS and the

protected line.

z Minimize all conductive loops including power and

ground loops.

z The ESD transient return path to ground should be

kept as short as possible.

z Never run critical signals near board edges.

z Use ground planes whenever possible.

Applications Information - Spice Model

uClamp0501T Spice Model

5

p

a l C

u

m

s r e t e

T1

a r a

m

e c i p S

P

1

V T(

D

U)S

m

P t i n

r e t e

a r a

1-e5

0.2

A5

S I p

m

B t l o V0.7

V

8.0

J V t l o V0

7.0

O5

S

h

R m

m

A3-E0.1

B I p

V

1-e9

O J C d a r a F2

5.2

T T c e s9-E14

2.0

M--5

N--1.1

1.1

G

E V e1

Outline Drawing - SLP1006P2T

UCLAMP0501T中文资料

Contact Information

Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012Phone: (805)498-2111 FAX (805)498-3804

Marking Code

Ordering Information

r

e b m u N t r a P g n i k r o W e g a t l o V r e p y t Q l e e R l e e R e z i S T

C T .T 1050p m a l C u V

50

00,3h

c n I 7Notes:

1) This is a lead-free, RoHS/WEEE compliant product MicroClamp, uClamp and μClamp are marks of Semtech Corporation

Tape and Reel Specification

e p a T h

t d i W )x a M (,B D 1D E F P 0P 2P T W m

m 8m m 2.4)

561.(m m 1.0+5.1m m 0.0-500.+95.0()

000.-m

UCLAMP0501T中文资料

m 4.052.0±)

UCLAMP0501T中文资料

130.(01.±057.1m m )

400.±960.(50.0±5.3m m )200.±831.(01.0±0.4m m -00.±751.()

41.0±0.4m m -00.±751.()

450.0±0.2m m )

200.±970.(20.0±452.0)

610.(m m m m 0.8m m 3.0+m m 1.0-)

210.±213.(0

A 0

B 0

K m

m 01.0-/+96.0m

m 01.0-/+91.1m

m 01.0-/+66.0Device Orientation in Tape