PPC440SPE-RGB533C中文资料

Part Number 440SPe

Revision 1.23 - Sept 21, 2006 PowerPC 440SPe Embedded Processor

Preliminary Data Sheet Features

?PowerPC? 440 processor core operating up to 667 MHz with 32KB I- and D-caches (with parity checking)

?On-chip 256KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory ?Selectable Processor vs Bus clock ratios (Refer to the Clocking chapter in the PPC440SPe

Embedded Processor User’s Manual for details)?Support up to 16 GB (4 Chip Selects) of 64-bit/32-bit SDRAM with ECC

DDR I 266-333-400

DDR II 400-533-667

?Three PCI-Express serial interfaces:

one 8 lanes and two 4 lanes - 2.5Gb/s per lane Root and Endpoint support.

Opaque bridge

?One 64-bit DDR PCI-X interfaces up to 133 MHz (DDR 266) with support for conventional PCI ?Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives ?Optional:16 Programmable Galois Field polynomials including 14d and 11d

?XOR Accelerator with DMA controller

?I2O messaging with two DMA controllers

?External Peripheral Bus (16-bit Data, 27-bit Address) for up to three devices; Bank0=16 MB, Bank1 and Bank2=128 MB each

?One Ethernet 10/100/1000Mbps half- or full-duplex interface. Operational modes supported are MII and GMII.

?Programmable Interrupt Controller supports interrupts from a variety of sources.?Programmable General Purpose Timers (GPT)?Three serial ports (16750 compatible UART)?Two IIC interfaces

?General Purpose I/O (GPIO) interface available

?JTAG interface for board level testing

?Processor can boot from PCI memory

Description

Designed specifically to address high-end embedded applications for storage, the PowerPC 440SPe (PPC440SPe) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, a DDR1/DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three PCI-Express interfaces, one DDR PCI-X bus interface, a 1Gbps Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.Technology: CMOS Cu-11, 0.13mm Package: 27mm, 675-ball, 1mm pitch, Flip Chip-Plastic Ball Grid Array (FC-PBGA)

Power (estimated): Less than 14W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet Contents

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

27mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet Figures

Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 27mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7. DDR SDRAM Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 9. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 11. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Tables

Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 15. I/O Specifications—667MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 18. DDR SDRAM Clock to Write DQS Timing—T DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 20. DDR SDRAM I/O Read Timing—T SD and T HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

Ordering and PVR Information

For information about the availability of the following parts, contact your local sales office. The most current version of the 440SPe is Revision B. The part numbers for 440SPe Revision B are shown in the following figures.

Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC440SPe Embedded Processor User’s Manual for details about accessing these registers.

Note: Raid-enabled versions (Product Feature = R) require a RAID key license.Figure 1. Order Part Number Key

The part numbers for 440SPe Revision A are shown in the following figure.

Product Name Order Part Number (see Notes 1-5)Package Rev Level PVR Value JTAG ID PPC440SPe PPC440SPe-xpBfffC

27mm, 675 FC-PBGA

B

0x53421891

0x14538049

Notes:

1.x = Product Feature

A = RAID6 not enabled (Rev Level

B only)R = RAID6 enabled (Rev Level B only)2.p = Module Package Type

G = leaded FC-PBGA

N = lead free FC-PGBA (RoHS compliant)3. B = Chip Revision Level B (2.0)4.fff = Processor Frequency

533 = 533MHz 667 = 667MHz

5. C = Case Temperature Range of 0°C to +95°C

Product Name Order Part Number Processor Frequency Package Rev Level PVR Value JTAG ID PPC440SPe PPC440SPe-3GA533C 533MHz 27mm, 675 FC-PBGA A 0x534218900x14538049PPC440SPe

PPC440SPe-3GA667C

667MHz

27mm, 675 FC-PBGA

A

0x53421890

0x14538049

PPC440SPe-RNB667C

Package

Product Feature

Case Temperature Range Revision Level

Processor Speed AMCC Part Number

Note: The example part number above is a RAID6-enabled, lead-free package, at Chip Revision Level B, at PCI Express core revision level 1.1, capable of running at 667 MHz, and is shipped in tray packaging.

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

PPC440SPe Functional Block Diagram

Figure 2. PPC440SPe Functional Block Diagram

The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus ? Architecture.Implemented with the Crossbar option, the CoreConnect buses provide:

?Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data path (10.6 GB/s total)

?32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s

Processor Core DCR Bus

32KB On-chip Peripheral Bus (OPB)

GPIO

IIC UART Bridge

External Clock,Control,Reset

Power Mgmt

JTAG Timers MMU

OPB Interrupt Controller

Universal I-Cache

32KB D-Cache

XOR/DMA PPC440

PCI-Express x2

x3

MAL

Ethernet DCRs GP Timers

256 KB

Low Latency (LL) Segment

High Bandwidth (HB) Segment

Processor Local Bus (PLB)

Trace Arb

PLB I2O/DMA Memory PCI-E0PCI-E1PCI-E2

MII,GMII

Queue DDR PCI-X

4 lanes 8 lanes 4 lanes

IRQ Handler

PCI-E Bus Controller

(EBC)

10/100/1000

Controller (DMA0 and DMA1)

Accelerator

Unit (DMA2)

Registers

64-bit

64+8

16

16 IRQs

DDR 1 and 2 SDRAM Cntl

L2 Cache/SRAM

MAC

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet Address Maps

The PPC440SPe incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various processor accessible address regions. The second address map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the PPC440SPe processor through the use of mtdcr and mfdcr instructions.

Table 1. System Memory Address Map (Sheet 1 of 2)

Function Sub Function Start Address End Address Size

Local Memory (LL)1DDR SDRAM0000 0000 0000 00000000 0003 FFFF FFFF16GB SRAM0000 0004 0000 00000000 0004 0003 FFFF256KB Reserved0000 0004 0004 00000000 0004 000F FFFF

Internal PLB Interfaces (LL)I2O Registers0000 0004 0010 00000000 0004 0010 00FF256B DMA 0 Registers0000 0004 0010 01000000 0004 0010 01FF256B DMA 1 Registers0000 0004 0010 02000000 0004 0010 02FF256B I20/DMA Buffers0000 0004 0010 03000000 0004 0010 0FFF

3.25K

B Reserved0000 0004 0010 10000000 0004 001F FFFF

XOR/DMA20000 0004 0020 00000000 0004 0020 03FF1KB Reserved0000 0004 0020 04000000 0004 002F FFFF

PCI Express Interrupt Handler0000 0004 0030 00000000 0004 0030 00FF256B Reserved0000 0004 0030 01000000 0004 DFFF FFFF

Internal OPB Peripherals (LL)EBC Memory60000 0004 E000 00000000 0004 EFFF FFFF256MB Reserved0000 0004 F000 00000000 0004 F000 01FF

UART00000 0004 F000 02000000 0004 F000 02078B

Reserved0000 0004 F000 02080000 0004 F000 02FF

UART10000 0004 F000 03000000 0004 F000 03078B

Reserved0000 0004 F000 03080000 0004 F000 03FF

IIC00000 0004 F000 04000000 0004 F000 041F32B

Reserved0000 0004 F000 04200000 0004 F000 04FF

IIC10000 0004 F000 05000000 0004 F000 051F32B

Reserved0000 0004 F000 05200000 0004 F000 05FF

UART20000 0004 F000 06000000 0004 F000 06078B

Reserved0000 0004 F000 06080000 0004 F000 06FF248B

GPIO Controller Registers0000 0004 F000 07000000 0004 F000 077F128B

Reserved0000 0004 F000 07800000 0004 F000 07FF

Ethernet Controller Registers0000 0004 F000 08000000 0004 F000 08FF256B

Reserved0000 0004 F000 09000000 0004 F000 09FF

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

General Purpose Timers 0000 0004 F000 0A000000 0004 F000 0B3F 320B

Reserved

0000 0004 F000 0B400000 0004 FEFF FFFF Boot ROM 2, 3EBC Bank0

0000 0004 FF00 00000000 0004 FFFF FFFF 16MB Reserved

0000 0005 0000 00000000 0007 FFFF FFFF Local Memory Alias (HB)

Aliased DDR SDRAM 0000 0008 0000 00000000 000B FFFF FFFF 16GB PCI Space (HB)

Reserved 0000 000C 0000 00000000 000C 07FF FFFF PCIX0 I/O 0000 000C 0800 00000000 000C 0800 FFFF 64KB Reserved

0000 000C 0801 00000000 000C 0EBF FFFF PCIX0 Addressing configuration Regs 0000 000C 0EC0 00000000 000C 0EC0 00078B Reserved

0000 000C 0EC0 00080000 000C 0EC7 FFFF PCIX0 Core Configuration Regs

0000 000C 0EC8 00000000 000C 0EC8 0FFF 4KB Reserved

0000 000C 0EC8 10000000 000C 0EC8 10FF PCIX0 Simple Message Passing 0000 000C 0EC8 11000000 000C 0EC8 11FF 256B Reserved

0000 000C 0EC8 12000000 000C 0ECF FFFF PCIX0 Special Cycle 0000 000C 0ED0 00000000 000C 0EDF FFFF 1MB Reserved

0000 000C 0EE0 00000000 000C 0FFF FFFF PCI Memory (PCI-Express & PCI-X)0000 000C 1000 00000000 000C FEFF FFFF 3.8GB PCI-X DDR boot ROM (PCI memory 0000 000C FF00 00000000 000C FFFF FFFF 16MB PCI Memory (PCI-Express & PCI-X)0000 000D 0000 00000000 000F FFFF FFFF 12GB Reserved 40000 0010 0000 00000FFF FFFF FFFF FFFF Reserved 5

1000 0000 0000 00001FFF FFFF FFFF FFFF PCI Core Space (HB)PCI Memory (PCI-Express & PCI-X)2000 0000 0000 0000

FFFF FFFF FFFF FFFF

Notes:

1.DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

2.The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

3.When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at C FF00 0000 (16 MB).

4.Never decoded.

5.Unpredictable results on Read and Write operations.

6.Accessed by means of EBC Peripheral Bank Configuration Registers.

Table 1. System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

Start Address End Address Size

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

Table 2. DCR Address Map (4KB of Device Configuration Registers)

Function Start Address End Address Size Total DCR Address Space10003FF1KW (4KB)1

By function:

Reserved00000B12W

Clocking Power On Reset00C00D2W

System DCRs 00E00F2W

Memory Controller 0100112W

External Bus Controller0120132W

Reserved01401F12W

SRAM02002F16W

L2 Controller03003F16W

Memory Queue04005F32W

I2O, DMA0 & DMA106007F32W

PLB08008F16W

PLB to OPB Bridge Out09009F16W

Reserved0A00AF16W

Reserved0B20BF14W

Interrupt Controller 00C00CF16W

Interrupt Controller 10D00DF16W

Interrupt Controller 20E00EF16W

Interrupt Controller 30F00FF16W

PCI-Express 010011F32W

PCI-Express 112013F32W

PCI-Express 214015F32W

Power Management1601678W

Reserved16817F24W

Ethernet MAL1801FF128W

Reserved2003FF512W

Notes:

1.DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-

gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet PowerPC 440 Processor Core

The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include:

?Up to 800 MHz operation

?PowerPC Book E architecture

?32KB I-cache, 32KB D-cache

–parity on data and tag address - Checking of parity with error injection

?Three logical regions in D-cache: Locked, Transient, and Normal

?D-cache full-line flush capability

?41-bit virtual address, 36-bit (64GB) physical address

?Superscalar, out-of-order execution

?Seven-stage pipeline

?Three execution pipelines

?Dynamic branch prediction

?Memory management unit

–64-entry, full associative, unified TLB with parity

–Separate instruction and data micro-TLBs

–Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

?Debug facilities

–Multiple instruction and data range breakpoints

–Data value compare

–Single step, branch, and trap events

–Non-invasive real-time trace interface

?24 DSP instructions

–Single cycle multiply and multiply-accumulate

–32 x 32 integer multiply

Internal Buses

The PowerPC 440SPe features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, the PCI Express and the DDR PCI-X bridges connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores.

The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB segment allows PLB masters DMA, XOR, PCI and PCI Express to exchange large blocks of data with SDRAM, PCI and PCI Express without interfering with the low latency PLB masters.

Bus features include:

?PLB

–128-bit implementation of the PLB architecture

–Separate and simultaneous read and write data paths

–64-bit address

–Simultaneous control, address, and data phases

–Four levels of pipelining

–Byte enable capability supporting unaligned transfers

–32- and 64-byte burst transfers

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

–166MHz, maximum 5.2GB/s (simultaneous read and write)

–Processor vs Bus clock ratios of N:1 and N:2

?OPB

–Dynamic bus sizing: 32, 16, and 8-bit data path

–32-bit address

–83.33MHz, maximum 333MB/s

?DCR

–Register control bus

–32-bit data path

–10-bit address

On-Chip SRAM/L2 Cache

Features include:

?Four banks of 64KB each for a total of 256KB

?Configurable as either L2 cache or SRAM

?Memory cycles supported:

–Single beat read and write, 1 to 16 bytes

–Quadword Read and Write burst for 12-bit master

–Guarded memory accesses on 4KB boundaries

?Sustainable 2.6GB/s peak bandwidth at 166MHz

?Use as an L2 cache improves processor performance and reduces the PLB load

–Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by software

–Data Array and Tag Array parity

–Unified data and instruction cache

–Four-way set associative

–36-bit addressing

–Full LRU replacement algorithm

–Write through, look aside

?Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core

PCI Express

Features include:

?Three independent PCI Express interfaces

–One 8 lanes

–Two4lanes

– 2.5 GB/sec full duplex per lane

?Compliant with PCI Express base specification 1.0a

?Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)

–Applications compliant with MSI rules are limited to one End Point port per PPC440SPe

?PCI-Express to PCI-Express opaque (Non-Transparent) bridge

?Power Management

?Supports one virtual channel (VC0) no Traffic Class (TC) filtering

?Maximum Payload block size 512 Bytes

?Supports up to 1024 byte maximum Read request size

?Requests supported:

–up to 4 posted outbound Write requests (memory and messages)

–up to 4 posted inbound Write requests

–up to 4 outbound Read requests outstanding on PCI Express

–up to 4 inbound Read requests outstanding on PCI Express

–Outbound I/O request as a PCI Express Root Port

–Inbound I/O request as a PCI Express End Point

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

?Buffering in each PCI Express Port for the following transaction types:

–4K byte Replay buffer: up to 8 in flight transactions

–2K bytes for Outbound posted Writes

–8K bytes for Outbound Reads completion

?2K prefetch request from first I2O/DMA PLB Master

?1K prefetch request from 2nd I2O/DMA PLB Master

?1K prefetch request from first PCIE 4x links

?1K prefetch request from 2nd PCIE 4x links

?256 byte from the PPC440

–2K bytes for Inbound posted Writes

–2K bytes for Inbound Reads completion

?Parity checking on each buffer

?POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs ?PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM

?INTx Interrupts support (PCI legacy):

–up to 4 INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC

–A/B/C/D INTx types Generation for Endpoints

?MSI - Message Signaled Interrupts

–MSI Generation for End Point

–MSI Termination for Root Ports

–MSI_X Termination for Root Ports

DDR PCI-X Interface

The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. The PCI-X interface supports 64-bit PCI-X bus in DDR mode 2. It can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.

Features include:

?PCI-X2.0

–Split transactions

–Frequency to 266MHz

–32- and 64-bit address/data bus

–ECC supported for 266MHz Mode 2 only

?PCI 2.3 backward compatibility

–Frequency to 66MHz

–32- and 64-bit bus

?Can be the PCI Host Bus Bridge or an Adapter Device PCI interface

?Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter

?Support for PLB-based (external to PLB–PCI-X bridge) I2O

?Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts

?Simple message passing capability

?Asynchronous to the PLB

?PCI Power Management Version 1.1

?PCI arbitration function with PCI-X Mode 2 support (optional)

?PCI register set addressable both from on-chip processor and PCI device sides

?Ability to boot from PCI-X bus memory

?Error tracking/status

?Supports initiation of transfer to the following address spaces:

–Single beat I/O reads and writes

–Single beat and burst memory reads and writes

–Single beat configuration reads and writes (Type 0 and Type 1)

–Single beat special cycles

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

?PCI-X initialization sequence support (frequency & mode determination)

?Support for unexpected split completions

?Outbound transaction split discard timers

?Vital Product Data (VPD) support

?PCI-X to PCI-Express opaque bridge

DDR1/DDR2 SDRAM Memory Controller

The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-speed 1KB FIFO buffers.

Features include:

?Registered and non-registered industry standard DIMMs

?DDR2 400/667 support

?64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)

? 5.32GB/s peak bandwidth for the 64-bit interface

? 2.66GB/s peak bandwidth for the 32-bit interface

?Four chip (bank) select signals supporting 4 external banks

?CAS latencies of 2, 3, 4, 5, 6, and 7 supported

?Page mode accesses (up to 32 open pages) with configurable paging policy

?Look-ahead request queue with programmable depth of four commands.

?Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current bank)

?Up to 16GB in four external banks

?Up to 6 MemClkout signals for high loading unbuffered DIMMS.

?Programmable address mapping and timing

?Hardware and software initiated self-refresh

?Sync DRAM configuration by means of mode register and extended mode register set commands

?Power management (self-refresh, suspend, sleep)

?Low Latency & High Bandwidth PLB ports

?Selectable PLB read response (immediate or deferred)

?Programmable Low Latency & High Bandwidth arbitration schemes

?High Bandwidth port has four 1KB read buffers and two 1KB write buffers

?Low Latency port has four 128B read buffers and two 128B write buffers

External Peripheral Bus Controller (EBC)

Features include:

?Support Boot ROM on Bank 0; programmable size 2, 4, 8,16 MB

?Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported

?Burst and non-burst devices

?16 or 8-bit data bus

?27-bit address, 128MB address space for Banks 1 & 2

?Peripheral Device pacing with external “Ready”

?Latch data on Ready, synchronous or asynchronous

?Programmable access timing per device

–256 Wait States for non-burst

–32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

–Programmable CSon, CSoff relative to address

–Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

?Programmable address mapping

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet Ethernet Controller Interface

The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip.

Features include:

?One 10/100/1000 interface running in full- and half-duplex modes

–One full Media Independent Interface (MII) with 4-bit parallel data transfer

–One Gigabit Media Independent Interface (GMII)

I2O/DMA Controller

The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and writes and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden. I2O features include:

?I2O pull- and push-messaging methods

?Dynamic message frame size

?Programmable FIFO size (4096 64-bit MFAs maximum)

?64-bit and 32-bit MFA sizes

?Three interrupt gathering methods

?Registered MFA prefetch and posting

?32-bit inbound and outbound doorbell registers

?Four 32-bit scratch pad registers

DMA features include:

?Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)?512-byte buffering

?Simultaneous fill and drain (PLB read/write pipelining)

?Any source PLB address to any destination address

?No memory alignment restrictions on source or destination

?32-byte command descriptor block

?Maximum transfer size of 16MB

?64-bit addressing

?1KB buffering (DMA1 only)

?Prefetch indicators for PCI-X buffer management (DMA1 only)

Optional RAID 5 and RAID 6 Acceleration Hardware

The 440SPe provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6 algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail.

The 440SPe offers a choice of two XOR engines for computing the P parity. The first choice is available with the XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with the RAID 6 Galois Field GF(28)-based polynomial computations, resides inside the Memory Queue functional block of the Memory Controller unit. The Galois Field polynomial used with the 440SPe is programmable and can be one of sixteen available irreducible polynomials, including 14d and 11d.

The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware also provides various alternatives for balancing load and performance, depending on customer-specific application firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously, resulting in extremely high throughput.

RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SPe-RpBfffC) as indicated in the ordering information section of this data sheet.

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

For more information about the RAID 6 implementation, description, and configuration of the acceleration hardware, refer to the following AMCC documents:

?PowerPC 440SP/440SPe RAID Support Application Note

?PowerPC 440SPe RAID Addendum to the User’s Manual

XOR/DMA2 Controller

The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity generation and check functions used across data stripes in a RAID 5 system.

?Computes a bit-wise XOR on up to 16 data streams with result stored in designated target

?Performs XOR check on up to 16 data streams

?Driven by a linked list Command Block structure specifying control information, source operands, target operand, status information, and link

?Source and target streams may reside anywhere in PLB address space.

?Provides completion status per Command Block to be handled by software at a later time

?96-byte and 160-byte Command Block formats are supported

?No memory alignment restrictions on operands or target

?Internal register arrays and data buffers are parity protected

?Can be used as a DMA controller (DMA2) with single source and target addresses

?PLB Master interface

?PLB Slave port used as control interface for reading and writing control and status information

Serial Port

The serial port is compatible with the NS? 16570 UART interface.

Features include:

?One 8-pin, one 4-pin, and one 2-pin interfaces are provided

?Selectable internal or external serial clock to allow wide range of baud rates

?Register compatibility with 16750 register set

?Complete status reporting capability

?Fully programmable serial-interface characteristics

IIC Bus Interface

Features include:

?Two IIC interfaces provided

?Support for Philips? Semiconductors I2C Specification, dated 1995

?Operation at 100kHz or 400kHz

?8-bit data

?10- or 7-bit address

?Slave transmitter and receiver

?Master transmitter and receiver

?Multiple bus masters

?Supports fixed V DD IIC interface

?Two independent 4 x 1 byte data buffers

?Twelve memory-mapped, fully programmable configuration registers

?One programmable interrupt request signal

?Full management of all IIC bus protocols

?Programmable error recovery

?Port 0 supports serial Bootstrap ROM with default override parameters at initialization

PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet General Purpose Timers (GPT)

Provides a time base counter and system timers additional to those defined in the processor core.

?32-bit time base counter driven by the OPB bus clock

?Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

?Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB bus master accesses.

?The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose.

?Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain). Universal Interrupt Controller (UIC)

Four cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts. Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

?16 external interrupts

?101 internal interrupts

?Edge-triggered or level-sensitive

?Positive- or negative-active

?Non-critical or critical interrupt to the on-chip processor core

?Programmable interrupt priority ordering

?Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

?IEEE 1149.1 Test Access Port

?IBM RISCWatch Debugger support

?JTAG Boundary Scan Description Language (BSDL)

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

Figure 3. 27mm, 675-Ball FC-PBGA Core Package

Top View

Bottom View

Note: All dimensions are in mm.

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PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

Signal Lists

This section contains two tables that list external signals.

Table 3 lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal(s) in brackets.

In Table 3, multiplexed pins that have no internal signal connected after reset are marked High Z.

Multiplexed signals appear alphabetically multiple times in the list—once for each signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 50 where the signals in the indicated interface group begin.

Table 4 on page 42 lists all the external signals in order by ball (pin) number.Signal List—Alphabetic Order

Table 3. Signals Listed Alphabetically (Sheet 1 of 25)

Signal Name

Ball Interface Group

Page

BA0AE22DDR SDRAM

52

BA1AD21BA2AE21BankSel0AD20BankSel1Y18BankSel2Y19

BankSel3W17CAS AB22ClkEn0Y21ClkEn1AA22ClkEn2AE25ClkEn3AF25DM0AD25DDR SDRAM

52DM1V20DM2V25DM3T25DM4J26DM5G22DM6F24DM7C23DM8

M19

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

DQS0AA23DDR SDRAM

52

DQS0AA24DQS1U21DQS1T19DQS2W23DQS2W24DQS3P24DQS3P25DQS4M22DQS4L22DQS5G25DQS5H25DQS6E22

DQS6F22DQS7B25DQS7C25DQS8P21DQS8R21ECC0R19ECC1R20ECC2M20ECC3P18ECC4P19ECC5N19ECC6N21ECC7

N18

Table 3. Signals Listed Alphabetically (Sheet 2 of 25)

Signal Name

Ball Interface Group

Page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

EMCCD H05Ethernet

53

EMCCrS D03EMCGTxClk J08EMCMDClk F03EMCMDIO B02EMCRefClk H07EMCRxClk B01EMCRxD0L06EMCRxD1J02EMCRxD2G03EMCRxD3H02EMCRxD4H03EMCRxD5L04EMCRxD6M07

EMCRxD7F05EMCRxDV J06EMCRxErr F04EMCTxClk C02EMCTxD0C03EMCTxD1G06EMCTxD2J07EMCTxD3A05EMCTxD4E03EMCTxD5C05EMCTxD6E01EMCTxD7B10EMCTxEn C01EMCTxErr D02ExtReset B11System 55GND A04Power

56GND A10GND A17GND A23GND

D01

Table 3. Signals Listed Alphabetically (Sheet 3 of 25)

Signal Name

Ball Interface Group

Page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

GND D07GND D13GND D14GND D20GND D26GND G04GND G10GND G17GND G23GND J09GND J12GND J15GND J18GND K01GND K07GND K10GND K12GND K15GND K17GND K20GND K26GND L11GND L13GND L14GND

L16

Table 3. Signals Listed Alphabetically (Sheet 4 of 25)

Signal Name

Ball Interface Group

Page