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HY57V561620CLTP-7中文资料

4 Banks x 4M x 16Bit Synchronous DRAM

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for

DESCRIPTION

The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

?Single 3.3±0.3V power supply

?All device pins are compatible with LVTTL interface ?

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package)

All inputs and outputs referenced to positive edge of system clock

?Data mask function by UDQM, LDQM ?

Internal four banks operation

?Auto refresh and self refresh ?8192 refresh cycles / 64ms

Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

?Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Note :

1. HY57V561620CT Series : Nomal power & Leaded 54Pin TSOP II

2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II

3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II

4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II

Part No.

Clock Frequency

Power Organization Interface 400mil 54pin TSOP II

HY57V561620C(L)T(P)-6166MHz (Normal)

Low Power

4Banks x 4Mbits x16LVTTL

(Leaded)

Lead Free

HY57V561620C(L)T(P)-7143MHz HY57V561620C(L)T(P)-K 133MHz HY57V561620C(L)T(P)-H 133MHz HY57V561620C(L)T(P)-8125MHz HY57V561620C(L)T(P)-P 100MHz HY57V561620C(L)T(P)-S 100MHz

PIN CONFIGURATION

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQM

BA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity

A0 ~ A12Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10

RAS, CAS, WE Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15Data Input/Output Multiplexed data input / output pin

V DD/V SS Power Supply/Ground Power supply for internal circuits and input buffers

V DDQ/V SSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 16 I/O Synchronous DRAM

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=0 to 70°C )

Note :

1.All voltages are referenced to V SS = 0V

2.V IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration

3.V IL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION (TA=0 to 70°C , V DD =3.3 ± 0.3V, V SS =0V)

Note :

1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature T A 0 ~ 70°C Storage Temperature

T STG -55 ~ 125°C Voltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power Dissipation

P D 1W Soldering Temperature ? Time

T SOLDER

260 ? 10

°C ? Sec

Parameter

Symbol Min Typ.Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6V 1Input High Voltage V IH 2.0 3.0VDDQ + 0.3

V 1,2Input Low Voltage

V IL

- 0.3

0.8

1,3

Parameter

Symbol Value Unit Note

AC Input High / Low Level Voltage

V IH / V IL 2.4/0.4V Input Timing Measurement Reference Level Voltage Vtrip 1.4V Input Rise / Fall Time

tR / tF 1ns Output Timing Measurement Reference Level

Voutref 1.4V Output Load Capacitance for Access Time Measurement

CAPACITANCE (TA=25°C , f=1MHz)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I (TA=0 to 70°C , V DD =3.3±0.3V)

Note :

1.V IN = 0 to 3.6V, All other pins are not tested under V IN =0V

2.D OUT is disabled, V OUT =0 to

3.6V

Parameter

Symbol

-6/7/K/H

-8/P/S

Unit

Min

Max Min Max Input capacitance

CLK

C I1 2.5 3.5 2.5 4.0pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM

CI 2 2.5 3.8 2.5 5.0pF Data input / output capacitance

DQ0 ~ DQ15

C I/O

4.0

6.5

4.0

6.5

Parameter

Symbol

Min.Max Unit Note Input Leakage Current I LI -11uA 1Output Leakage Current I LO -11uA 2

Output High Voltage V OH 2.4-V I OH = -4mA Output Low Voltage

V OL

-0.4

I OL = +4mA

DC CHARACTERISTICS II (TA=0 to 70°C , V DD =3.3±0.3V, V SS =0V)

Note :

1.I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V561620CT(P)-6/7/K/H/8/P/S

4.HY57V561620CLT(P)-6/7/K/H/8/P/S

Parameter

Symbol

Test Condition

Speed

Unit

Note

-6

-7-K -H -8-P -S Operating Current

I DD1Burst length=1, One bank active t RC ≥ t RC (min), I OL =0mA 130

110

110100

100

Precharge Standby Current in Power Down Mode

I DD2P CKE ≤ V IL (max), t CK = 15ns 2

I DD2PS

CKE ≤ V IL (max), t CK = ∞

Precharge Standby Current in Non Power Down Mode

I DD2N

CKE ≥ V IH (min), CS ≥ V IH (min), t CK = 15ns Input signals are changed one time during 30ns. All other pins ≥ V DD -0.2V or ≤ 0.2V 20

I DD2NS

CKE ≥ V IH (min), t CK = ∞Input signals are stable.10Active Standby Current in Power Down Mode

I DD3P CKE ≤ V IL (max), t CK = 15ns 3

I DD3PS

CKE ≤ V IL (max), t CK = ∞

Active Standby Current in Non Power Down Mode

I DD3N

CKE ≥ V IH (min), CS ≥ V IH (min), t CK = 15ns Input signals are changed one time during 30ns. All other pins ≥ V DD -0.2V or ≤ 0.2V 30

I DD3NS

CKE ≥ V IH (min), t CK = ∞Input signals are stable.25

Burst Mode Operating Current

I DD4t CK ≥ t CK (min), I OL =0mA All banks active

150130130130130110110mA 1Auto Refresh Current I DD5t RRC ≥ t RRC (min), All banks active 220

220

220200

200

mA 2Self Refresh Current

I DD6

CKE ≤ 0.2V

1.5

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate

Parameter

Symbol

-6

-7

-K

-H

-8

-P

-S

Unit Note

Min

Max

Min Max

System Clock

Cycle Time

CAS Latency = 3tCK36

1000

7.5

1000

7.5

1000

CAS Latency = 2tCK27.5107.510101012ns Clock High Pulse Width tCHW 2.5- 2.5- 2.5- 2.5-3-3-3-ns 1Clock Low Pulse Width

tCLW 2.5- 2.5- 2.5- 2.5-3-3-3-ns 1

Access Time From Clock

CAS Latency = 3

tAC3- 5.4- 5.4- 5.4- 5.4-6-6-6ns

CAS Latency = 2

tAC2-6-6- 5.4-6-6-6-6ns Data-Out Hold Time tOH 2.7- 2.7- 2.7- 2.7-3-3-3-ns Data-Input Setup Time tDS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Data-Input Hold Time tDH 0.8-0.8-0.8-0.8-1-1-1-ns 1Address Setup Time tAS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Address Hold Time tAH 0.8-0.8-0.8-0.8-1-1-1-ns 1CKE Setup Time tCKS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1CKE Hold Time tCKH 0.8-0.8-0.8-0.8-1-1-1-ns 1Command Setup Time tCS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Command Hold Time

tCH 0.8-0.8-0.8-0.8-1-1-1-ns 1CLK to Data Output in Low-Z Time tOLZ

1-1-1-1-1-1-1-ns CLK to Data Output in High-Z Time

CAS

Latency =

3tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 2.7 5.4363636ns CAS Latency =

2tOHZ2

2.7

5.4

2.7

5.4

2.7

5.4

AC CHARACTERISTICS II

Note :

1. A new command can be given tRRC after self refresh exit

Parameter

Symbol

-6

-7

-K

-H

-8

-P

-S

Unit

Note

Min

Max Min Max Min Max Min Max Min Max Min Max Min Max RAS Cycle Time

Operation

tRC

-60

-65

-68

-70

-ns

Auto Refresh

tRRC 60-60-60-65-68-70-70-ns RAS to CAS Delay tRCD 18-18-15-20-20-20-20-ns RAS Active Time tRAS 42100K 42100K 45100K 45100K 48100K 50100K 50100K ns RAS Precharge Time tRP 18-18-15-20-20-20-20-ns RAS to RAS Bank Active Delay tRRD 12-14-15-15-16-20-20-ns CAS to CAS Delay tCCD 1-1-1-1-1-1-1-CLK Write Command to Data-In Delay tWTL 0-0-0-0-0-0-0-CLK Write Recovery Time

tWR 2-2-2-2-2-2-2-CLK Data-In to Active

Command tDAL 5-5-5-5-5-5-5-CLK DQM to Data-Out Hi-Z tDQZ 2-2-2-2-2-2-2-CLK DQM to Data-In Mask tDQM 0-0-0-0-0-0-0-CLK MRS to New

Command

tMRD 2-2-2-2-2-2-2-CLK Precharge to Data Output Hi-Z

CAS Latency = 3tPROZ33-3-3-3-3-3-3-CLK CAS Latency = 2

tPROZ22-2-2-2-2-2-2-CLK Power Down Exit Time tPDE 1-1-1-1-1-1-1-CLK Self Refresh Exit Time tSRE 1-1-1-1-1-1-1-CLK 1

Refresh Time

tREF

-64

IBIS SPECIFICATION

I OH Characteristics (Pull-up)

I OL Characteristics (Pull-down)

Voltage 100MHz (Min)100MHz (Max)66MHz (Min)(V)I(mA)

I(mA)I(mA)

3.45-2.43.3-27.33.00-7

4.1-0.72.6-21.1-129.2-7.52.4-34.1-153.3-13.32.0-58.7-197-27.51.8-67.3-226.2-3

5.51.65-73-248-41.11.5-77.9-269.7-47.91.4-80.8-284.3-52.41.0-88.6-344.5-72.50

-93-502.4

-93Voltage 100MHz (Min)100MHz (Max)66MHz (Min)(V)I(mA)I(mA)I(mA)00000.427.570.217.7

0.6541.8107.526.9

0.8551.6133.833.31.058.0151.237.61.470.7187.746.61.572.9194.448.01.6575.4202.549.51.877.0208.650.71.9577.6212.051.53.080.3219.6

54.23.45

81.4

222.6

54.9

DEVICE OPERATING OPTION TABLE

HY57V561620C(L)T(P)-6

HY57V561620C(L)T(P)-7

HY57V561620C(L)T(P)-K

HY57V561620C(L)T(P)-H

HY57V561620C(L)T-8

HY57V561620C(L)T(P)-P

HY57V561620C(L)T(P)-S

CAS Latency

tRCD tRAS tRC tRP tAC tOH 166MHz(6ns)3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns 143MHz(7ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 133MHz(7.5ns)

2CLKs

3CLKs

6CLKs

9CLKs

3CLKs

5.4ns

2.7ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 143MHz(7ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 133MHz(7.5ns)2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns)

3CLKs

6CLKs

9CLKs

3CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns)2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz(10ns)3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

COMMAND TRUTH TABLE

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don ′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation

Command

CKEn-1CKEn CS RAS CAS WE DQM ADDR

A10/AP BA Note

Mode Register Set H X L L L L X

OP code

No Operation H X

H H H Bank Active H

Read

V Read with Autoprecharge H Write

Write with Autoprecharge H Precharge All Banks

Precharge selected Bank L V

Burst Stop H X

H H

X X DQM H X V X Auto Refresh

H H L L L H X X

Burst-Read-Single-WRITE

H X L L L H X A9 Pin High

(Other Pins OP code)

Self Refresh 1

Entry

H L L L L H X

Exit

L H H H Precharge power down

Entry

L H H H

Exit

L H H H Clock Suspend

Entry H L

Exit

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package