ADUC836中文资料
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ADuC836
MicroConverter?, Dual 16-Bit - ADCs with Embedded 62 kB Flash MCU
FEATURES
High Resolution - ADCs
2 Independent ADCs (16-Bit Resolution)
16-Bit No Missing Codes, Primary ADC
16-Bit rms (16-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/ C, Gain Drift 0.5 ppm/ C
Memory
62 Kbytes On-Chip Flash/EE Program Memory
4 Kbytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Y ear Retention, 100 Kcycles Endurance 3 Levels of Flash/EE Program Memory Security
In-Circuit Serial Download (No External Hardware) High Speed User Download (5 Seconds)
2304 Bytes On-Chip Data RAM
8051 Based Core
8051 Compatible Instruction Set
32 kHz External Crystal
On-Chip Programmable PLL (12.58 MHz Max)
3 16-Bit Timer/Counter
26 Programmable I/O Lines
11 Interrupt Sources, 2 Priority Levels
Dual Data Pointer, Extended 11-Bit Stack Pointer
On-Chip Peripherals
Internal Power on Reset Circuit
12-Bit Voltage Output DAC
Dual 16-Bit - DACs/PWMs
On-Chip T emperature Sensor
Dual Excitation Current Sources
Time Interval Counter (Wake-Up/RTC Timer) UART, SPI?, and I2C? Serial I/O
High Speed Baud Rate Generator (Including 115,200) Watchdog Timer (WDT)
Power Supply Monitor (PSM)
Power
Normal: 2.3 mA Max @ 3.6 V (Core CLK = 1.57 MHz) Power-Down: 20 A Max with Wake-Up Timer Running Specified for 3 V and 5 V Operation
Package and T emperature Range
52-Lead MQFP (14 mm 14 mm), –40 C to +125 C
56-Lead LFCSP (8 mm 8 mm), –40 C to +85 C APPLICATIONS
Intelligent Sensors
Weigh Scales
Portable Instrumentation, Battery-Powered Systems
4–20 mA T ransmitters
Data Logging
Precision System Monitoring
FUNCTIONAL BLOCK DIAGRAM
REFIN+
DV
GENERAL DESCRIPTION
The ADuC836 is a complete smart transducer front end, integrating two high resolution - ADCs, an 8-bit MCU, and program/data Flash/EE memory on a single chip.
The two independent ADCs (primary and auxiliary) include a temperature sensor and a PGA (allowing direct measurement
of low level signals). The ADCs with on-chip digital filtering and programmable output data rates are intended for the measure-ment of wide dynamic range, low frequency signals, such as those in weigh scale, strain gage, pressure transducer, or temperature measurement applications.
The device operates from a 32 kHz crystal with an on-chip PLL generating a high frequency clock of 12.58 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle.
62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are provided on-chip. The program memory can be configured as data memory to give up to 60 Kbytes of NV data memory in data logging applications.
On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC836 is supported by a QuickStart? development system featuring low cost software and hardware development tools.
REV. A
ADuC836
–2–TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . .1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .9ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .9DETAILED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . .10PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .10MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . .13SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . .14Accumulator SFR (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . .14B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Stack Pointer (SP and SPH) . . . . . . . . . . . . . . . . . . . . . . . .15 Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . .15Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . .15 ADuC836 Configuration SFR (CFG836) . . . . . . . . . . . . . .15Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16ADC SFR INTERFACE
ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19ADC0H/ADC0M/ADC1H/ADC1L . . . . . . . . . . . . . . . . . .20OF0H/OF0M/OF1H/OF1L . . . . . . . . . . . . . . . . . . . . . . . .20 GN0H/GN0M/GN1H/GN1L . . . . . . . . . . . . . . . . . . . . . . .20SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21PRIMARY AND AUXILIARY ADC NOISE
PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . . .25Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . .25Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .25Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . .29Flash/EE Memory and the ADuC836 . . . . . . . . . . . . . . . . .29 ADuC836 Flash/EE Memory Reliability . . . . . . . . . . . . . . .29 Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . .30Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 User Download Mode (ULOAD) . . . . . . . . . . . . . . . . . . . .31Flash/EE Program Memory Security . . . . . . . . . . . . . . . . . .31 Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . . .31 Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . .32 ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Programming the Flash/EE Data Memory . . . . . . . . . . . . .33 Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . .33OTHER ON-CHIP PERIPHERALS
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Time Interval Counter (Wake-Up/RTC Timer) . . . . . . . . .40 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . .44I 2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488052 COMPATIBLE ON-CHIP PERIPHERALS
Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .57UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Baud Rate Generation Using Timer 1 and Timer 2 . . . . . . .59 Baud Rate Generation Using Timer 3 . . . . . . . . . . . . . . . . .60Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61HARDWARE DESIGN CONSIDERATIONS
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . .63Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Power-On Reset (POR) Operation . . . . . . . . . . . . . . . . . . .64Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Wake-Up from Power-Down Latency . . . . . . . . . . . . . . . . .65 Grounding and Board Layout Recommendations . . . . . . . .66 ADuC836 System Self-Identification . . . . . . . . . . . . . . . . . .66 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66OTHER HARDWARE CONSIDERATIONS
In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . .67 Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . .67 Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . .67 Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . .68QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . .69TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .70OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .80
REV. A
ADuC836
–3–
(AV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 =
32.768 kHz Crystal; all specifications T MIN to T MAX , unless otherwise noted.)
Parameter ADuC836
T est Conditions/Comments Unit ADC SPECIFICATIONS
Conversion Rate 5.4 On Both Channels Hz min 105 Programmable in 0.732 ms Increments Hz max Primary ADC
No Missing Codes 2 16 20 Hz Update Rate Bits min Resolution 13.5 Range = ±20 mV, 20 Hz Update Rate Bits p-p typ 16
Range = ±2.56 V, 20 Hz Update Rate Bits p-p typ Output Noise See T ables X and XI in
Output Noise Varies with Selected ADuC836 ADC Description Update Rate and Gain Range
Integral Nonlinearity ±15 1 LSB ppm of FSR max Offset Error 3 ±3 V typ Offset Error Drift ±10 nV/°C typ Full-Scale Error 4 ±10 Range = ±20 mV to ±640 mV V typ ±0.5 Range = ±1.28 V to ±2.56 V LSB typ Gain Error Drift 5 ±0.5 ppm/°C typ ADC Range Matching ±2 AIN = 18 mV V typ Power Supply Rejection (PSR) 95 AIN = 7.8 mV, Range = ±20 mV dBs typ 80 AIN = 1 V, Range = ±2.56 V dBs typ Common-Mode DC Rejection
On AIN 95 At DC, AIN = 7.8 mV, Range = ±20 mV dBs typ 113 At DC, AIN = 1 V, Range = ±2.56 V dBs typ On REFIN 125 At DC, AIN = 1 V, Range = ±2.56 V dBs typ Common-Mode 50 Hz/60 Hz Rejection 20 Hz Update Rate
On AIN 95 50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV, dBs typ Range = ±20 mV
90 50 Hz/60 Hz ±1 Hz, AIN = 1 V, dBs typ Range = ±2.56 V
On REFIN 90 50 Hz/60 Hz ±1 Hz, AIN = 1 V, dBs typ Range = ±2.56 V
Normal Mode 50 Hz/60 Hz Rejection
On AIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs typ On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs typ Auxiliary ADC
No Missing Codes 2 16 Bits min Resolution 16
Range = ±2.5 V, 20 Hz Update Rate Bits p-p typ Output Noise See T able XII in ADuC836 Output Noise Varies with Selected ADC Description Update Rate
Integral Nonlinearity ±15 ppm of FSR max Offset Error 3 –2 LSB typ Offset Error Drift 1 V/°C typ Full-Scale Error 6 –2.5 LSB typ Gain Error Drift 5 ±0.5 ppm/°C typ Power Supply Rejection (PSR) 80 AIN = 1 V, 20 Hz Update Rate dBs typ Normal Mode 50 Hz/60 Hz Rejection
On AIN 60 50 Hz/60 Hz ±1 Hz dBs typ On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs typ
DAC PERFORMANCE DC Specifications 7
Resolution 12 Bits Relative Accuracy ±3 LSB typ Differential Nonlinearity –1 Guaranteed 12-Bit Monotonic LSB max Offset Error ±50 mV max Gain Error 8 ±1 AV DD Range % max ±1 V REF Range % typ AC Specifications 2, 7
Voltage Output Settling Time 15 Settling Time to 1 LSB of Final Value s typ Digital-to-Analog Glitch Energy 10
1 LSB Change at Major Carry nVs typ
SPECIFICATIONS 1
REV. A
ADuC836
SPECIFICATIONS (continued)
Parameter ADuC836 T est Conditions/Comments Unit INTERNAL REFERENCE
ADC Reference
Reference Voltage 1.25 ± 1% Initial T olerance @ 25°C, V DD = 5 V V min/max Power Supply Rejection 45 dBs typ
Reference T empco100 ppm/°C typ DAC Reference
Reference Voltage 2.5 ± 1% Initial T olerance @ 25°C, V DD = 5 V V min/max Power Supply Rejection 50 dBs typ
Reference T empco±100 ppm/°C typ ANALOG INPUTS/REFERENCE INPUTS
Primary ADC
Differential Input Voltage Ranges9, 10External Reference Voltage = 2.5 V
RN2, RN1, RN0 of ADC0CON Set to Bipolar Mode (ADC0CON3 = 0) ±20 0 0 0 (Unipolar Mode 0 mV to 20 mV) mV
±40 0 0 1 (Unipolar Mode 0 mV to 40 mV) mV
±80 0 1 0 (Unipolar Mode 0 mV to 80 mV) mV
±160 0 1 1 (Unipolar Mode 0 mV to 160 mV) mV
±320 1 0 0 (Unipolar Mode 0 mV to 320 mV) mV
±640 1 0 1 (Unipolar Mode 0 mV to 640 mV) mV
±1.28 1 1 0 (Unipolar Mode 0 V to 1.28 V) V
±2.56 1 1 1 (Unipolar Mode 0 V to 2.56 V) V
Analog Input Current2±1 T MAX = 85°C nA max
±5 T MAX = 125°C nA max
Analog Input Current Drift±5 T MAX = 85°C pA/°C typ
±15 T MAX = 125°C pA/°C typ
Absolute AIN Voltage Limits2AGND + 100 mV V min AV DD – 100 mV V max Auxiliary ADC
Input Voltage Range9, 100 to V REF Unipolar Mode, for Bipolar Mode V
See Note 11
Average Analog Input Current 125 Input Current Will Vary with Input nA/V typ
Average Analog Input Current Drift2±2 Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ
Absolute AIN Voltage Limits2, 11AGND – 30 mV V min AV DD + 30 mV V max External Reference Inputs
REFIN(+) to REFIN(–) Range2 1 V min
AV DD V max
Average Reference Input Current 1 Both ADCs Enabled A/V typ
Average Reference Input Current Drift±0.1 nA/V/°C typ
“NO Ext. REF” Trigger Voltage 0.3 NOXREF Bit Active if V REF < 0.3 V V min
0.65 NOXREF Bit Inactive if V REF > 0.65 V V max
ADC SYSTEM CALIBRATION
Full-Scale Calibration Limit 1.05 FS V max
Zero-Scale Calibration Limit–1.05 FS V min
Input Span0.8 FS V min
2.1 FS V max ANALOG (DAC) OUTPUT
Voltage Range 0 to V REF DACRN = 0 in DACCON SFR V typ
0 to AV DD DACRN = 1 in DACCON SFR V typ Resistive Load 10 From DAC Output to AGND k typ Capacitive Load100 From DAC Output to AGND pF typ
Output Impedance 0.5 typ
I SINK50 A typ TEMPERATURE SENSOR
Accuracy±2 °C typ
Thermal Impedance ( JA) 90 MQFP Package°C/W typ
52 CSP Package (Base Floating)12 °C/W typ
–4–
REV. A
ADuC836
REV. A
–5–
ADuC836
SPECIFICATIONS
(continued)
REV. A
ADuC836
REV. A
–7–
ADuC836
–8–NOTES
1 T emperature range for ADuC836BS (MQFP package) is –40°C to +125°C. T emperature range for ADuC836BCP (CSP package) is –40°C to +85°C.
2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
3 System Zero-Scale Calibration can remove this error.
4 The primary ADC is factory calibrated at 25°C with AV DD = DV DD =
5 V yielding this full-scale error of 10 V . If user power supply or temperature conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10 V . A system zero-scale and full-scale calibration will remove this error altogether. 5 Gain Error Drift is a span drift. T o calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6 The auxiliary ADC is factory calibrated at 25°C with AV DD = DV DD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether.
7 DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to V REF ; reduced code range of 100 to 3950, 0 to V DD . 8 Gain Error is a measurement of the span error of the DAC.
9 In general terms, the bipolar input voltage range to the primary ADC is given by Range ADC = ±(V REF 2RN )/125, where: V REF = REFIN(+) to REFIN(–) voltage and V REF = 1.25 V when internal ADC V REF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., V REF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range ADC = ±1.28 V . In Unipolar mode, the effective range is 0 V to 1.28 V in our example.10
1.25 V is used as the reference voltage to the auxiliary ADC when internal V REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.
11
In Bipolar mode, the auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits. The bipolar range is still –V REF to +V REF ; however, the negative voltage is limited to –30 mV .
12 The ADuC836BCP (CSP package) has been qualified and tested with the base of the CSP package floating.13Pins configured in SPI mode, pins configured as digital inputs during this test.14Pins configured in I 2C mode only.
15Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
16Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 Kcycles.17
Retention lifetime equivalent at junction temperature (T J ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section.
18
Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions:
Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in Power-Down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.
19
DV DD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
REV. A
ADuC836
–9–
ORDERING GUIDE
Model
Temperature Range Package Description Package Option ADuC836BS –40°C to +125°C 52-Lead Metric Quad Flat Package S-52ADuC836BCP
–40°C to +85°C 56-Lead Lead Frame Chip Scale Package CP-56
EVAL-ADuC836QS
QuickStart Development System
ABSOLUTE MAXIMUM RATINGS 1
(T A = 25°C, unless otherwise noted.)
AV DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AV DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DV DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DV DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND 2 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AV DD to DV DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V Analog Input Voltage to AGND 3 . . . . . . –0.3 V to AV DD + 0.3 V Reference Input Voltage to AGND . . . . –0.3 V to AV DD + 0.3 V AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . . . –0.3 V to DV DD + 0.3 V Digital Output Voltage to DGND . . . . . –0.3 V to DV DD + 0.3 V Operating T emperature Range . . . . . . . . . . . . –40°C to +125°C Storage T emperature Range . . . . . . . . . . . . . . –65°C to +150°C Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance (MQFP) . . . . . . . . . . . . . . . . . 90°C/W JA Thermal Impedance (LFCSP Base Floating) . . . . . . 52°C/W Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES 1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2
AGND and DGND are shorted internally on the ADuC836.3
Applies to P1.2 to P1.7 pins operating in analog or digital input modes.
PIN CONFIGURATIONS
52-Lead MQFP
?
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56-Lead LFCSP
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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. A
ADuC836
–10–
PIN FUNCTION DESCRIPTIONS
Pin No. Pin No.52-Lead 56-Lead
MQFP CSP Mnemonic T ype * Description
1, 2 56, 1 P1.0/P1.1 I/O P1.0 and P1.1 can function as digital inputs or digital outputs and have a pull-up
configuration as described for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA.
P1.0/T2/PWM0 I/O P1.0 and P1.1 also have various secondary functions as described below. P1.0 can be
used to provide a clock input to Timer 2. When enabled, Counter 2 is incremented in response to a negative transition on the T2 input pin. If the PWM is enabled, the PWM0 output will appear at this pin.
P1.1/T2EX/PWM1I/O P1.1 can also be used to provide a control input to Timer 2. When enabled, a PWM1
negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. If the PWM is enabled, the PWM1 output will appear at this pin.3–4, 2–3, P1.2–P1.7 I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input 9–12 11–14 for which 0 must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: P1.2/DAC/IEXC1 I/O The voltage output from the DAC or one or both current sources (200 μA or 2 200 μA) can be configured to appear at this pin.
P1.3/AIN5/IEXC2 I/O Auxiliary ADC input or one or both current sources can be configured at this pin.
AIN3AIN4AIN5
AIN1AIN2
REFIN REFIN
IEXC 2IEXC 1A V D D
A G N D
D G N D
S C L O C K
M O S I /S D A T A
M I S O
S S
X T A L P 0.0 (A D 0)
P 0.1 (A D 1)
P 0.3 (A D 3)
P 0.4 (A D 4)
P 0.5 (A D 5)
P 0.6 (A D 6)
P 0.7 (A D 7)
P 0.2 (A D 2)
E A
P S E N
T X D
R X D
X T A L 2
P 1.0 (T 2)
P 1.1 (T 2E X )
P 1.2 (D A C /I E X C 1)
P 1.4 (A I N 1)
P 1.5 (A I N 2)
P 1.6 (A I N 3)
P 1.7 (A I N 4/D A C )
P 1.3 (A I N 5/I E X C 2)
P 2.0 (A 8/A 16)
P 2.1 (A 9/A 17)
P 2.2 (A 10/A 18)
P 2.3 (A 11/A 19)
P 2.4 (A 12/A 20)
P 2.5 (A 13/A 21)
P 2.6 (A 14/A 22)
P 2.7 (A 15/A 23)
P 3.0 (R X D )
P 3.1 (T X D )
P 3.2 (I N T 0)
P 3.3 (I N T 1)
P 3.4 (T 0/P W M C L K )
P 3.5 (T 1)
P 3.7 (R D )
P 3.6 (W R )
A L E
R E S E T
D V D D
*PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE
SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC836 OVER THE ADuC816
Figure 1. Detailed Block Diagram
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PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Pin No.52-Lead 56-Lead
MQFP CSP Mnemonic T ype * Description
P1.4/AIN1 I Primary ADC, Positive Analog Input P1.5/AIN2 I Primary ADC, Negative Analog Input
P1.6/AIN3 I Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input
P1.7/AIN4/DAC I/O Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin.5 4, 5 AV DD S Analog Supply Voltage, 3 V or 5 V
6 6, 7, 8 AGND S Analog Ground. Ground reference pin for the analog circuitry.
7 9 REFIN(–) I Reference Input, Negative T erminal
8 10 REFIN(+) I Reference Input, Positive T erminal
13 15 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.14 16 MISO I/O Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this input pin.15 17 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is
running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin.16–19, 18–21, P3.0–P3.7 I/O P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that 22–25 24–27 have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions including: P3.0/RXD I/O Receiver Data for UART Serial Port P3.1/TXD I/O Transmitter Data for UART Serial Port
P3.2/INT0 I/O External Interrupt 0. This pin can also be used as a gate control input to Timer 0. P3.3/INT1 I/O External Interrupt 1. This pin can also be used as a gate control input to Timer 1. P3.4/T0/PWMCLK I/O Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be input at this pin.
P3.5/T1 I/O Timer/Counter 1 External Input
P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory.
P3.7/RD I/O External Data Memory Read Strobe. Enables the data from an external data memory to Port 0.
20, 34, 48 22, 36, 51, DV DD S Digital Supply, 3 V or 5 V
21, 35, 47 23, 37, 38, DGND S Digital Ground. Ground reference point for the digital circuitry. 50
26 SCLOCK I/O Serial Interface Clock for either the I 2C or SPI Interface. As an input, this pin is a
Schmitt-triggered input, and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin.27 MOSI/SDATA I/O Serial Data I/O for the I 2C Interface or Master Output/Slave Input for the
SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin.28–31 30–33 P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s 36–39 39–42 (A8–A15) written to them are pulled high by the internal pull-up resistors, and in that state can (A16–A23) be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors.
Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space.
32 34 XTAL1 I Input to the Crystal Oscillator Inverter
33 35 XTAL2 O Output from the Crystal Oscillator Inverter. (See the Hardware Design Considerations
section for description.)REV. A
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–12–PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Pin No.52-Lead 56-Lead
MQFP CSP Mnemonic T ype * Description
40 43 EA I/O External Access Enable, Logic Input. When held high, this input enables the device to
fetch code from internal program memory locations 0000h to F7FFh. When held low, this input enables the device to fetch all instructions from external program memory. T o determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle.EA may also be used as an external emulation I/O pin, and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution.41 44 PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the
external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable Serial
Download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle.42 45 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR.43–46 46–49 P0.0–P0.7 I/O These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional
49–52 52–55 (AD0–AD3) I/O port. Port 0 pins that have 1s written to them float and in that state can be used
(AD4–AD7)as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s.
*I = Input, O = Output, S = Supply.
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MEMORY ORGANIZATION
The ADuC836 contains four different memory blocks:
62 Kbytes of On-Chip Flash/EE Program Memory 4 Kbytes of On-Chip Flash/EE Data Memory 256 bytes of General-Purpose RAM
2 Kbytes of Internal XRAM
(1) Flash/EE Program Memory
The ADuC836 provides 62 Kbytes of Flash/EE program mem-ory to run user code. The user can choose to run code from this internal memory or run code from an external program memory.If the user applies power or resets the device while the EA pin is pulled low externally, the part will execute code from the external program space; otherwise, if EA is pulled high externally, the part defaults to code execution from its internal 62 Kbytes of Flash/EE program memory.
Unlike the ADuC816, where code execution can overflow from the internal code space to external code space once the PC becomes greater than 1FFFH, the ADuC836 does not support the rollover from F7FFH in internal code space to F800H in external code space. Instead, the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code.
Permanently embedded firmware allows code to be serially down-loaded to the 62 Kbytes of internal code space via the UART serial port while the device is in-circuit. No external hardware is required.56 Kbytes of the program memory can be reprogrammed during runtime; thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. This is discussed in more detail in the Flash/EE Memory section.
(2) Flash/EE Data Memory
4 Kbytes of Flash/EE Data Memory are available to the user and can be accessed indirectly via a group of registers mapped into the Special Function Register (SFR) area. Access to the Flash/EE Data memory is discussed in detail in the Flash/EE Memory section.
(3) General-Purpose RAM
The general-purpose RAM is divided into two separate memories: the upper and lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing; the upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space, which can only be accessed through direct addressing.
The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits), locations 20H through 2FH above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the inter-nal memory address space, and the stack depth can be expanded up to 2048 bytes.
Reset initializes the stack pointer to location 07H. Any call or push pre-increments the SP before loading the stack. Therefore, loading the stack starts from location 08H, which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage.
BANKS SELECTED
VIA
11
10
01
00
Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM
The ADuC836 contains 2 Kbytes of on-chip extended data mem-ory. This memory, although on-chip, is accessed via the MOVX instruction. The 2 Kbytes of internal XRAM are mapped into the bottom 2 Kbytes of the external address space if the CFG836.0 bit is set. Otherwise, access to the external data memory will occur just like a standard 8051.
Even with the CFG836.0 bit set, access to the external XRAM will occur once the 24-bit DPTR is greater than 0007FFH.
CFG836.0 = 0
CFG836.0 = 1
Figure 3. Internal and External XRAM
GENERAL NOTES PERTAINING TO THIS DATA SHEET
1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state, unless otherwise stated.
2. SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC836 hardware, unless otherwise stated.
3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products.
4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP package, unless otherwise stated.
REV. A
ADuC836
–14–When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a stan-dard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O.
The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM. On the ADuC836 however, it is possible (by setting CFG836.7) to enable the 11-bit extended stack pointer. In this case, the stack will roll over from FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is visible in the SP and SPH SFRs. The SP SFR is located at 81H as with a standard 8052. The SPH SFR is located at B7H. The 3 LSBs of this SFR contain the three extra bits necessary to
extend the 8-bit stack pointer into an 11-bit stack pointer.
07FFH
Figure 4. Extended Stack Pointer Operation
External Data Memory (External XRAM)
Just like a standard 8051 compatible core, the ADuC836 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory.
The ADuC836, however, can access up to 16 Mbytes of external data memory. This is an enhancement of the 64 Kbytes external data memory space available on a standard 8051 compatible core.The external data memory is discussed in more detail in the ADuC836 Hardware Design Considerations section.
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip periph-erals. A block diagram showing the programming model of the ADuC836 via the SFR area is shown in Figure 5.
Figure 5. Programming Model
All registers, except the Program Counter (PC) and the four general-purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals.
Accumulator SFR (ACC)
ACC is the Accumulator Register, which is used for math operations including addition, subtraction, integer multiplication, and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions, refer to the Accumulator as A.
B SFR (B)
The B Register is used with the ACC for multiplication and division operations. For other instructions, it can be treated as a general-purpose scratch pad register.
Data Pointer (DPTR)
The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte), and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL).
The ADuC836 supports dual data pointers. For more information, refer to the Dual Data Pointer section.
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T able II. PCON SFR Bit Designations
Bit Name Description
7 SMOD Double UART Baud Rate
6 SERIPD SPI Power-Down Interrupt Enable 5 INT0PD INT0 Power-Down Interrupt Enable 4 ALEOFF Disable ALE Output 3 GF1 General-Purpose Flag Bit 2 GF0 General-Purpose Flag Bit 1 PD Power-Down Mode Enable 0 IDL Idle Mode Enable
ADuC836 CONFIGURATION SFR (CFG836)
The CFG836 SFR contains the necessary bits to configure the internal XRAM and the extended SP . By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled.
SFR Address AFH Power-On Default Value 00H Bit Addressable No
T able III. CFG836 SFR Bit Designations
Bit Name Description
7 EXSP Extended SP Enable. If this bit is set, the
stack will roll over from SPH/SP = 00FFH to 0100H. If this bit is clear, the SPH SFR will be disabled and the stack will roll over from SP = FFH to SP = 00H.
6 ––– Reserved for Future Use 5 ––– Reserved for Future Use 4 ––– Reserved for Future Use 3 ––– Reserved for Future Use 2 ––– Reserved for Future Use 1 ––– Reserved for Future Use
0 XRAMEN XRAM Enable Bit. If this bit is set, the in-ternal XRAM will be mapped into the lower 2 Kbytes of the external address space. If this bit is clear, the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2 Kbytes of external data memory (see Figure 3).
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the “top of the stack.” The SP Regis ter is incremented before data is stored, during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP Register is initialized to 07H after a reset. This causes the stack to begin at location 08H.
As mentioned earlier, the ADuC836 offers an extended 11-bit stack pointer. The three extra bits that make up the 11-bit stack pointer are the 3 LSBs of the SPH byte located at B7H.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status of the CPU as detailed in T able I.SFR Address D0H Power-On Default Value 00H Bit Addressable Y es
T able I. PSW SFR Bit Designations
Bit Name Description
7 CY Carry Flag
6 AC Auxiliary Carry Flag 5 F0 General-Purpose Flag 4 RS1 Register Bank Select Bits
3 RS0 RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 32 OV Overflow Flag
1 F1 General-Purpose Flag 0 P Parity Bit
Power Control SFR (PCON)
The PCON SFR contains bits for power saving options and general-purpose status flags, as shown in T able II.
The TIC (Wake-Up/RTC timer) can be used to accurately wake up the ADuC836 from power-down at regular intervals. T o use the TIC to wake up the ADuC836 from power-down, the OSC_PD bit in the PLLCON SFR must be clear and the TIC must be enabled.
SFR Address 87H Power-On Default Value 00H Bit Addressable No
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–16–
BIT MNEMONIC THESE BITS ARE CONTAINED IN THIS BYTE.
BIT VALUE
SFR MAP KEY:
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT ADDRESSABLE.
NOTES
1CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.2THESE SFRs MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1.
Figure 6. Special Function Register Locations and T heir Reset Default Values
COMPLETE SFR MAP
Figure 6 shows a full SFR memory map and the SFR con-tents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are
not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software.
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ADC SFR INTERFACE
Both ADCs are controlled and configured via a number of SFRs that are summarized here and described in more detail in the following sections.
ADCSTAT ADC Status Register. Holds general status of the
primary and auxiliary ADCs.ADCMODE ADC Mode Register. Controls general modes of
operation for primary and auxiliary ADCs ADC0CON Primary ADC Control Register. Controls specific
configuration of primary ADC.ADC1CON Auxiliary ADC Control Register. Controls
specific configuration of auxiliary ADC.SF Sinc Filter Register. Configures the decimation
factor for the Sinc 3 filter and thus the primary and auxiliary ADC update rates.ICON Current Source Control Register. Allows the user
to control of the various on-chip current source options.
ADC0M/H Primary ADC 16-bit conversion result is held in
these two 8-bit registers.ADC1L/H Auxiliary ADC 16-bit conversion result is held in
these two 8-bit registers.OF0M/H Primary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.OF1L/H Auxiliary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.GN0M/H Primary ADC 16-bit Gain Calibration Coefficient
is held in these two 8-bit registers.GN1L/H Auxiliary ADC 16-bit Gain Calibration Coefficient
is held in these two 8-bit registers.
ADCSTAT (ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions such as reference detect and conversion overflow/underflow flags.SFR Address D8H Power-On Default Value 00H Bit Addressable Y es
T able IV . ADCSTAT SFR Bit Designations
Bit Name Description
7 RDY0 Ready Bit for Primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conversion or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared.6 RDY1 Ready Bit for Auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC.5 CAL Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
4 NOXREF No External Reference Bit (only active if primary or auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When set, conversion results are clamped to all ones, if using external reference.
Cleared to indicate valid V REF .
3 ERR0 Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC.1 ––– Reserved for Future Use 0 ––– Reserved for Future Use
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–18–ADCMODE (ADC Mode Register)
Used to control the operational mode of both ADCs.SFR Address D1H Power-On Default Value 00H Bit Addressable No
T able V . ADCMODE SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use 6 ––– Reserved for Future Use
5 ADC0EN Primary ADC Enable.
Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0, below.Cleared by the user to place the primary ADC in power-down mode.4 ADC1EN Auxiliary ADC Enable.
Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0, below.Cleared by the user to place the auxiliary ADC in power-down mode.3 ––– Reserved for Future Use
2 MD2 Primary and Auxiliary ADC Mode bits.
1 MD1 These bits select the operational mode of the enabled ADC as follows: 0 MD0 MD2
MD1 MD00 0 0 ADC Power-Down Mode (Power-On Default)
0 0 1 Idle Mode. The ADC filter and modulator are held in a reset state although the modulator clocks are still provided.
0 1 0 Single Conversion Mode. A single conversion is performed on the enabled ADC.
On completion of the conversion, the ADC data registers (ADC0H/M and/or ADC1H/L) are updated, the relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0 accordingly being written to 000.
0 1 1 Continuous Conversion. The ADC data registers are regularly updated at the selected update rate (see SF Register).
1 0 0 Internal Zero-Scale Calibration. Internal short automatically connected to the enabled ADC input(s).
1 0 1 Internal Full-Scale Calibration. Internal or external V REF (as determined by XREF0 and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC input(s) for this calibration.
1 1 0 System Zero-Scale Calibration. User should connect system zero-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register.
1 1 1 System Full-Scale Calibration. User should connect system full-scale input to the enabled ADC input(s) as selected by the CH1/CH0 and ACH1/ACH0 bits in the
ADC0/1CON Register.
NOTES
1.Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.)
2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is given priority over the auxiliary ADC, and any change requested on the primary ADC is immediately responded to.
3.On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the auxiliary ADC will be delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC.
4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in Power-Down mode.
5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.
6. Calibrations are performed at maximum SF (see SF SFR) value, guaranteeing optimum calibration operation.
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ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register)
The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, range (the auxiliary ADC operates on a fixed input range of ±V REF ).ADC0CON Primary ADC Control SFR SFR Address D2H Power-On Default Value 07H Bit Addressable No ADC1CON Auxiliary ADC Control SFR SFR Address D3H Power-On Default Value 00H Bit Addressable No
T able VI. ADC0CON SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use
6 XREF0 Primary ADC External Reference Select Bit.
Set by user to enable the primary ADC to use the external reference via REFIN(+)/REFIN(–).Cleared by user to enable the primary ADC to use the internal band gap reference (V REF = 1.25 V).
5 CH1 Primary ADC Channel Selection Bits.
4 CH0 Written by the user to select the differential input pairs used by the primary ADC as follows:
CH1 CH0 Positive Input Negative Input 0 0 AIN1 AIN20 1 AIN3 AIN41 0 AIN2 AIN2 (Internal Short)1 1 AIN3 AIN2
3 UNI0 Primary ADC Unipolar Bit.
Set by user to enable unipolar coding, i.e., zero differential input will result in 000000H output.Cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000H output.
2 RN2 Primary ADC Range Bits.
1 RN1 Written by the user to select the primary ADC input range as follows:0 RN0 RN
2 RN1 RN0 Selected Primary ADC Input Range (V REF = 2.5 V )
0 0 0 ±20 mV (0 mV–20 mV in Unipolar Mode)0 0 1 ±40 mV (0 mV–40 mV in Unipolar Mode)0 1 0 ±80 mV (0 mV–80 mV in Unipolar Mode)0 1 1 ±160 mV (0 mV–160 mV in Unipolar Mode)1 0 0 ±320 mV (0 mV–320 mV in Unipolar Mode)1 0 1 ±640 mV (0 mV–640 mV in Unipolar Mode)1 1 0 ±1.28 V (0 V–1.28 V in Unipolar Mode)1 1 1 ±2.56 V (0 V–2.56 V in Unipolar Mode)
T able VII. ADC1CON SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use
6 XREF1 Auxiliary ADC External Reference Bit.
Set by user to enable the auxiliary ADC to use the external reference via REFIN(+)/REFIN(–).Cleared by user to enable the auxiliary ADC to use the internal band gap reference.
5 ACH1 Auxiliary ADC Channel Selection Bits.
4 ACH0 Written by the user to select the single-ended input pins used to drive the auxiliary ADC as follows:
ACH1 ACH0 Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 T emp Sensor AGND (T emp Sensor routed to the ADC input)1 1 AIN5 AGND
3 UNI1 Auxiliary ADC Unipolar Bit.
Set by user to enable unipolar coding, i.e., zero input will result in 0000H output.Cleared by user to enable bipolar coding, i.e., zero input will result in 8000H output.
2 ––– Reserved for Future Use 1 ––– Reserved for Future Use 0 ––– Reserved for Future Use
NOTES
1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding.
2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0°C.
3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H Register ADC conversion result.
REV. A
ADuC836
–20–ADC0H/ADC0M (Primary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the primary ADC.SFR Address ADC0H High Data Byte DBH ADC0M Middle Data Byte DAH Power-On Default Value 00H ADC0H, ADC0M Bit Addressable No ADC0H, ADC0M
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.SFR Address ADC1H High Data Byte DDH ADC1L Low Data Byte DCH Power-On Default Value 00H ADC1H, ADC1L Bit Addressable No ADC1H, ADC1L
OF0H/OF0M (Primary ADC Offset Calibration Registers *)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address OF0H Primary ADC Offset Coefficient High Byte E3H OF0M Primary ADC Offset Coefficient Middle Byte E2H Power-On Default Value 80000H OF0H, OF0M respectively Bit Addressable No OF0H, OF0M
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers *)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address OF1H Auxiliary ADC Offset Coefficient High Byte E5H OF1L Auxiliary ADC Offset Coefficient Low Byte E4H Power-On Default Value 8000H OF1H and OF1L, respectively Bit Addressable No OF1H, OF1L
GN0H/GN0M (Primary ADC Gain Calibration Registers *)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address GN0H Primary ADC Gain Coefficient High Byte EBH GN0M Primary ADC Gain Coefficient Middle Byte EAH Power-On Default Value Configured at Factory Final T est; See Notes above.Bit Addressable No GN0H, GN0M
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers *)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address GN1H Auxiliary ADC Gain Coefficient High Byte EDH GN1L Auxiliary ADC Gain Coefficient Low Byte ECH Power-On Default Value Configured at Factory Final T est; see notes above.Bit Addressable No GN1H, GN1L
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
REV. A