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K4S560832D中文资料

256Mbit SDRAM

8M x 8bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 1.1

May. 2003

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.1 May. 2003

Revision History

Revision 0.0 (Jan. , 2002)

- First release

Revision 0.1(May., 2003)

- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.

Rev. 1.1 May. 2003

V DD

DQ0 V DDQ

N.C

DQ1

V SSQ

N.C

DQ2 V DDQ

N.C

DQ3

V SSQ

N.C

V DD

N.C

CAS

RAS

BA0

BA1 A10/AP

V DD 1

PIN CONFIGURATION (Top view)

V SS

DQ7

V SSQ

N.C

DQ6

V DDQ

N.C

DQ5

V SSQ

N.C

DQ4

V DDQ

N.C

V SS

N.C/RFU

DQM

CLK

CKE

A12

A11

A6 A5 A4 V SS

54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitcH)

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS Chip select Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.

A0 ~ A12Address Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE Write enable Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~7Data input/output Data inputs/outputs are multiplexed on the same pins.

V DD/V SS Power supply/ground Power and ground for the input buffers and the core logic.

V DDQ/V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

Rev. 1.1 May. 2003

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD , V DDQ

-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150

°C Power dissipation P D 1W Short circuit current

I OS

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage V DD , V DDQ

3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mA

Input leakage current

I LI

-10

31. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V IN ≤ V DDQ .

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :1. -75/7C only specify a maximum value of 3.5pF

2. -75/7C only specify a maximum value of

3.8pF 3. -75/7C only specify a maximum value of 6.0pF

Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)

Symbol Min Max Unit Note Clock

C CLK 2.5 4.0pF 1RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0pF 2Address C AD

D 2.5 5.0pF 2DQ 0 ~ DQ 15

C OUT

4.0

6.5

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)

Parameter Symbol Test Condition

Version

Unit Note -7C-75-1H-1L

Operating current (One bank active)I CC1

Burst length = 1

t RC ≥ t RC(min)

I O = 0 mA

100909090mA1

Precharge standby cur-rent in power-down mode

I CC2P CKE ≤ V IL(max), t CC = 10ns2

mA I CC2PS CKE & CLK ≤ V IL(max), t CC = ∞2

Precharge standby cur-rent in non power-down mode

I CC2N

CKE ≥ V IH(min), CS ≥ V IH(min), t CC = 10ns

Input signals are changed one time during 20ns

mA I CC2NS

CKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞

Input signals are stable

Active standby current in power-down mode

I CC3P CKE ≤ V IL(max), t CC = 10ns6

mA I CC3PS CKE & CLK ≤ V IL(max), t CC = ∞6

Active standby current in non power-down mode (One bank active)

I CC3N

CKE ≥ V IH(min), CS ≥ V IH(min), t CC = 10ns

Input signals are changed one time during 20ns

30mA I CC3NS

CKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞

Input signals are stable

25mA

Operating current (Burst mode)I CC4

I O = 0 mA

Page burst

4banks Activated.

t CCD = 2CLKs

110110100100mA1

Refresh current I CC5t RC ≥ t RC(min)220200190190mA2

Self refresh current I CC6CKE ≤ 0.2V C3mA3 L 1.5mA4

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S560832D-TC**

4. K4S560832D-TL**

5. Unless otherwise noticed, input swing level is CMOS(V IH/V IL=V DDQ/V SSQ).

Notes :

Rev. 1.1 May. 2003

AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)

Parameter Value Unit AC input levels (Vih/Vil)

2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall time

tr/tf = 1/1ns Output timing measurement reference level 1.4V

Output load condition

See Fig. 2

3.3V

1200?

870?

Output

50pF

V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA

Vtt = 1.4V

50?

Output

50pF

Z0 = 50?

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-7C

-75-1H -1L Row active to row active delay t RRD (min)15152020ns 1RAS to CAS delay t RCD (min)15202020ns 1Row precharge time t RP (min)15202020ns 1Row active time

t RAS (min)45

ns 1

t RAS (max)

100

us Row cycle time

t RC (min)60

ns 1Last data in to row precharge t RDL (min)2CLK 2, 5Last data in to Active delay

t DAL (min) 2 CLK + tRP

-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stop

t BDL (min)1CLK 2Col. address to col. address delay t CCD (min)

1CLK 3Number of valid output data

CAS latency=32ea

4CAS latency=2

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .

Notes :

Rev. 1.1 May. 2003

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol Condition Min Typ

Max Unit Notes Output rise time

trh

Measure in linear region : 1.2V ~ 1.8V 1.37

4.37

Volts/ns

Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3

Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall time

tfh

Measure in linear region : 1.2V ~ 1.8V

2.0

2.9

5.0

Volts/ns

1,2

1. Rise time specification based on 0pF + 50 ? to V SS , use these values to design to.

2. Fall time specification based on 0pF + 50 ? to V DD , use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to V SS .

Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

-7C

-75

-1H

-1L Unit Note

Min

Max Min Max Min Max Min Max CLK cycle time

CAS latency=3t CC

7.51000

101000

CAS latency=2

7.5

CLK to valid output delay CAS latency=3t SAC 5.4 5.466ns

1,2

CAS latency=2 5.4

Output data hold time

CAS latency=3t OH

3333ns 2CAS latency=2

3333CLK high pulse width t CH 2.5 2.533ns 3CLK low pulse width t CL 2.5 2.533ns 3Input setup time t SS 1.5 1.522ns 3Input hold time t SH 0.80.811ns 3CLK to output in Low-Z t SLZ 1

CLK to output in Hi-Z

CAS latency=3t SHZ 5.4 5.466ns

CAS latency=2

5.4

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

I OH Characteristics (Pull-up)

Voltage 100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

(V)I (mA)I (mA)I (mA)

3.45 -2.4

3.3 -27.3

3.0 0.0 -7

4.1 -0.7

2.6-21.1-129.2 -7.5

2.4-34.1-15

3.3-13.3

2.0-58.7-197.0-27.5

1.8-67.3-226.2-35.5

1.65-73.0-248.0-41.1

1.5-77.9-269.7-47.9

1.4-80.8-284.3-5

2.4

1.0-88.6-344.5-7

2.5

0.0-93.0-502.4-93.0 IBIS SPECIFICATION

I OL Characteristics (Pull-down)

Voltage 100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

(V)I (mA)I (mA)I (mA) 0.0 0.0 0.0 0.0 0.427.5 70.217.7 0.6541.8107.526.9

0.8551.6133.833.3

1.058.0151.237.6 1.470.7187.746.6 1.57

2.9194.448.0 1.6575.4202.549.5 1.877.0208.650.7 1.9577.6212.051.5

3.080.3219.65

4.2 3.4581.4222.654.9

-100

-200

-300

-400

-500

-600

0.51 1.52 2.5 3.5

Voltage

250

200

150

100

0.51 1.52 2.5 3.5

Voltage

66MHz and 100MHz/133MHz Pull-up

66MHz and 100MHz/133MHz Pull-down

I OH Min (100MHz)

I OH Max (66 and 100MHz)

I OH Min (66MHz)

I OL Min (100MHz)

I OL Max (100MHz)

I OL Min (66MHz)

Rev. 1.1 May. 2003

V DD Clamp @ CLK, CKE, CS, DQM & DQ

V DD (V)I (mA)

0.00.0

0.20.0

0.40.0

0.60.0

0.70.0

0.80.0

0.90.0

1.0 0.23

1.2 1.34

1.4 3.02

1.6 5.06

1.8 7.35

2.0 9.83

2.212.48

2.415.30

2.618.31

V SS Clamp @ CLK, CKE, CS, DQM & DQ V SS (V)I (mA)

-2.6-57.23

-2.4-45.77

-2.2-38.26

-2.0-31.22

-1.8-24.58

-1.6-18.37

-1.4-12.56

-1.2 -7.57

-1.0 -3.37

-0.9 -1.75

-0.8 -0.58

-0.7 -0.05

-0.6 0.0

-0.4 0.0

-0.2 0.0

0.0 0.0

Voltage

I (mA)

Voltage

I (mA)

Minimum V DD clamp current

(Referenced to V DD)

Minimum V SS clamp current

-10

-20

-30

-40

-30

-2-1

-50

-60

Rev. 1.1 May. 2003

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don't care, H=Logic high, L=Logic low)Command

CKEn-1

CKEn

RAS

CAS

DQM

BA 0,1

A 10/AP

A 11,A 12,A 9 ~ A 0

Note

Mode register set H X L L L L X OP code

1,2Refresh

Auto refresh

H L L L H X

3Self refresh

Entry L 3

Exit

L H L H H H X X

X X X 3

Bank active & row addr.H X L L H H X V Row address Read &

column address Auto precharge disable H

L Column address (A 0 ~ A 9)4Auto precharge enable H

4,5Write &

column address Auto precharge disable H X L H L L X V

L Column address (A 0 ~ A 9)

4Auto precharge enable

H 4,5Burst stop H X L H H L X X

Precharge

Bank selection H

L L H L X

V L X

All banks

Clock suspend or active power down

Entry H L H X X X X X

V V V Exit L H X X X X X Precharge power down mode

Entry

H X X X X

H H H Exit

L H

H X X X X L

V V

DQM

H V

X 7

No operation command

H X X X X

Notes :X

1. OP Code : Operand code

A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.

If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)