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74LVX74TTR中文资料

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August 2004

HIGH SPEED:

f MAX = 145MHz (TYP.) at V CC = 3.3V s 5V TOLERANT INPUTS s

INPUT VOLTAGE LEVEL:V IL =0.8V, V IH =2V AT V CC =3V s

LOW POWER DISSIPATION:I CC = 2 μA (MAX.) at T A =25°C s

LOW NOISE:

V OLP = 0.3V (TYP .) at V CC = 3.3V

SYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 4mA (MIN)

BALANCED PROPAGATION DELAYS:t PLH ? t PHL

OPERATING VOLTAGE RANGE:

V CC (OPR) = 2V to 3.6V (1.2V Data Retention)s

PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74

s IMPROVED LATCH-UP IMMUNITY

POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.

A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

74LVX74

LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS)

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE T & R SOP 74LVX74MTR TSSOP

74LVX74TTR

74LVX74

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Figure 2: Input Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Figure 3: Logic Diagram

PIN N°SYMBOL NAME AND FUNCTION 1, 131CLR, 2CLR Asynchronous Reset - Direct Input 2, 121D, 2D Data Inputs 3, 11

1CK, 2CK

Clock Input

(LOW to HIGH, Edge Triggered)

4, 101PR, 2PR Asynchronous Set - Direct Input

5, 91Q, 2Q True Flip-Flop Outputs 6, 81Q, 2Q Complement Flip-Flop Outputs

7GND Ground (0V)

V CC

Positive Supply Voltage

74LVX74

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Table 4: Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

Table 5: Recommended Operating Conditions

1) Truth Table guaranteed: 1.2V to 3.6V 2) V IN from 0.8V to 2.0V

Table 6: DC Specifications

Symbol Parameter

Value Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage -0.5 to +7.0V V O DC Output Voltage -0.5 to V CC + 0.5

V I IK DC Input Diode Current - 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 25mA I CC or I GND DC V CC or Ground Current

± 50mA T stg Storage Temperature -65 to +150

°C T L

Lead Temperature (10 sec)

300

°C

Symbol Parameter

Value Unit V CC Supply Voltage (note 1) 2 to 3.6V V I Input Voltage 0 to 5.5V V O Output Voltage 0 to V CC V T op Operating Temperature

-55 to 125°C dt/dv

Input Rise and Fall Time (note 2) (V CC = 3.3V)

0 to 100

ns/V

Symbol

Parameter

Test Condition

Value Unit

V CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.

Max.

Min.Max.

V IH

High Level Input Voltage

2.0 1.5 1.5 1.5V

3.0 2.0 2.0 2.03.6 2.4

2.4

V IL

Low Level Input Voltage

2.00.50.50.5V

3.00.80.80.83.60.8

0.8

0.8V OH

High Level Output Voltage

2.0I O =-50 μA 1.9 2.0 1.9 1.9V

3.0I O =-50 μA 2.9 3.0

2.9 2.9

3.0

I O =-4 mA 2.58

2.48

2.4

V OL

Low Level Output Voltage

2.0I O =50 μA 0.00.10.10.1V

3.0I O =50 μA 0.0

0.10.10.13.0

I O =4 mA 0.360.440.55I I Input Leakage Current

3.6V I = 5V or GND ± 0.1± 1± 1μA I CC

Quiescent Supply Current

3.6

V I = V CC or GND

μA

74LVX74

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Table 7: Dynamic Switching Characteristics

1) Worst case package.

2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ILD ), 0V to threshold (V IHD ), f=1MHz.

Table 8: AC Electrical Characteristics (Input t r = t f = 3ns)

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V

Symbol

Parameter

Test Condition

Value Unit

V CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.

Max.

Min.

Max.

V OLP Dynamic Low Voltage Quiet Output (note 1, 2) 3.3C L = 50 pF

0.30.5

V OLV -0.5-0.3

V IHD Dynamic High Voltage Input (note 1, 3)

3.32

V ILD

Dynamic Low Voltage Input (note 1, 3)

3.3

0.8

Symbol

Parameter

Test Condition

Value Unit V CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.

Typ.Max.Min.Max.Min.Max.t PLH t PHL Propagation Delay Time

CK to Q or Q

2.7157.315.0 1.018.5 1.018.5ns

2.7509.818.5 1.022.0 1.022.0

3.3(*)

15 5.79.7 1.011.5 1.011.53.3(*)

508.213.2 1.015.0 1.015.0t PLH t PHL Propagation Delay Time PR or CLR to Q or Q 2.7

158.415.6 1.018.5 1.018.5ns

2.7

5010.919.1 1.022.0 1.022.03.3(*)

15 6.610.1 1.012.0 1.012.03.3(*)509.1

13.6 1.0

15.5 1.0

15.5t w Minimum Pulse Width HIGH or LOW, CK 2.7508.510.010.0ns 3.3(*)50 6.07.07.0t w(L)Minimum Pulse Width LOW PR or CLR

2.7

508.510.010.0ns 3.3(*)

50 6.07.07.0t s Minimum Setup Time D to CK HIGH or LOW

2.7508.09.59.5ns

3.3(*)

50 5.5 6.5 6.5t h Minimum Hold Time D to CK HIGH or LOW

2.7500.50.50.5ns

3.3(*)

500.50.50.5t REM Minimum Removal Time PR or CLR to CK

2.750 6.57.57.5ns

3.3(*)

50 5.0

5.0

f MAX

Maximum Clock Frequency 2.715551355050MHz

2.7

50456040403.3(*)

159514580803.3(*)5060

8550

t OSLH t OSHL

Output To Output Skew Time (note1, 2)

2.7500.5 1.0 1.5 1.5ns

3.3(*)

0.5

1.0

1.5

74LVX74

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Table 9: Capacitive Characteristics

1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /2 (per circuit)

Figure 4: Test Circuit

C L =15/50pF or equivalent (includes jig and probe capacitance)R T = Z OUT of pulse generator (typically 50?)

Symbol

Parameter

Test Condition

Value Unit

V CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.

Typ.Max.Min.

Max.Min.

Max.C IN Input Capacitance 3.3410

pF C PD

Power Dissipation Capacitance (note 1)

3.3

f IN = 10 MHz

74LVX74

Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)

Figure 6: Waveform - Recovery Time (f=1MHz; 50% duty cycle)

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74LVX74 Figure 7: Waveform - Propagation Delays, Minimum Pulse Width (f=1MHz; 50% duty cycle)

Figure 8: Waveform - Minimum Pulse Width

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74LVX74

8/13DIM.

mm.inch

MIN.TYP MAX.MIN.TYP.MAX.

A 1.35 1.750.0530.069 A10.10.250.0040.010 A2 1.10 1.650.0430.065 B0.330.510.0130.020 C0.190.250.0070.010 D8.558.750.3370.344 E 3.8 4.00.1500.157 e 1.270.050

H 5.8 6.20.2280.244 h0.250.500.0100.020 L0.4 1.270.0160.050 k0°8°0°8°ddd0.1000.004

SO-14 MECHANICAL DATA

0016019D

74LVX74

9/13

DIM.

mm.

inch

MIN.

TYP

MAX.MIN.

TYP.

MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.039

0.041b 0.190.300.0070.012c 0.090.200.0040.0089D 4.95 5.10.1930.1970.201E 6.2 6.4 6.60.2440.2520.260E1 4.3

4.4 4.48

0.169

0.1730.176

e 0.65 BSC

0.0256 BSC

K 0?8?0?8?L

0.45

0.60

0.75

0.018

0.024

0.030

TSSOP14 MECHANICAL DATA

A E1

PIN 1 IDENTIFICATION

0080337D

74LVX74

Tape & Reel SO-14 MECHANICAL DATA

mm.inch DIM.

MIN.TYP MAX.MIN.TYP.MAX.

A33012.992 C12.813.20.5040.519 D20.20.795

N60 2.362

T22.40.882 Ao 6.4 6.60.2520.260 Bo99.20.3540.362 Ko 2.1 2.30.0820.090 Po 3.9 4.10.1530.161 P7.98.10.3110.319

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74LVX74 Tape & Reel TSSOP14 MECHANICAL DATA

mm.inch

DIM.

MIN.TYP MAX.MIN.TYP.MAX.

A33012.992

C12.813.20.5040.519

D20.20.795

N60 2.362

T22.40.882

Ao 6.7 6.90.2640.272

Bo 5.3 5.50.2090.217

Ko 1.6 1.80.0630.071

Po 3.9 4.10.1530.161

P7.98.10.3110.319

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74LVX74

Table 10: Revision History

Date Revision Description of Changes 27-Aug-20043Ordering Codes Revision - pag. 1.

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74LVX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners

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