MC74AC14DR2中文资料

MC74AC14, MC74ACT14Hex Inverter Schmitt Trigger

The MC74AC14/74ACT14 contains six logic inverters which accept standard CMOS Input signals (TTL levels for MC74ACT14)and provide standard CMOS output levels. They are capable of transforming slowly changing input signals into sharply defined,jitter–free output signals. In addition, they have a greater noise margin then conventional inverters.

The MC74AC14/74ACT14 has hysteresis between the positive–going and negative–going input thresholds (typically 1.0 V)which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations.

?Schmitt Trigger Inputs

?Outputs Source/Sink 24 mA

?′ACT14 Has TTL Compatible Inputs

GND

V

Figure 1. Pinout; 14–Lead Packages Conductors

(Top View)FUNCTION TABLE

14

14

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Device Package Shipping ORDERING INFORMATION

MC74AC14DT TSSOP–14

96 Units/Rail

MC74AC14DTR2TSSOP–142500 T ape & Reel MC74ACT14DT TSSOP–14

96 Units/Rail

MC74ACT14DTR2TSSOP–142500 T ape & Reel MC74AC14N

PDIP–1425 Units/Rail MC74AC14D SOIC–1455 Units/Rail MC74ACT14N PDIP–1425 Units/Rail MC74AC14DR2SOIC–142500 T ape & Reel MC74ACT14D SOIC–1455 Units/Rail MC74ACT14DR2SOIC–142500 T ape & Reel MC74AC14M EIAJ–1450 Units/Rail MC74AC14MEL EIAJ–142000 T ape & Reel MC74ACT14M EIAJ–1450 Units/Rail MC74ACT14MEL

EIAJ–14

2000 T ape & Reel

See general marking information in the device marking section on page 5 of this data sheet.

DEVICE MARKING INFORMATION

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-mended Operating Conditions.

1.V in from 30% to 70% V CC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.V in from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

*All outputs loaded; thresholds on input associated with output under test.

?Maximum test duration 2.0 ms, one output loaded at a time.

NOTE:I IN and I CC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V CC.

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

Voltage Range 5.0 V is 5.0 V ±0.5 V.

*All outputs loaded; thresholds on input associated with output under test.?Maximum test duration 2.0 ms, one output loaded at a time.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MARKING DIAGRAMS

A = Assembly Location WL, L = Wafer Lot YY , Y = Year

WW, W

= Work Week

PDIP–14SO–14TSSOP–14MC74AC14N AWLYYWW

AC14AWLYWW

AC 14ALYW

ACT 14ALYW

ACT14AWLYWW

MC74ACT14N AWLYYWW 74AC14ALYW

EIAJ–1474ACT14ALYW

PACKAGE DIMENSIONS

PDIP–14N SUFFIX

14 PIN PLASTIC DIP PACKAGE

CASE 646–06ISSUE M

SO–14D SUFFIX

14 PIN PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 8.558.750.3370.344B 3.80 4.000.1500.157C 1.35 1.750.0540.068D 0.350.490.0140.019F 0.40 1.250.0160.049G 1.27 BSC 0.050 BSC J 0.190.250.0080.009K 0.100.250.0040.009M 0 7 0 7 P 5.80 6.200.2280.244R

0.250.500.0100.019

____

PACKAGE DIMENSIONS

TSSOP–14DT SUFFIX

14 PIN PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 4.90 5.100.1930.200B 4.30 4.500.1690.177C --- 1.20

---0.047

D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.500.600.0200.024J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSC M

0 8 0 8 NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CON DITION.

6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.

__

__

14X REF K

EIAJ–14M SUFFIX

14 PIN PLASTIC EIAJ PACKAGE

CASE 965–01ISSUE O

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

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