LV-buffer
Low-V oltage
Class
)must be as small as
possible to reduce the standby power consumption,while the current in the
class
).The principle and implementation of the proposed buffer
Manuscript received July 2,1996;revised October 27,1997.
The authors are with the Department of Electrical Engineering,Texas A&M University,College Station,TX 77843-3128USA.Publisher Item Identi?er S 0018-9200(98)03578-1.
will be described in Section II.Experimental results will be presented in Section III.
II.C
LASS
mode of operation (the gate-to-source voltage swing
of
and
mode,when the input voltage increases,the resistance
connected to
node
to be large enough to provide the maximum drive for
the output pMOS transistor
(
increases,which
enhances the voltage swing at that node.
The proposed output buffer,shown in Fig.1(b),
uses
(
mode of operation,the gate
of
–
A in the example of
Fig.2.Under these conditions,the quiescent output current
in
)is not too sensitive to process variations.
Outside the
1–3
make up a current
mirror
with
and
and
0018–9200/98$10.00?1998IEEE
(a)(b)
Fig.1.(a)Output buffer using diode-connected transistors to control quiescent current and (b)output buffer with adaptive
load.
Fig.2.Simulated I –V characteristics of the adaptive loads in Fig.1(b)(X axis is V in ).
is the saturation drain–source voltage for all four
transistors
and
and
,the current for the loads
is
[see Fig.1(b)],
where will be discussed later.
The
biasing current needed for the
adaptive loads is provided by making the sizes
of
.
The effect of transistor mismatch on the quiescent current of the proposed buffer was analyzed using HSPICE simulations.An op amp con?gured as a unity-gain follower was used for the simulations.The op amp was constructed by adding an ideal op-amp input stage,with 100dB gain,in front of the pro-posed output buffer.A 5mV mismatch between the threshold voltages
of
)of the unity-gain follower was
Fig.3.Simulated variation of the quiescent current with and without 5mV V T mismatch.
swept
from
V for both cases indicates that the change
of the quiescent current due to
the
and
mode,and with very little area overhead.Its simplicity dis-tinguishes it from other proposed
class
,which is close to 1.2V (assuming
a
supply voltage.
The
parameter
and the distortion of the
buffer.
If
to be more
sensitive to process variations.
Increasing
drops
as
increases.
On the other hand,the sensitivity of the quiescent current,
assuming
a
increases.It is evident that there is a trade off between the sensitivity of the quiescent current and the distortion.A reasonable range
for
,,
and
are used to stabilize the ampli?er,as in the nested Miller compensation topologies [12].
III.E XPERIMENTAL R ESULTS
The realization of the
class
m
n-well digital CMOS process.Fig.6shows the measured
class
Fig.4.Simulated quiescent current,voltage gain at node A,and the THD as a function of .
(
and A/V
A.The ratio between the
maximum(class
respectively.For these four samples,the mean value of the
quiescent current is272
19%.For a process with tighter control,the deviation of
the quiescent current would be smaller.It is important to note
that the measured changes of the quiescent current have an
insigni?cant impact on the op-amp performance such as the
gain–bandwidth or phase margin,etc.
The op amp(of Fig.5)was con?gured as a unity-gain
follower,and was loaded with a200to
.
Fig.8.Magnitude spectrum at the output node of a unity-gain follower with 1kHz sine wave
input.
Fig.9.Measured 0.8V/100kHz step response of three-stage op amp with proposed buffer.
This is not due to any limitations imposed by the output buffer,but rather is due to the limited common-mode range (CMR)of the differential input stage.The input differential stage turns off when the input voltage falls below the lower bound of the CMR.The lower bound of the CMR is determined by the threshold voltage of the input transistors of the differential pair.In the process used for
fabrication,
approaches the lower rail (see Fig.7).Better tracking can be achieved by reducing the lower bound of the CMR,which can be,in turn,achieved by using
low
,we used a 2V supply voltage to achieve
a 1V swing.
IV.C ONCLUSION
A circuit technique to control the quiescent current of low-voltage
class