AK4122中文资料

ASAHI KASEI
[AK4122]
AK4122
24-Bit 96kHz SRC with DIR
GENERAL DESCRIPTION The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By using the AK4122, the system can take very simple configuration because the AK4122 has an internal PLL and does not need any master clock at slave mode. Then the AK4122 is suitable for the application interfacing to different sample rates like Car Audio, DVD recorder, etc.
FEATURES 1. SRC ? Asynchronous Sample Rate Converter ? Input Sample Rate Range (fsi) : 8kHz ～ 96kHz ? Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz ? Input to Output Sample Rate Ratio : 0.33 to 6 ? THD+N : ?113dB ? I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible ? Clock for Master mode : 256/384/512/768fs ? SRC Bypass mode ? Soft Mute Function 2. DIR ? 4-Channel Inputs Selector & 1-Channel Through Output ? AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible ? Low Jitter Analog PLL ? PLL Lock Range : 32kHz ～ 96kHz ? Auto detection - Non-PCM Bit Stream - DTS-CD Bit Stream - Validity Flag - Sampling Frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) - Unlock & Parity Error - DAT Start ID ? 40-bit Channel Status Buffer ? Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams ? Q-subcode Buffer for CD bit streams 3. 4-wire Serial μP Interface 4. Power Supply ? AVDD: 3.0 ～ 3.6V (typ. 3.3V) ? DVDD: 3.0 ～ 3.6V (typ. 3.3V) 5. Ta = ?10 ～ 70°C 6. Package : 48pin LQFP
MS0267-E-03 -1-
2004/08

ASAHI KASEI
[AK4122]
Block Diagram
INT0 INT1 INT2 RX1 RX2 RX3 RX4
RX1 RX2 RX3 RX4 OPS1-0
R
FILT
TX
TX PDN
IPS1-0
DIR PORT3 De-em Filter
OSEL
SMUTE Serial Audio I/F
LRCK BICK SDTO
PORT1 BICK1 LRCK1 SDTI
BICK1 LRCK1 SDTI
Serial Audio I/F PORT2
SRC
BYPS
ISEL1-0
LRCK BICK SDTO OMCLK
PLL
BICK2 LRCK2 SDTIO MCLK2
BICK2 LRCK2 SDTIO
Serial Audio I/F Control Register
M/S2 M/S3
AVDD AVSS
DVDD DVSS
CDTO CDTI CCLK CSN
Block diagram
MS0267-E-03 -2-
2004/08

ASAHI KASEI
[AK4122]
Ordering Guide
AK4122VQ AKD4122 ?10 ～ +70°C 48pin LQFP (0.5mm pitch) Evaluation Board for AK4122
Pin Layout
OMCLK
DVDD
SDTO
DVSS
CCLK
LRCK
BVSS
BICK
INT1
48 47 46 45 44 43 42 41 40 39 38 37 CDTI CDTO TST1 INT2 TST2 TST3 M/S2 M/S3 SMUTE TST4 TST5 FILT 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 SDTIO BICK2 LRCK2 MCLK2 DVDD DVSS SDTI BICK1 LRCK1 PDN AVSS R
AK4122VQ
Top View
INT0 31 30 29 28 27 26 TST11
CSN
12 25 13 14 15 16 17 18 19 20 21 22 23 24 TST10 AVDD
AVSS
TST6
TST7
TST8
TST9
RX1
RX2
RX3
MS0267-E-03 -3-
RX4
TX
2004/08

ASAHI KASEI
[AK4122]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 Pin Name CDTI CDTO TST1 INT2 TST2 TST3 M/S2 M/S3 SMUTE TST4 TST5 I/O I O O O O I I I I I I Function Control Data Input Pin Control Data Output Pin Test 1 Pin Interrupt 2 Pin Test 2 Pin Test 3 Pin This pin should be connected to DVSS. Master / Slave Mode Pin for PORT2 “H” : Master mode, “L” : Slave Mode Master / Slave Mode Pin for PORT3 “H” : Master mode, “L” : Slave Mode Soft Mute Pin “H” : Soft Mute, “L” : Normal Operation Test 4 Pin This pin should be connected to AVSS. Test 5 Pin This pin should be connected to AVSS. PLL Loop Filter Pin 470?±5% resistor and 2.2μF±50% ceramic capacitor in parallel with a 2.2nF±50% ceramic capacitor should be connected to AVSS externally. Analog Ground Pin Analog Power Supply Pin, 3.0 ～ 3.6V Test 6 Pin This pin should be connected to AVSS. Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 7 Pin This pin should be connected to AVSS. Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 8 Pin This pin should be connected to AVSS. Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 9 Pin This pin should be connected to AVSS. Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 10 Pin This pin should be connected to AVSS. Test 11 Pin
12 13 14 15 16 17 18 19 20 21 22 23 24
FILT AVSS AVDD TST6 RX1 TST7 RX2 TST8 RX3 TST9 RX4 TST10 TST11
O I I I I I I I I I O
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-03 -4-
2004/08

ASAHI KASEI
[AK4122]
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
R AVSS PDN LRCK1 BICK1 SDTI DVSS DVDD MCLK2 LRCK2 BICK2 SDTIO INT0 INT1 TX SDTO BICK LRCK OMCLK DVSS DVDD BVSS CSN CCLK
I I I I I I/O I/O I/O O O O O I/O I/O I I I
External Resistor Pin 12k?±5% resistor should be connected to AVSS externally. Analog Ground Pin Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initializes the control register. Input Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Digital Ground Pin Digital Power Supply Pin, 3.0 ～ 3.6V Master Clock Input Pin Input / Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input / Output Pin Interrupt 0 Pin Interrupt 1 Pin Transmitter Output Pin Audio Serial Data Output Pin Audio Serial Data Clock Pin Output Channel Clock Pin Master Clock Input Pin Digital Ground Pin Digital Power Supply Pin, 3.0 ～ 3.6V Substrate Ground Pin This pin should be connected to AVSS. Chip Select Pin Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-03 -5-
2004/08

ASAHI KASEI
[AK4122]
Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below. Classification PORT1 Pin Name BICK1, LRCK1, SDTI MCLK2 BICK2, LRCK2 SDTIO M/S2 OMCLK PORT3 BICK, LRCK SDTO M/S3 RX1, RX2, RX3, RX4 INT0, INT1, INT2, TX CSN, CCLK, CDTI CDTO SMUTE TST1, TST2, TST11 TST3 TST4, TST5, TST6, TST7, TST8, TST9, TST10 Setting These pins should be connected to DVSS. This pin should be connected to DVSS. These pins should be connected to DVSS in slave mode or open in master mode. This pin should be connected to DVSS. This pin should be connected to DVDD or DVSS. This pin should be connected to DVSS. These pins should be connected to DVSS in slave mode or open in master mode. This pin should be open. This pin should be connected to DVDD or DVSS. These pins should be open. These pins should be open. These pins should be connected to DVSS. This pin should be open. This pin should be connected to DVSS. These pins should be open. This pin should be connected to DVSS. These pins should be connected to AVSS.
PORT2
DIR Control PORT Other TEST
MS0267-E-03 -6-
2004/08

ASAHI KASEI
[AK4122]
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |BVSS ? DVSS| (Note 2) Input Current, Any Pin Except Supplies Digital Input Voltage 1 (Except RX1-4 pins) Digital Input Voltage 2 (RX1-4 pins) Ambient Temperature (Power applied) Storage Temperature Symbol AVDD DVDD ?GND IIN VIND1 VIND2 Ta Tstg min ?0.3 ?0.3 ?0.3 ?0.3 ?10 ?65 max 4.6 4.6 0.3 ±10 DVDD+0.3 AVDD+0.3 70 150 Units V V V mA V V °C °C
Note 1. All voltages with respect to ground. Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, BVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 3.0 3.3 (Note 3) Digital DVDD 3.0 3.3
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical.
max 3.6 AVDD
Units V V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0267-E-03 -7-
2004/08

ASAHI KASEI
[AK4122]
SRC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution (Note 4) 24 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 32 96 kHz THD+N (Input = 1kHz, 0dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz ?113 dB FSO/FSI = 48kHz/44.1kHz ?113 dB FSO/FSI = 32kHz/48kHz ?114 dB FSO/FSI = 96kHz/32kHz ?111 dB Worst Case (FSO/FSI = 48kHz/8kHz) ?103 dB Dynamic Range (Input = 1kHz, ?60dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz 114 dB FSO/FSI = 48kHz/44.1kHz 115 dB FSO/FSI = 32kHz/48kHz 115 dB FSO/FSI = 96kHz/32kHz 116 dB Worst Case (FSO/FSI = 32kHz/44.1kHz) 112 dB Dynamic Range (Input = 1kHz, ?60dBFS, A-weighted, Note 5) FSO/FSI = 44.1kHz/48kHz 117 dB Ratio between Input and Output Sample Rate (Note 6) FSO/FSI 0.33 6 Note 4. Input data for SRC corresponds to 24bit data. When LSB 4bit data is input, the AK4122 calculates as “0” data because SRC is 20bit calculation. Therefore, SRC outputs “0” data. Note 5. Measured by ROHDE & SCHWARZ UPD04, Rejection Filter = wide, 8192point FFT. Note 6. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz. The “6” is the ratio of FSO/FSI when FSI is 8kHz and FSO is 48kHz.
S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ～ 3.6V) Parameter Symbol min typ Input Resistance Zin 10 Input Voltage VTH 200 Input Sample Frequency fs 32 -
max 96
Units k? mVpp kHz
MS0267-E-03 -8-
2004/08

ASAHI KASEI
[AK4122]
FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ～ 3.6V; DEM=OFF) Parameter Symbol min Digital Filter Passband ?0.001dB 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.905 ≤ FSO/FSI < 0.985 PB 0 0.714 ≤ FSO/FSI < 0.905 PB 0 0.656 ≤ FSO/FSI < 0.714 PB 0 0.536 ≤ FSO/FSI < 0.656 PB 0 0.492 ≤ FSO/FSI < 0.536 PB 0 0.452 ≤ FSO/FSI < 0.492 PB 0 0.333 ≤ FSO/FSI < 0.452 PB 0 Stopband 0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI 0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI 0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI 0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI 0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI 0.492 ≤ FSO/FSI < 0.536 SB 0.2732FSI 0.452 ≤ FSO/FSI < 0.492 SB 0.2510FSI 0.333 ≤ FSO/FSI < 0.452 SB 0.1822FSI Passband Ripple PR Stopband Attenuation SA 96 Group Delay (Note 7) GD -
typ
max 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2245FSI 0.2003FSI 0.1781FSI 0.1092FSI
Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs
±0.01 58.5 -
Note 7. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.
DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ～ 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=?400μA) VOH DVDD?0.4 Low-Level Output Voltage (Iout=400μA) VOL Input Leakage Current Iin Parameter Power Supply Current Normal operation (PDN pin = “H”) (Note 8) FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.6V Power down (PDN pin = “L”) (Note 9) AVDD+DVDD min
typ typ
max 30%DVDD 0.4 ±10 max
Units V V V V μA Units
15 29 10
45 100
mA mA mA μA
Note 8. Typ and max values are the value of AVDD+DVDD in each power supply voltage. Power supply current of each path@Slave Mode, AVDD=DVDD=3.3V, FSI=FSO=48kHz 1. PORT1 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 2. PORT2 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 3. DIR → SRC → PORT3: AVDD=6mA(typ), DVDD=9mA(typ) Note 9. All digital input pins are held DVSS.
MS0267-E-03 -9-
2004/08

ASAHI KASEI
[AK4122]
SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ～ 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 8.192 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK for Input data (LRCK1, LRCK2) Frequency fs 8 Duty Cycle Duty 48 LRCK for Output data (LRCK, LRCK2) Frequency (Note 10) fs 32 Duty Cycle Slave Mode Duty 48 Master Mode Duty
S/PDIF Clock Recover Frequency Audio Interface Timing Input for PORT1 BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “↑” (Note 11) BICK1 “↑” to LRCK1 Edge (Note 11) SDTI Hold Time from BICK1 “↑” SDTI Setup Time to BICK1 “↑” Input for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “↑” (Note 11) BICK2 “↑” to LRCK2 Edge (Note 11) SDTIO Hold Time from BICK2 “↑” SDTIO Setup Time to BICK2 “↑” Output for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “↑” (Note 11) BICK2 “↑” to LRCK2 Edge (Note 11) LRCK2 to SDTIO (MSB) (Except I2S mode) BICK2 “↓” to SDTIO fPLL 32
typ
max 36.864
Units MHz ns ns kHz % kHz % % kHz
50
96 52 96 52 96
50 50
tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD
1/64fs 65 65 30 30 30 30 1/64fs 65 65 30 30 30 30 1/64fs 65 65 30 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 10. Min value is 8kHz at BYPASS mode. Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge. BICK2 rising edge must not occur at the same time as LRCK2 edge.
MS0267-E-03 - 10 -
2004/08

ASAHI KASEI
[AK4122]
Parameter Output for PORT3 (Slave mode) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO Output for PORT2 (Master mode) BICK2 Frequency BICK2 Duty BICK2 “↓” to LRCK2 BICK2 “↓” to SDTIO Output for PORT3 (Master mode) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN “↑” to CDTO Hi-Z Reset Timing PDN Pulse Width (Note 12)
Symbol tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPD
min 1/64fs 65 65 30 30
typ
max
Units ns ns ns ns ns ns ns Hz % ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns
30 30 64fs 50 ?20 ?20 64fs 50 ?20 ?20 200 80 80 40 40 150 50 50 20 30 1000 20 30
45 70 150
(Note 13)
Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. In case of using INT2. When INT2 is not used, the max value is not limited. Note 13. The AK4122 can be reset by bringing the PDN pin = “L”.
MS0267-E-03 - 11 -
2004/08

ASAHI KASEI
[AK4122]
Timing Diagram
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL
Clock Timing
tCLKL
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Slave mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
MS0267-E-03 - 12 -
2004/08

ASAHI KASEI
[AK4122]
LRCK
50%DVDD
tMBLR
dBCK 50%DVDD
BICK
tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Master mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCDH VIH R/W VIL Hi-Z
CDTO
WRITE/READ Command Input Timing
MS0267-E-03 - 13 -
2004/08

ASAHI KASEI
[AK4122]
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL Hi-Z
CDTO
WRITE Data Input Timing
VIH CSN VIL
VIH CCLK VIL
VIH CDTI A1 A0 VIL tDCD CDTO Hi-Z D7 D6 50%DVDD
READ Data Output Timing 1
MS0267-E-03 - 14 -
2004/08

ASAHI KASEI
[AK4122]
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI VIL tCCZ Hi-Z
CDTO
D2
D1
D0
50%DVDD
READ Data Output Timing 2
tPD PDN VIL
Power Down & Reset Timing
MS0267-E-03 - 15 -
2004/08

ASAHI KASEI
[AK4122]
OPERATION OVERVIEW Internal Signal Path
The input source of the SRC can be switched between the outputs of the DIR, PORT1 or PORT2. The input source of the PORT2 and PORT3 can be switched between the outputs of the SRC or BYPASS. When PORT2 is used as input port, PORT2 cannot use as output port. The signal path should be controlled during PWN bit = “0”. The Switch Names (ISEL1-0 bits etc) in Figure 1 correspond to the register bits that control the switch function. Refer to Table 1.
DIR PORT3 De-em Filter
OSEL
PORT1 Serial Audio I/F PORT2 Serial Audio I/F SRC
BYPS
ISEL1-0
Serial Audio I/F
PLL
Figure 1. Connection Input Source & Output Source
Mode 0 1 2 3 4 5 6 7 8 9
Input PORT ISEL1-0 bit 00 : PORT1 01 : PORT2 10 : DIR 00 : PORT1 01 : PORT2 10 : DIR 00 : PORT1 10 : DIR 00 : PORT1 10 : DIR
SRC / Bypass BYPS bit 0 : SRC
Output PORT OSEL bit
Path PORT1 → SRC → PORT3 PORT2 → SRC → PORT3 DIR → SRC → PORT3 PORT1 → PORT3 PORT2 → PORT3 DIR → PORT3 PORT1 → SRC → PORT2 DIR → SRC → PORT2 PORT1 → PORT2 DIR → PORT2
0 : PORT3 (Note 1) 1 : Bypass 0 : SRC 1 : Bypass
1 : PORT2 (Note 2)
Table 1. Path Select Default is Mode 0. (Path : PORT1 → SRC → PORT3) After PDN pin = “L” → “H”, SDTIO pin of PORT2 is the input pin. The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is selected as an input port. Refer to Table 6 and 7 for Master/Slave mode setting.
MS0267-E-03 - 16 -
2004/08

ASAHI KASEI
[AK4122]
Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately by Table 2. M/S2 pin L Mode Slave Unused pin Pin I/O Setting MCLK2 I This pin should be connected to DVSS. BICK2 I This pin should be connected to DVSS. LRCK2 I This pin should be connected to DVSS. SDTIO I This pin should be connected to DVSS. MCLK2 I This pin should be connected to DVSS. BICK2 O This pin should be open. LRCK2 O This pin should be open. SDTIO I This pin should be connected to DVSS. Table 2. Pin Setting for PORT2
H
Master
Note 2. In this case, PORT3 is output port. If PORT3 is unused, the digital I/O pins should be processed appropriately by Table 3. M/S3 pin L Mode Slave Unused pin Pin I/O Setting OMCLK I This pin should be connected to DVSS. BICK I This pin should be connected to DVSS. LRCK I This pin should be connected to DVSS. SDTO O This pin should be open. OMCLK I This pin should be connected to DVSS. BICK O This pin should be open. LRCK O This pin should be open. SDTO O This pin should be open. Table 3. Pin Setting for PORT3
H
Master
System Clock
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and PORT3 are in slave mode and then please set MCLK2 pin and OMCLK pin to DVSS. However, when PORT2 and PORT3 are used in master mode, MCLK2 pin and OMCLK pin should be supplied to MCLK. The M/S2 pin and M/S3 pin select between master and slave mode. Table 4 and 5 show setting of MCLK frequency that PORT2 and PORT3 are master mode. In case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output port (PORT2 or PORT3) should be input. ICKS1 0 0 1 1 ICKS0 MCLK2 32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz 0 256fs 256fs 1 384fs 384fs 0 512fs N/A 1 768fs N/A Table 4. MCLK2 frequency select for Master mode
Default
OCKS1 0 0 1 1
OCKS0
OMCLK 32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz 0 256fs 256fs 1 384fs 384fs 0 512fs N/A 1 768fs N/A Table 5. OMCLK frequency select for Master mode
Default
MS0267-E-03 - 17 -
2004/08

ASAHI KASEI
[AK4122]
Master Mode and Slave Mode
When PORT2 and PORT3 are used as output port, the M/S2 pin and M/S3 pin select either master or slave mode. “H” is master mode, “L” is slave mode. In master mode, MCLK should be input and the AK4122 outputs BICK and LRCK. In slave mode, BICK and LRCK are input externally and MCLK is not needed. If PORT2 is used as input port, M/S2 pin should be set “H” or “L”. M/S2 pin L L H H Data I/O Mode BICK, LRCK I/O Slave, SRC Input Input Available 1 Output Not Available 0 I/O Master, SRC Output 1 I/O Master, Bypass Table 6. Master mode/Slave mode for PORT2 BYPS bit Data I/O Mode BICK, LRCK 0 Output Slave, SRC Input 1 Output Not Available 0 Output Master, SRC Output 1 Output Master, Bypass Table 7. Master mode/Slave mode for PORT3 BYPS bit 0
M/S3 pin L L H H
Audio Interface Format
The audio interface should be controlled during PWN bit = “0”. When in BYPASS mode, BICK1, BICK2 and BICK are fixed to 64fs. (1) PORT1 Four kinds of data formats can be chosen with the DIF1-0 bits (Table 8). In all modes, the serial data is in MSB first, 2’s compliment format. The SDTI is latched on the rising edge of BICK1. PORT1 corresponds to slave mode only. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 Input Format LRCK 0 16bit, LSB justified H/L 1 24bit, MSB justified H/L 0 24bit, I2S Compatible L/H 1 24bit, LSB justified H/L Table 8. Audio Interface Format for PORT1 BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs
Default
Note: The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is selected as an input port.
LRCK
0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTI(i) BICK(64fs) SDTI(i)
Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 15 14 13 0 1 2 3 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
SDTI-15:MSB, 0:LSB Lch Data Rch Data
Figure 2. Mode 0 Timing MS0267-E-03 - 18 2004/08

ASAHI KASEI
[AK4122]
LRCK
0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 3. Mode 1 Timing
LRCK
0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 4. Mode 2 Timing
LRCK
0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1
BICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 1 0 Don't Care 23 8 1 0
Figure 5. Mode 3 Timing (2) PORT2 Four kinds of data formats can be chosen with the IDIF1-0 bits (Table 9). In all modes, the serial data is in MSB first, 2’s compliment format. If PORT2 is selected the output port, the SDTIO is clocked out on the falling edge of BICK2, and if PORT2 is selected the input port, the SDTIO is latched on the rising edge of BICK2. The audio interface supports both master and slave modes. In master mode, BICK2 and LRCK2 are output with the BICK2 frequency fixed to 64fs and the LRCK2 frequency fixed to 1fs. Mode 0 1 2 3 IDIF1 0 0 1 1 IDIF0 0 1 0 1 Output Format Input Format 24bit, MSB justified 16bit, LSB justified 24bit, MSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, I2S Compatible 24bit, MSB justified 24bit, LSB justified Table 9. Audio Interface Format for PORT2 LRCK H/L H/L L/H H/L BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs
Default
MS0267-E-03 - 19 -
2004/08

ASAHI KASEI
[AK4122]
LRCK
0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTIO(o) SDTIO(i)
23 22 21 15 14 13 0 1 2 3 15 14 13 12 11 10 9 8 23 22 21 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 15 14 13 12 11 10 9 8 23 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 21 Don't Care 7 6 5 4 3 15 14 13 12 1 0 23 22 21 Don't Care 7 6 5 4 3 15 14 13 12 2 1 0 23
SDTIO-23:MSB, 0:LSB SDTIO-15:MSB, 0:LSB Lch Data Rch Data
Figure 6. Mode 0 Timing
LRCK
0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 23 22 4 3 2 1 0 4 3 2 1 0 23 22 Don't Care 23 22 4 3 2 1 0 4 3 2 1 0 23 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 7. Mode 1 Timing
LRCK
0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 23 22 4 3 2 1 0 4 3 2 1 0 23 22 Don't Care 23 22 4 3 2 1 0 4 3 2 1 0 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 8. Mode 2 Timing
LRCK
0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1
BICK(64fs) SDTIO(o) SDTIO(i)
23 22 16 15 23 0 8 1 0 23 22 16 15 23 0 8 1 0 23
Don't Care 23:MSB, 0:LSB
Don't Care
Lch Data
Rch Data
Figure 9. Mode 3 Timing
MS0267-E-03 - 20 -
2004/08