当前位置：文档库 › HY57V561620T-P中文资料

HY57V561620T-P中文资料

HY57V561620

4Banks x 4M x 16Bit Synchronous DRAM

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

DESCRIPTION

The Hyundai HY57V561620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory appli-cations which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.

HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

?Single 3.3V ± 0.3V power supply

?All device pins are compatible with LVTTL interface ?

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch

All inputs and outputs referenced to positive edge of system clock

?Data mask function by UDQM and LDQM ?

Internal four banks operation

?Auto refresh and self refresh ?8192 refresh cycles / 64ms

Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst

- 1, 2, 4 and 8 for Interleave Burst ?Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power Organization Interface Package

HY57V561620T-H 133MHz Normal

4Banks x 4Mbits

x16

LVTTL 400mil 54pin TSOP II

HY57V561620T-8125MHz HY57V561620T-P 100MHz HY57V561620T-S 100MHz HY57V561620T-10100MHz HY57V561620LT-H 133MHz Low Power

HY57V561620LT-8125MHz HY57V561620LT-P 100MHz HY57V561620LT-S 100MHz HY57V561620LT-10

100MHz

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQM

BA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity

A0 ~ A12Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10

RAS, CAS, WE Row Address Strobe, Col-

umn Address Strobe, Write

Enable

RAS, CAS and WE define the operation

Refer function truth table for details

UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15Data Input/Output Multiplexed data input / output pin

V DD/V SS Power Supply/Ground Power supply for internal circuits and input buffers

V DDQ/V SSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x16 I/O Synchronous DRAM

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=0 to 70°C )

Note :

1. All voltages are referenced to V SS = 0V

2. V IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration

3. V IL (max) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION (TA=0 to 70°C , V DD =3.3 ± 0.3V, V SS =0V)

Note :

1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature T A 0 ~ 70°C Storage Temperature

T STG -55 ~ 125°C Voltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power Dissipation

P D 1W Soldering Temperature ? Time

T SOLDER

260 ? 10

°C ? Sec

Parameter

Symbol Min Typ.Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6V 1Input High Voltage V IH 2.0 3.0V DDQ + 2.0

V 1,2Input Low Voltage

V IL

VSSQ-2.0

0.8

1,3

Parameter

Symbol Value Unit Note

AC Input High / Low Level Voltage

V IH / V IL 2.4/0.4V Input Timing Measurement Reference Level Voltage Vtrip 1.4V Input Rise / Fall Time

tR / tF 1ns Output Timing Measurement Reference Level

Voutref 1.4V Output Load Capacitance for Access Time Measurement

CAPACITANCE (TA=25°C , f=1MHz)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I (TA=0 to 70°C , V DD =3.3±0.3V)

Note :

1. V IN = 0 to 3.6V, All other pins are not under test = 0V

2. D OUT is disabled, V OUT =0 to

3.6V

Parameter

Symbol

-H

-8/P/S/10

Unit

Min

Max Min Max Input capacitance

CLK

C I1 2.5 3.5 2.5 4.0pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM

CI 2 2.5 3.8 2.5 5.0pF Data input / output capacitance

DQ0 ~ DQ15

C I/O

4.0

6.5

4.0

6.5

Parameter

Symbol

Min.Max Unit Note Input leakage current I LI -11uA 1Output leakage current I LO -11uA 2

Output high voltage V OH 2.4-V I OH = -4mA Output low voltage

V OL

-0.4

I OL =+4mA

DC CHARACTERISTICS II (TA=0°C to 70°C , V DD =3.3V ± 0.3V, V SS =0V)

Note :

1. I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY57V561620T-H/8/P/S/10

4. HY57V561620LT-H/8/P/S/10

Parameter

Symbol

Test Condition

Speed

Unit

Note

-H

-8-P -S -10Operating Current

IDD1Burst Length=1, One bank active

tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA 120

110

100100

100

Precharge Standby Current in power down mode

IDD2P CKE ≤ VIL(max), tCK = min.2

IDD2PS

CKE ≤ VIL(max), tCK = ∞

Precharge Standby Current in non power down mode

IDD2N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min

Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 20

IDD2NS CKE ≥ VIH(min), tCK = ∞Input signals are stable.10Active Standby Current in power down mode

IDD3P CKE ≤ VIL(max), tCK = min 3

IDD3PS

CKE ≤ VIL(max), tCK = ∞

Active Standby Current in non power down mode

IDD3N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min

Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 25

IDD3NS

CKE ≥ VIH(min), tCK = ∞Input signals are stable 15Burst Mode Operating Current

IDD4

tCK ≥ tCK(min),

tRAS ≥ tRAS(min), IO=0mA All banks active

CL=3150140120120120

CL=2

120120*********Auto Refresh Current

IDD5

tRRC ≥ tRRC(min), All banks active 260

260

250250

250

mA 2Self Refresh Current IDD6

CKE ≤ 0.2V

AC CHARACTERISTICS I

Note :

1. Assume tR / tF (input rise and fall time ) is 1ns.

2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v

Parameter

Symbol

-H

-8

-P

-S

-10

Unit

Note

Min

Max

Min Max

System clock cycle time

CAS Latency = 3tCK37.5

1000

CAS Latency = 2

tCK21212101212ns Clock high pulse width tCHW 2.5-3-3-3-3-ns 1Clock low pulse width tCLW 2.5-3-3

-3

-3-ns 1

Access time from clock

CAS Latency = 3tAC3- 5.4-666-8ns

CAS Latency = 2tAC2-6-666-8ns Data-out hold time tOH 2.7-3-3-3-3-ns Data-Input setup time tDS 1.5-2-2-2- 2.5-ns 1Data-Input hold time tDH 0.8-1-1-1- 1.5-ns 1Address setup time tAS 1.5-2-2-2- 2.5-ns 1Address hold time tAH 0.8-1-1-1- 1.5-ns 1CKE setup time tCKS 1.5-2-2-2- 2.5-ns 1CKE hold time tCKH 0.8-1-1-1- 1.5-ns 1Command setup time tCS 1.5-2-2-2- 2.5-ns 1Command hold time

tCH 0.8-1-1-1- 1.5-ns 1CLK to data output in low Z-time tOLZ 1-1-1-1-1-ns CLK to data output in high Z-time

CAS Latency = 3tOHZ3 2.7 5.436363638ns CAS Latency = 2tOHZ2

AC CHARACTERISTICS II

Note :

1. A new command can be given tRRC after self refresh exit.

Parameter

Symbol

-H

-8

-P

-S

-10

Unit

Note

Min

Max Min Max Min Max Min Max Min Max RAS cycle time

Operation

tRC

-68

-70

-80

-ns

Auto Refresh

tRRC 65-68-70-70-80-ns RAS to CAS delay tRCD 20-20-20-20-24-ns RAS active time tRAS 45100K 48100K 50100K 50100K 50100K ns RAS precharge time

tRP 20-20-20-20-30-ns RAS to RAS bank active delay tRRD 15-16-20-20-20-ns CAS to CAS delay

tCCD 1-1-1-1-1-CLK Write command to data-in delay tWTL 0-0-0-0-0-CLK Data-in to precharge command tDPL 2-2-2-2-2-CLK Data-in to active command tDAL 5-5-4-4-5-CLK DQM to data-out Hi-Z tDQZ 2-2-2-2-2-CLK DQM to data-in mask tDQM 0-0-0-0-0-CLK MRS to new command tMRD 2-2-2-2-2-CLK Precharge to data output Hi-Z

CAS Latency = 3tPROZ33-3-3-3-3-CLK CAS Latency = 2

tPROZ2----2-2-2-CLK Power down exit time tPDE 1-1-1-1-1-CLK Self refresh exit time tSRE 1-1-1-1-1-CLK 1

Refresh Time

tREF

-64

IBIS SPECIFICATION

** IBIS spec. is also applied to 133MHz device.

I OH Characteristics (Pull-up) 66MHz and 100MHz Pull-up

Voltage 100MHz Min 100MHz Max 66MHz Min

(V)I (mA)

I (mA)I (mA)

3.45-2.43.3-27.3

3.00.0-7

4.1-0.72.6-21.1-129.2-7.52.4-34.1-153.3-13.32.0-58.7-197.0-27.51.8-67.3-226.2-3

5.51.65-73.0-248.0-41.11.5-77.9-269.7-47.91.4-80.8-284.3-52.41.0-88.6-344.5-72.50.0

-93.0-502.4

-93.0

I OL Characteristics (Pull-down) 66MHz and 100MHz Pull-down

Voltage 100MHz Min 100MHz Max 66MHz Min (V)I (mA)I (mA)I (mA)0.00.00.00.0

0.427.570.217.70.6541.8107.526.90.8551.6133.833.31.058.0151.237.61.470.7187.746.61.572.9194.448.01.6575.4202.549.51.877.0208.650.71.9577.6212.051.53.080.3219.654.23.45

81.4

222.6

54.9

V DD Clamp @ CLK, CKE, CS, DQM & DQ

V DD (V)I(mA)

0.00.0

0.20.0

0.40.0

0.60.0

0.70.0

0.80.0

0.90.0

1.00.23

1.2 1.34

1.4 3.02

1.6 5.06

1.87.35

2.09.83

2.212.48

2.415.30

2.618.31

V SS Clamp @ CLK, CKE, CS, DQM & DQ V SS (V)I (mA)

-2.6-57.23

-2.4-45.77

-2.2-38.26

-2.0-31.22

-1.8-24.58

-1.6-18.37

-1.4-12.56

-1.2-7.57

-1.0-3.37

-0.9-1.75

-0.8-0.58

-0.7-0.05

-0.60.0

-0.40.0

-0.20.0

0.0

0.0 Minimum V DD clamp current (Referenced to V DD) Minimum V SS clamp current

DEVICE OPERATING OPTION TABLE

HY57V561620(L)T-H

HY57V561620(L)T-8

HY57V561620(L)T-P

HY57V561620(L)T-S

HY57V561620(L)T-10

CAS Latency

tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz(10ns)3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD tRAS tRC tRP tAC tOH 100MHz(10.0ns)3CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 83MHz(12.0ns)2CLKs 3CLKs 5CLKs 8CLKs 3CLKs 8ns 3ns 66MHz(15.0ns)

2CLKs

4CLKs

6CLKs

2CLKs

8ns

3ns

COMMAND TRUTH TABLE

Note :

1. OP Code : Operand Code

2. V = Valid, X = Don’t care, H = Logic High, L= Logic Low, RA = Row Address, CA = Column Address.

Command

CKEn-1CKEn CS RAS CAS WE DQM ADDR

A10/AP BA Note Mode Register Set H X L L L L X

OP code

No Operation H X

H H H Bank Active H

Read

V Read with Autoprecharge H Write

Write with Autoprecharge H Precharge All Banks

Precharge selected Bank L V

Burst Stop H X

H H

X X UDQM, LDQM H X V X Auto Refresh

H H L L L H X X

Self Refresh

Entry

L L L H X

Exit

L H H H Precharge power down

Entry

L H H H

Exit

L H H H Clock Suspend

Entry H L

Exit

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package