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DP83848K(T)

DP83848T PHYTER? Mini DP83848K PHYTER? Mini LS Industrial Temperature Single Port 10/100 Ethernet Transceiver

? 2006 National Semiconductor Corporation

https://www.wendangku.net/doc/1f14081914.html,

DP83848T PHYTER? Mini DP83848K PHYTER? Mini LS

Industrial Temperature Single Port 10/100 Ethernet Transceiver

October 2006

System Diagram

PHYTER ? is a registered trademark of National Semiconductor Corporation.

Status 10BASE-T

or 100BASE-TX

MII

Typical Ethernet Application

M a g n e t i c s

R J -45

Clock LED/s

PHYTER Mini/ PHYTER

Mini LS

10/100 Ethernet Transceiver

M e d i a A c c e s s C o n t r o l l e r o l e r

MPU/CPU Source

Features

?Low-power 3.3V, 0.18μm CMOS technology ? 3.3V MAC Interface

?Auto-MDIX for 10/100 Mb/s ?Energy Detection Mode

?MII Interface

?MII serial management interface (MDC and MDIO)?IEEE 802.3u Auto-Negotiation and Parallel Detection ?IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

?IEEE 802.3u PCS, 100BASE-TX transceivers and filters ?Integrated ANSI X3.263 compliant TP-PMD physical su-blayer with adaptive equalization and Baseline Wander compensation ?Error-free Operation beyond 137 meters

?ESD protection - Greater than 4KV Human body model ?LED support for Link in DP83848T

?LED support for Link and Speed in DP83848K

?Supports system clock from oscillator (Not available in

DP83848K)?Single register access for complete PHY status

?10/100 Mb/s packet BIST (Built in Self Test)

?40 pin LLP package (6mm) x (6mm) x (0.8mm)General Description

The DP83848T/K addresses the quality, reliability and small form factor required for space sensitive applications in embedded systems operating in the industrial tempera-ture range.

The DP83848T/K offers performance far exceeding the

IEEE specifications, with superior interoperability and industry leading performance beyond 137m of Cat-V cable. The DP83848T/K also offers Auto-MDIX to remove cabling complications. DP83848T/K has superior ESD pro-tection, greater than 4KV Human Body Model, providing

extremely high reliability and robust operation, ensuring a high level performance in all applications.DP83848K offers two flexible LED indicators - one for Link

and the other for Speed.

A 25MHz clock out that eliminates the need and hence the space and cost, of an additional Media Access Control (MAC) clock source component is available only in

DP83848T.

The DP83848T/K is offered in a tiny 6mm x 6mm LLP 40-pin package and is ideal for industrial controls, build-ing/factory automation, transportation and test equipment.

Applications ?Peripheral devices

?Mobile devices

?Factory and building automation ?Basestations

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D P 83848T /K

SERIAL MANAGEMENT

T X _C L K

T X D [3:0]

T X _E N

M D I O

M D C

C O L

C R S

R X _E R

R X _D V

R X D [3:0]

R X _C L K

Auto-Negotiation State Machine

Clock RX_DATA

RX_CLK

TX_DATA TX_CLK REFERENCE CLOCK

TD±RD±

LED/S

Generation

MII INTERFACE

Figure 1. DP83848T/K Functional Block Diagram

MII

Registers

Transmit Block

10BASE-T &100BASE-TX 10BASE-T &100BASE-TX Receive Block

Auto-MDIX

DAC

ADC

LED Driver

MII

DP83848T/K

Table of Contents

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.1 SERIAL MANAGEMENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 MAC DATA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3 CLOCK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4 LED INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.5 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6 STRAP OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.7 10 MB/S AND 100 MB/S PMD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.8 SPECIAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.9 POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.10 PACKAGE PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.0 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 AUTO-NEGOTIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.5 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 AUTO-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 PHY ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 LED INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.1 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 HALF DUPLEX VS. FULL DUPLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6 INTERNAL LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.1 MII INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 802.3U MII SERIAL MANAGEMENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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D P 83848T /K

4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.1 TPI NETWORK CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.2 ESD PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.3 CLOCK IN (X1) REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.4 POWER FEEDBACK CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.5 POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.6 ENERGY DETECT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.0 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.1 HARDWARE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.2 SOFTWARE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

7.1 REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 427.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 437.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 447.2 EXTENDED REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.1 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.2.2 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.2.3 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 487.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507.2.7 10Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537.2.9 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.1 DC SPECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.2 AC SPECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.2.6 100BASE-TX Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.2.7 100BASE-TX Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628.2.9 100BASE-TX Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638.2.10 100BASE-TX Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648.2.13 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658.2.14 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658.2.15 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668.2.16 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668.2.17 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

DP83848T/K 8.2.18 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.19 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.21 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.22 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.23 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.2.24 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.25 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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D P 83848T /K

List of Figures

Figure 1. DP83848T/K Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . .26Figure 9. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Figure 11. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 12. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Figure 13. Power Feedback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

DP83848T/K

List of Tables

Table1. Auto-Negotiation Modes in DP83848K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table2. Auto-Negotiation Modes in DP83848T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table3. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table4. LED Mode Select for DP83848T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table5. LED Mode Select for DP83848K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table6. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table5. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table6. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table7. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table9. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table10. Basic Mode Control Register (BMCR), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table11. Basic Mode Status Register (BMSR), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table12. PHY Identifier Register #1 (PHYIDR1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table13. PHY Identifier Register #2 (PHYIDR2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table14. Negotiation Advertisement Register (ANAR), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 . . . . . . . .42

Table16. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 . . . . . . . . .43

Table17. Auto-Negotiate Expansion Register (ANER), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table18. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 . . . . . . . . . . . . . . . . . . .44

Table19. PHY Status Register (PHYSTS), address 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table20. False Carrier Sense Counter Register (FCSCR), address 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table21. Receiver Error Counter Register (RECR), address 0x15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table22. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 . . . . . . . . . . . . . . . . . . . .48

Table23. LED Direct Control Register (LEDCR), address 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table24. PHY Control Register (PHYCR), address 0x19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table25. 10Base-T Status/Control Register (10BTSCR), address 0x1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B . . . . . . . . . . . . . . . . . . . . . . . . .53

Table27. Energy Detect Control (EDCR), address 0x1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

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D P 83848T /K

Pin Layout for DP83848T

PFBIN2DGND X1X2IOVDD33MDC MDIO RESET_N LED_LINK/AN025MHz_OUT

RBIAS

PFBOUT

AVDD33

AGND

PFBIN1

TD +

TD -AGND

RD +

RD -

IOVDD33TX_CLK TX_EN TXD_0TXD_1TXD_2TXD_3RESERVED RESERVED RESERVED

RX_CLK RX_DV CRS/LED_CFG RX_ER/MDIX_EN COL/PHYAD0RXD_0/PHYAD1RXD_1/PHYAD2RXD_2/PHYAD3RXD_3/PHYAD4IOGND 12345678910

201918171615141312113029282726252423222131

40Top View

Order Number DP83848T NS Package Number NSQAU040

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DP83848T/K

Pin Layout for DP83848K

PFBIN2DGND X1X2IOVDD33MDC MDIO RESET_N LED_LINK/AN0LED_SPEED/AN1

RBIAS

PFBOUT

AVDD33

AGND

PFBIN1

TD +

TD -AGND

RD +

RD -

IOVDD33TX_CLK TX_EN TXD_0TXD_1TXD_2TXD_3RESERVED RESERVED RESERVED

RX_CLK RX_DV CRS/LED_CFG RX_ER/MDIX_EN COL/PHYAD0RXD_0/PHYAD1RXD_1/PHYAD2RXD_2/PHYAD3RXD_3/PHYAD4IOGND 12345678910

201918171615141312113029282726252423222131

40Top View

Order Number DP83848K NS Package Number NSQAU040

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D P 83848T /K

1.0 Pin Descriptions

The DP83848T/K pins are classified into the following interface categories (each interface is described in the sections that follow):—Serial Management Interface —MAC Data Interface —Clock Interface —LED Interface —Reset

—Strap Options

—10/100 Mb/s PMD Interface —Special Connect Pins —

Power and Ground pins

Note:Strapping pin option. Please see Section 1.6 for strap definitions.

All DP83848T/K signal pins are I/O cells regardless of the particular use. The definitions below define the functional-ity of the I/O cells for each pin.1.1 SERIAL MANAGEMENT INTERFACE

1.2 MAC DATA INTERFACE

Type: I Input Type: O Output

Type: I/O Input/Output

Type: PD,PU Internal Pulldown/Pullup

Type: S

Strapping Pin (All strap pins have weak in-ternal pull-ups or pull-downs. If the default strap value is needed to be changed then an external 2.2 k ? resistor should be used.Please see Section 1.6 for details.)

Signal Name

Type Pin #Description

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.

MDIO I/O 24

MANAGEMENT DATA I/O: Bi-directional management instruc-tion/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k ? pullup resistor.

Signal Name

Type Pin #Description

TX_CLK

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock.

TX_EN I, PD 3MII TRANSMIT ENABLE: Active high input indicates the pres-ence of valid data inputs on TXD[3:0].

TXD_0TXD_1TXD_2TXD_3I

I, PD 456

7MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

RX_CLK O 31MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.RX_DV O, PD 32MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].

RX_ER

S, O, PU

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a re-ceived packet in 100 Mb/s mode.

RXD_0RXD_1RXD_2RXD_3S, O, PD 36373839

MII RECEIVE DATA: Nibble wide receive data signals driven syn-chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

CRS/LED_CFG

S, O, PU 33

MII CARRIER SENSE: Asserted high to indicate the receive me-dium is non-idle.

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DP83848T/K

1.3 CLOCK INTERFACE

1.4 LED INTERFACE

See Table 4 for LED Mode Selection.

1.5 RESET

COL

S, O, PU

MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1μs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-nal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation.

Signal Name

Type

Pin #Description

X1 I

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848T/K and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83848T/K sup-ports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connect-ed to pin X1 only.

X2O 27

CRYSTAL OUTPUT: This pin is the primary clock reference out-put to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.25MHz_OUT O 21

25 MHz CLOCK OUTPUT:

This pin provides a 25 MHz clock output to the system. This allows other devices to use the reference clock from the DP83848T without requiring additional clock sources. Note: This pin is not available in DP83848K.

Signal Name

Type Pin #Description

Signal Name

Type Pin #Description

LED_LINK

S, O, PU

LINK LED: In Mode 1, this pin indicates the status of the LINK.The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.

LED_SPEED

S, O, PU

SPEED LED: This LED is ON when DP83848K is in 100Mb/s and OFF when DP83848K is in 10Mb/s. Functionality of this LED is in-dependent of the mode selected.

Note: This pin is not available in DP83848T.

Signal Name

Type Pin #Description

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the DP83848T/K. Asserting this pin low for at least 1 μs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block sec-tion. All strap options are re-initialized as well.

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D P 83848T /K

1.6 STRAP OPTIONS

DP83848T/K uses many functional pins as strap options.The values of these pins are sampled during reset and used to strap the device into specific modes of operation.The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 k ? resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate func-tions after reset is deasserted, they should not be con-nected directly to VCC or GND.

Signal Name

Type Pin #Description

PHYAD0 (COL)PHYAD1 (RXD_0)PHYAD2 (RXD_1)PHYAD3 (RXD_2)PHYAD4 (RXD_3)

S, O, PU S, O, PD

3536373839

PHY ADDRESS [4:0]: The DP83848T/K provides five PHY ad-dress pins, the state of which are latched into the PHYCTRL reg-ister at system Hardware-Reset.

The DP83848T/K supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). A PHY Address of 0 puts the part into the MII Isolate Mode . The MII isolate mode must be se-lected by strapping Phy Address 0; changing to Address 0 by reg-ister write will not put the Phy in the MII isolate mode. Please refer to section 2.3 for additional information.PHYAD0 pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

AN0 (LED_LINK)AN1 (LED_SPEED)

S, O, PU S, O, PU

2221

These input pins control the advertised operating mode of the de-vice according to the following table. The value on these pins are set by connecting them to GND (0) or V CC (1) through 2.2 k ? re-sistors. These pins should NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83848T at Hard-ware-Reset.

The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default for DP83848K is 11 since these pins have an internal pull-up.

Note: AN1 (LED_SPEED) pin is not available in DP83848T The default is 1 in DP83848T since the AN0 pin has an internal pull-up.

AN1AN0Advertised Mode 0010BASE-T, Half/Full-Duplex 01100BASE-TX, Half/Full-Duplex 1010BASE-T, Half-Duplex 100BASE-TX, Half-Duplex 1

10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex

AN0Advertised Mode 010BASE-T Half-Duplex 100BASE-TX, Half-Duplex 1

10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex

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DP83848T/K

1.7 10 MB/S AND 100 MB/S PMD INTERFACE

1.8 SPECIAL CONNECTIONS

1.9 POWER SUPPLY PINS

LED_CFG (CRS)

S, O, PU

LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are con-figurable via register access.SeeTable 4 for LED Mode Selection.

MDIX_EN (RX_ER)S, O, PU 34

MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable Auto-MDIX mode.

Signal Name

Type Pin #Description

TD-, TD+

I/O

14, 15

Differential common driver transmit output (PMD Output Pair).These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Re-ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+

I/O

11, 12

Differential receive input (PMD Input Pair). These differential in-puts are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.

These pins require 3.3V bias for operation.

Signal Name

Type Pin #Description

RBIAS I 20Bias Resistor Connection. A 4.87 k ? 1% resistor should be con-nected from RBIAS to GND.

PFBOUT

Power Feedback Output. Parallel caps, 10μ F (Tantalum pre-ferred) and 0.1μF, should be placed close to the PFBOUT. Con-nect this pin to PFBIN1 (pin 16) and PFBIN2 (pin 30). See Section 5.4 for proper placement pin.

PFBIN1PFBIN2

I 1630

Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1μF should be connected close to each pin.

Note: Do not supply power to these pins other than from PFBOUT.

RESERVED

I/O

8,9,10

RESERVED: These pins must be left unconnected.

Signal Name

Pin #Description

IOVDD331, 26I/O 3.3V Supply IOGND 40I/O Ground DGND 29Digital Ground AVDD3318Analog 3.3V Supply AGND

13, 17

Analog Ground

Signal Name

Type Pin #Description

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D P 83848T /K

1.10 PACKAGE PIN ASSIGNMENTS

NSQAU040Pin #Pin Name (DP83848T)

1IO_VDD 2TX_CLK 3TX_EN 4TXD_05TXD_16TXD_27TXD_38RESERVED 9RESERVED 10RESERVED 11RD-12RD+13AGND 14TD -15TD +16PFBIN117AGND 18AVDD3319PFBOUT 20RBIAS 2125MHz_OUT 22LED_LINK/AN023RESET_N 24MDIO 25MDC 26IOVDD3327X228X129DGND 30PFBIN231RX_CLK 32RX_DV 33CRS/LED_CFG 34RX_ER/MDIX_EN 35COL/PHYAD036RXD_0/PHYAD137RXD_1/PHYAD238RXD_2/PHYAD339RXD_3/PHYAD440

IOGND

NSQAU040Pin #Pin Name (DP83848K)1IO_VDD 2TX_CLK 3TX_EN 4TXD_05TXD_16TXD_27TXD_38RESERVED 9RESERVED 10RESERVED 11RD-12RD+13AGND 14TD -15TD +16PFBIN117AGND 18AVDD3319PFBOUT 20RBIAS

21LED_SPEED/AN122LED_LINK/AN023RESET_N 24MDIO 25MDC 26IOVDD3327X228X129DGND 30PFBIN231RX_CLK 32RX_DV 33CRS/LED_CFG 34RX_ER/MDIX_EN 35COL/PHYAD036RXD_0/PHYAD137RXD_1/PHYAD238RXD_2/PHYAD339RXD_3/PHYAD440

IOGND

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DP83848T/K

2.0 Configuration

This section includes information on the various configura-tion options available with the DP83848T/K. The configura-tion options described below include:—Auto-Negotiation

—PHY Address and LED —Half Duplex vs. Full Duplex —Isolate mode —Loopback mode —

BIST

2.1 AUTO-NEGOTIATION

The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of

a link segment and automatically selecting the highest per-formance mode of operation supported by both devices.Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83848T/K supports four differ-ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high-est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83848T can be controlled either by

internal register access or by the use of the AN0 pin.

Note: In DP83848K, the Auto-Negotiation function can be

controlled either by internal register access or by the use of AN0 and AN1 pins.

2.1.1 Auto-Negotiation Pin Control

The state of AN0 and AN1 pins determine the specific mode advertised by the device as given in Table 2.. The state of AN0 and AN1 pins, upon power-up/reset, deter-mines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or reset can be changed at any time by writing to the Basic Mode Control Register (BMCR) at address 0x00h.

Note: DP83848T does not offer the AN1 pin. Table 2 shows

the Auto-Negotiation mode in DP83848T.

Table 1. Auto-Negotiation Modes in DP83848K AN1

AN0Advertised Mode

10BASE-T, Half/Full-Duplex

01100BASE-TX, Half/Full-Duplex 1010BASE-T, Half-Duplex 100BASE-TX, Half-Duplex

1110BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex Table 2. Auto-Negotiation Modes in DP83848T AN0Advertised Mode 010BASE-T Half-Duplex 100BASE-TX, Half-Duplex 110BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

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D P 83848T /K

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848T/K transmits the abilities programmed into the Auto-Negotia-tion Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected. Auto-Negotiation Priority Resolution:

—(1) 100BASE-TX Full Duplex (Highest Priority)—(2) 100BASE-TX Half Duplex —(3) 10BASE-T Full Duplex

—(4) 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is dis-abled, the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved.

The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotia-tion ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848T/K (only the 100BASE-T4 bit is not set since the DP83848T/K does not support that function). The BMSR also provides status on:

—Completion of Auto-Negotiation

—Occurrence of a remote fault as advertised by the Link Partner

—Establishment of a valid link

—Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR)indicates the Auto-Negotiation abilities to be advertised by the DP83848T/K. All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the tech-nology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi-cates additional Auto-Negotiation status. The ANER pro-vides status on:—Occurrence of a Parallel Detect Fault

—Next Page function support by the Link Partner —Next page support function by DP83848T/K

—

Reception of the current page that is exchanged by Auto-Negotiation

—Auto-Negotiation support by the Link Partner

2.1.3 Auto-Negotiation Parallel Detection

The DP83848T/K supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel Detection requires both the 10 Mb/s and 100 Mb/s receiv-ers to monitor the receive signal and report link status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the Link Partner does not support Auto-Negoti-ation but is transmitting link signals that the 100BASE-TX or 10BASE-T PMAs recognize as valid link signals.If the DP83848T/K completes Auto-Negotiation as a result of Parallel Detection, bit 5 or bit 7 within the ANLPAR reg-ister will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detec-tion by reading a zero in the Link Partner Auto-Negotiation Able bit once the Auto-Negotiation Complete bit is set. If configured for parallel detect mode and any condition other than a single good link occurs then the parallel detect fault bit will be set.

2.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart Auto-Negotiation) of the BMCR to one. If the mode configured by a successful Auto-Negotiation loses a valid link, then the Auto-Negotia-tion process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes discon-nected.

A renegotiation request from any entity, such as a man-agement agent, will cause the DP83848T/K to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotia-tion resumes. The DP83848T/K will resume Auto-Negotia-tion after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.

2.1.5 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approxi-mately 2-3 seconds to complete. In addition, Auto-Negoti-ation with next page should take approximately 2-3seconds to complete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negoti-ation.

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DP83848T/K

2.2 AUTO-MDIX

When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The function uses a ran-dom seed to control switching of the crossover circuitry.

This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications.

Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (0x19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit,bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera-tion. 2.3 PHY ADDRESS

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown below.

The DP83848T/K can be set to respond to any of 32 possi-ble PHY addresses via strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848T/K or port sharing an MDIO bus in a system must have a unique physical address.

The DP83848T/K supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). Strapping PHY

Address 0 puts the part into Isolate Mode . It should also be noted that selecting PHY Address 0 via an MDIO write to PHYCR will not put the device in Isolate Mode. See Section 2.3.1 for more information.For further detail relating to the latch-in timing requirements

of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in

Section 6.0. Since the PHYAD[0] pin has weak internal pull-up resistor

and PHYAD[4:1] pins have weak internal pull-down resis-tors, the default setting for the PHY address is 00001(01h).Refer to Figure 2 for an example of a PHYAD connection to

external components. In this example, the PHYAD strap-ping results in address 00011 (03h).

2.3.1 MII Isolate Mode

The DP83848T/K can be put into MII Isolate mode by writ-ing to bit 10 of the BMCR register or by strapping in Physi-cal Address 0. It should be noted that selecting Physical Address 0 via an MDIO write to PHYCR will not put the device in the MII isolate mode.

When in the MII isolate mode, the DP83848T/K does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK,RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83848T/K will continue to respond to all management transactions.

While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83848T/K can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848T/K is in Isolate mode.

Table 3. PHY Address Mapping

Pin #PHYAD Function

RXD Function

35PHYAD0COL 36PHYAD1RXD_037PHYAD2RXD_138PHYAD3RXD_239

PHYAD4

RXD_3

Figure 2. PHYAD Strapping Example

C O L

R X D _0

R X D _1

R X D _2

R X D _3

VCC

2.2k ?

PHYAD0 = 1

PHYAD1 = 1PHYAD2 = 0PHYAD3 = 0PHYAD4= 0

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D P 83848T /K

2.4 LED INTERFACE

The DP83848T supports a configurable Light Emitting Diode (LED) pin for configuring the link. The PHY Control Register (PHYCR) for the LED can also be selected through address 19h, bit [5].

See Table 4. for LED Mode selection of DP83848T.

The DP83848K supports configurable Light Emitting Diode (LED) pins for configuring the link and speed. The PHY Control Register (PHYCR) for the LED can also be selected through address 19h, bit [5].

See Table 5. for LED Mode selection of DP83848K.

The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with the TP-PMD specifications which will result in internal generation of signal detect. A 10 Mb/s Link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as speci-fied in the IEEE 802.3 specification.

The LED_LINK pin in Mode 1 will be OFF when no LINK is present.

The LED_LINK pin in Mode 2 will be ON to indicate Link is good and BLINK to indicate activity is present on either transmit or receive activity.

The LED_SPEED pin in DP83848K indicates 10 or 100Mb/s data rate of the port. The standard CMOS driver goes high when operating in 100Mb/s operation. The functionality of this LED is independent of the mode selected.

Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down.

2.4.1 LED

Since the Auto-Negotiation strap options share the LED output pins, the external components required for strap-ping and LED usage must be considered in order to avoid contention.

Specifically, when the LED output is used to drive the LED directly, the active state of the output driver is dependent on the logic level sampled by the AN input upon power-up/reset. For example, if the AN input is resistively pulled low then the corresponding output will be configured as an active high driver. Conversely, if the AN input is resistively pulled high, then the corresponding output will be config-ured as an active low driver.

Refer to Figure 3 for an example of AN connection to ex-ternal components. In this example, the AN strapping re-sults in Auto-Negotiation with 10BASE-T Half-Duplex , 100BASE-TX Half-Duplex advertised.

The adaptive nature of the LED output helps to simplify potential implementation issues of this dual purpose pin..

Note: DP83848T does not have LED_SPEED (AN1) pin.

2.4.2 LED Direct Control

The DP83848T/K provides another option to directly con-trol the LED outputs through the LED Direct Control Reg-ister (LEDCR), address 18h. The register does not provide read access to the LED.

Table 4. LED Mode Select for DP83848T Mode LED_CFG[0] (bit 5)

or (pin40)

LED_LINK

11ON for Good Link OFF for No Link 2

ON for Good Link BLINK for Activity

Table 5. LED Mode Select for DP83848K

Mode LED_CFG[0]

(bit 5) or (pin40)LED_LINK

LED_SPEED

11ON for Good Link OFF for No Link ON in 100Mb/s OFF in 10Mb/s 2

ON for Good Link BLINK for Activity

ON in 100Mb/s

OFF in 10Mb/s

L E D _L I N K

VCC

275?

AN0 = 02.2k ?

L E D _S P E E D

AN1 = 1

275?

Figure 3. AN Strapping and LED Loading Example

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DP83848T/K

2.5 HALF DUPLEX VS. FULL DUPLEX The DP83848T/K supports both half and full duplex opera-tion at both 10 Mb/s and 100 Mb/s speeds.Half-duplex relies on the CSMA/CD protocol to handle colli-sions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.

Since the DP83848T/K is designed to support simulta-neous transmit and receive activity, it is capable of support-ing full-duplex switched applications with a throughput of up to 200 Mb/s per port when operating in 100BASE-TX mode. Because the CSMA/CD protocol does not apply to full-duplex operation, the DP83848T/K disables its own

internal collision sensing and reporting functions and modi-fies the behavior of Carrier Sense (CRS) such that it indi-cates only receive activity. This allows a full-duplex capable MAC to operate properly.All modes of operation (100BASE-TX and 10BASE-T) can run either half-duplex or full-duplex. Additionally, other than CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode.It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state machine in the partner would be unable to detect the full duplex capa-bility of the far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10 Mb/s). 2.6 INTERNAL LOOPBACK

The DP83848T/K includes a Loopback Test mode for facili-tating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Reg-ister (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status

may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be

transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback mode .2.7 BIST

The DP83848T/K incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnos-tics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continu-ous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to the generated pseudo-ran-dom data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous

Mode can be used to allow continuous data transmission,setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh). The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].

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D P 83848T /K

3.0 Functional Description

The DP83848T/K supports MII mode of operation using the MII interface pins. In the MII mode, the IEEE 802.3serial management interface is operational for device con-figuration and status. The serial management interface of the MII allows for the configuration and control of multiple PHY devices, gathering of status, error information, and the determination of the type and capabilities of the attached PHY(s).

3.1 MII INTERFACE

The DP83848T/K incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems. This sec-tion describes the nibble wide MII data interface.

The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals to facili-tate data transfer between the PHY and the upper layer (MAC).

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface includes a dedicated receive bus and a dedicated transmit bus.These two data buses, along with various control and sta-tus signals, allow for the simultaneous exchange of data between the DP83848T/K and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for syn-chronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s operational modes. The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a colli-sion which can occur during half-duplex operation when both a transmit and receive operation occur simulta-neously.

3.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.

If the DP83848T/K is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state.This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision.If a collision occurs during a receive operation, it is imme-diately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1μs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indi-cate successful transmission. SQE is reported as a pulse on the COL signal of the MII.

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,once valid data is detected via the squelch function during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

3.2 802.3U MII SERIAL MANAGEMENT INTER-FACE

3.2.1 Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and MDIO. The DP83848T/K implements all the required MII registers as well as several optional registers. These registers are fully described in Section 7.0. A description of the serial management access protocol follows.

3.2.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage-ment Data Clock (MDC) and Management Data Input/Out-put (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame for-mat is shown below in Table 6..

The MDIO pin requires a pull-up resistor (1.5 k ?) which,during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83848T/K with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 con-secutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition,32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected.The DP83848T/K waits until it has received this preamble sequence before responding to any other transaction.Once the DP83848T/K serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred.