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LMX2353TMNOPB;LMX2353TMXNOPB;LMX2353SLBX;中文规格书,Datasheet资料

LMX2353

LMX2353 PLLatinum Fractional N Single 2.5 GHz Low Power Frequency Synthesizer

Literature Number: SNAS047A

LMX2353

PLLatinum ?Fractional N Single 2.5GHz Low Power Frequency Synthesizer

General Description

The LMX2353is a monolithic integrated fractional N fre-quency synthesizer,designed to be used in a local oscillator subsystem for a radio transceiver.It is fabricated using Na-tional’s 0.5μABiC V silicon BiCMOS process.The LMX2353contains dual modulus prescalers along with modulo 15or 16fractional compensation circuitry in the N divider.A 16/17or 32/33prescale ratio can be selected for the https://www.wendangku.net/doc/1f14519105.html,ing a fractional N phase locked loop technique,the LMX2353can generate very stable low noise control signals for UHF and VHF voltage controlled oscillators (VCOs).The LMX2353has a highly flexible 16level programmable charge pump which supplies output current magnitudes from 100μA to 1.6mA.Two uncommitted CMOS outputs can be used to provide external control signals,or configured to FastLock ?mode.Serial data is transferred into the LMX2353via a three wire interface (Data,LE,Clock).Supply voltage can range from 2.7V to 5.5V.The LMX2353fea-tures very low current consumption;typically 5.5mA at 3.0V.The LMX2353is available in a 16-pin TSSOP or a 16-pin CSP surface mount plastic package.

Features

n 2.7V –5.5V operation n Low Current Consumption

I CC =5.5mA typ at V CC =3.0V

n Programmable or Logical Power Down Mode I CC =5μA typ at V CC =3.0V

n Modulo 15or 16fractional N divider

Supports ratios of 1,2,3,4,5,8,15,or 16n Programmable charge pump current levels 100μA to 1.6mA in 100μA steps n Digital Filtered Lock Detect

Applications

n Portable wireless communications (PCS/PCN,cordless)n Zero blind slot TDMA systems

n Cellular and Cordless telephone systems

n Spread spectrum communication systems (CDMA)n

Cable TV Tuners (CATV)

Functional Block Diagram

Fastlock ?,MICROWIRE ?and PLLatinum ?are trademarks of National Semiconductor Corporation.TRI-STATE ?is a registered trademark of National Semiconductor Corporation.

DS101124-1

?2001National Semiconductor Corporation https://www.wendangku.net/doc/1f14519105.html,

Pin Description

Pin No.Pin Name I/O Description

CSP TSSOP 161V P —Power supply for charge pump.Must be ≥V CC .

12CP O O Charge pump output.Connected to a loop filter for driving the control input external VCO.

23GND —Ground for PLL digital circuitry.

34f IN I RF prescaler input.Small signal input from the VCO.

45f INB I RF prescaler complimentary input.A bypass capacitor should be placed as as possible to this pin and be connected directly to the ground plane.56GND —Ground for PLL analog circuitry.

67OSC IN I Oscillator input.A CMOS inverting gate input.The input has a V CC /2input threshold and can be driven from an external CMOS or TTL logic gate.78F o LD O Multiplexed output of N or R divider and lock detect.CMOS output.

PLL Enable.Powers down N and R counters,prescalers,and TRI-STATE ?pump output when LOW.Bringing CE high powers up PLL depending on th of CTL_WORD.

910CLK I High impedance CMOS Clock input.Data for the various counters is clocke the 24-bit shift register on the rising edge.

1011DATA I Binary serial data input.Data entered MSB first.The last two bits are the co bits.High impedance CMOS input.

1112LE I Load enable high impedance CMOS input.Data stored in the shift registers loaded into one of the 4internal latches when LE goes HIGH.1213GND —Ground.

V CC

—

PLL power supply voltage input.May range from 2.7V to 5.5V.Bypass capa should be placed as close as possible to this pin and be connected directly ground plane.

1415OUT1—Programmable CMOS output.Level of the output is controlled by F2[18]bit.

OUT0

—

Programmable CMOS output.Level of the output is controlled by F2[17]bit.

DS101124-2

TOP VIEW

Order Number LMX2353TM or

LMX2353TMX

See NS Package Number MTC16

DS101124-3

TOP VIEW

Order Number LMX2353SLBX See NS Package Number SLB16A

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please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Power Supply Voltage

V CC?0.3V to6.5V Vp?0.3V to6.5V Voltage on any pin with

GND=0V(V I)?0.3V to V CC+0.3V Storage Temperature Range(T S)?65?C to+150?C Lead Temperature(solder,4sec.)(T L)+260?C Power Supply Voltage

V CC 2.7V to5.5V Vp V CC to5.5V Operating Temperature(T A)?40?C to+85?C Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional,but do not guarantee specific perfor-mance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.

Note2:This device is a high performance RF integrated circuit with an ESD rating<2kV and is ESD sensitive.Handling and assembly of this device should only be done at ESD free workstations.

Electrical Characteristics(V

=Vp=3.0V;?40?C

Symbol Parameter Conditions

Value

Unit Min Typ Max

GENERAL

I CC Power Supply Current 5.5 6.75mA I CC-PWDN Power Down Current CE=LOW520μA f IN RF Operating Frequency(Note3)0.5 2.5GHz f OSC Oscillator Frequency(Note3)250MHz fφPhase Detector Frequency10MHz Pf IN RF Input Sensitivity 2.7V≤V CC<3.0V?150dBm

3.0V≤V CC≤5.0V?100dBm V OSC Oscillator Sensitivity OSC IN0.5V CC V PP CHARGE PUMP

ICP o-source Charge Pump Output Current VCP o=Vp/2,

CP_WORD=0000

?100μA ICP o-sink VCP o=Vp/2,

CP_WORD=0000

100μA ICP o-source VCP o=Vp/2,

CP_WORD=1111

?1.6mA ICP o-sink VCP o=Vp/2,

CP_WORD=1111

1.6mA

ICP o-TRI Charge Pump TRI-STATE

Current 0.5≤VCP o≤Vp?0.5,

?40?C

-2.5 2.5nA

ICP o-sink vs ICP o-source CP Sink vs Source Mismatch VCP o=Vp/2,T A=25?C

310%

ICP o vs VCP o CP Current vs Voltage0.5≤VCP o≤Vp?0.5,T A=25?C

415%

ICP o vs T CP Current vs Temperature VCP o=Vp/2,?40?C

V IH High-Level Input Voltage(Note4)0.8V CC V

V IL Low-Level Input Voltage(Note4)0.2V CC V

I IH High-Level Input Current V IH=V CC=5.5V,(Note4)?1.0 1.0μA

I IL Low-Level Input Current V IL=0,V CC=5.5V,(Note4)?1.0 1.0μA

I IH Oscillator Input Current V IH=V CC=5.5V100μA

I IL Oscillator Input Current V IL=0,V CC=5.5V?100μA

V OH High-Level Output Voltage I OH=?500μA V CC?

0.4

V OL Low-Level Output Voltage I OL=500μA0.4V

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Symbol Parameter Conditions

Value

Min Typ Max

MICROWIRE TIMING

t CS Data to Clock Setup Time See Data Input Timing50 t CH Data to Clock Hold Time See Data Input Timing10 t CWH Clock Pulse Width High See Data Input Timing50 t CWL Clock Pulse Width Low See Data Input Timing50

t ES Clock to Load Enable Setup

Time See Data Input Timing

t EW Load Enable Pulse Width See Data Input Timing50 Note3:Minimum operating frequencies are not production tested—only characterized.

Note4:Except f IN and OSC IN.

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Note5:I CPo vs V CPo=Charge Pump Output Current magnitude vs Variation Voltage=

[1/2*{|I1|-|I3|}]/[1/2*{|I1|+|I3|}]*100%and[1/2*{|I4|-|I6|}]/[1/2*{|I4|+|I6|}]*100%

Note6:I CPo-SINK vs I CPo-SOURCE=Charge Pump Output Current Sink vs Source Mismatch= [|I2|-|I5|]/[1/2*{|I2|+|I5|}]*100%

Note7:I CPo vs T A=Charge Pump Outpuit Current magnitude variation vs Temperature=

[|I2@temp|-|I2@25o C|]/|I2@25o C|*100%and|I5@temp|-|I5@25o C|/|I5@25o C|*100%DS101124-9

I1=CP sink current at V CPo=V P-?V

I2=CP sink current at V CPo=V P/2

I3=CP sink current at V CPo=?V

I4=CP source current at V CPo=V P-?V

I5=CP source current at V CPo=V P/2

I6=CP source current at V CPo=?V

?V=Voltage offset from positive and negative rails.Dependent on VCO tuning range relative to V CC and ground.Typical values are between0.5V and1.0V.

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I CC vs V CC LMX2353

DS101124-10

I CPO TRI-STATE vs CP O Voltage

DS101124-11

Charge Pump Current vs CP O Voltage CP_WORD =0011and 1111

DS101124-12

Sink vs Source Mismatch

(See (Note 6)under Charge Pump Current Specification Definitions)

DS101124-13

LMX2353V P Voltage vs V P Load Current in V Doubler Mode,T =25o C

DS101124-17

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1.0Functional Description

The basic phase-lock-loop (PLL)configuration consists of a high-stability crystal reference oscillator,a frequency synthesizer such as the National Semiconductor LMX2353,a voltage controlled oscillator (VCO),and a passive loop filter.The frequency synthesizer includes a phase detector,current mode charge pump,as well as programmable reference [R]and feedback [N]frequency dividers.The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison frequency.This reference signal,fr,is then presented to the input of a phase/frequency detector and compared with another signal,fp,the feedback signal,which was obtained by dividing the VCO frequency down by way of the N counter and fractional circuitry.The phase/frequency detector’s current source outputs pump charge into the loop filter,which then converts the charge into the VCO’s control voltage.The phase/frequency comparator’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency (and phase)match that of the reference signal.When this “phase-locked”condition exists,the RF VCO’s frequency will be N+F times that of the comparison frequency,where N is the integer divide ratio and F is the fractional component.The fractional synthesis allows the phase detector frequency to be

LMX2353Sensitivity vs Frequency DS101124-15Oscillator Input Sensitivity vs Frequency

DS101124-16

RF Input Impedence

Vcc =2.7V to 5.5V,f IN =50MHz to 3GHz (f INB Capacitor =100pF)

DS101124-14

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a lower phase noise referred to the phase detector input,and the comparison frequency is increased allowing faster sw

times.

1.1REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSC IN pin.OSC IN can operate to50MHz with a minimum input sensitivity of0.5V pp.The inputs have a V CC/2input threshold and can be from an external CMOS or TTL logic gate.

1.2REFERENCE DIVIDER(R-COUNTER)

The R-counter is clocked through the oscillator block.The maximum frequency is50MHz.The R-counter is CMOS desi 15-bit in length with programmable divider ratio from3to32,767.

1.3FEEDBACK DIVIDER(N-COUNTER)

The N counter is clocked by the small signal f IN input pin.The N counter is19bits with15bits integer divide and4bits frac The integer part is configured as a5-bit A counter and a10-bit B counter.The LMX2353is capable of operating from50 to1.2GHz with the16/17prescaler offering a continuous integer divide range from272to16399,and1.2GHz to2.5GH the32/33prescaler offering a continuous integer divide range from1056to32767.The fractional compensation is program in either1/15or1/16modes.

1.3.1Prescaler

The RF input to the prescaler consist of f IN and f INB;which are complimentary inputs to a differential pair amplifie complimentary input is internally coupled to ground with a100pF capacitor.This input is typically AC coupled to ground t external capacitors as well.A16/17or32/33prescaler ratio can be selected.

1.3.2Fractional Compensation

The fractional compensation circuitry in the N divider allows the user to adjust the VCO’s tuning resolution in1/16o increments of the phase detector comparison frequency.A4-bit register is programmed with the fractions desired num while another bit selects between fractional15and16modulo base denominator.An integer average is accomplished by a4-bit accumulator.A variable phase delay stage compensates for the accumulated integer phase error,minimizing the pump duty cycle,and reducing spurious levels.This technique eliminates the need for compensation current injection in loop filter.Overflow signals generated by the accumulator are equivalent to1full VCO cycle,and result in a pulse swall

1.4PHASE/FREQUENCY DETECTOR

The phase/frequency detector is driven from the N and R counter outputs.The maximum frequency at the phase detecto is about10MHz for some high frequency VCO due to the minimum continuous divide ratio of the dual modulus prescale phase detector frequency exceeds2.37MHz,there are higher chances of running into illegal divide ratios,because the mi continuous divide ratio with a32/33prescaler is1056.The phase detector outputs control the charge pumps.The polarity pump-up or pump-down control is programmed using PD_POL depending on whether the VCO characteristics are pos negative.The phase detector also receives a feedback signal from the charge pump,in order to eliminate dead zone.

1.5CHARGE PUMPS

The phase detector’s current source output pumps charge into an external loop filter,which then integrates into the VCO’s voltage.The charge pump steers the charge pump output CP o to V CC(pump-up)or Ground(pump-down).When locked, primarily in a TRISTATE mode with small corrections.The charge pump output current magnitude can be selected from1 to1.6mA by programming the CP_WORD bits.

1.6VOLTAGE DOUBLER

The V p pin is normally driven from an external power supply over a range of V CC to5.5V to provide current for the RF pump circuit.An internal voltage doubler circuit connected between the V CC and V p supply pins alternately allows V CC (±10%)users to run the RF charge pump circuit at close to twice the V CC power supply voltage.The Voltage doubler m enabled by setting the V2_EN bit(R[20])to a HIGH level.The average delivery current of the doubler is less th instantaneous current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out condition.A large external capacitor connected to V p(≈0.1μF)is therefore needed to control power supply droop when ch frequencies.

1.7MICROWIRE?SERIAL INTERFACE

The programmable functions are accessed through the MICROWIRE serial interface.The interface is made of three fun clock,data and latch enable(LE).Serial data for the various counters is clocked in from data on the rising edge of clock,i 24-bit shift register.Data is entered MSB first.The last two bits decode the internal register address.On the rising edge data stored in the shift register is loaded into one of the4appropriate latches(selected by address bits).A complete progra description is included in the following sections.

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The F o LD output pin can deliver several internal functions including analog/digital lock detects,and counter outputs.See programming description2.4.2for more details.

1.8.1Lock Detect Output

A digital filtered lock detect function is included with each phase detector through an internal digital filter to produce a logic level output available on the F O LD output pin if selected.The lock detect output is high when the error between the phase detector inputs is less than15ns for5consecutive comparison cycles.The lock detect output is low when the error between the phase detector inputs is more than30ns for one comparison cycle.An analog lock detect status generated from the phase detector is also available on the F O LD output pin,if selected.The lock detect output goes high when the charge pump is inactive.It goes low when the charge pump is active during a comparison cycle.When a PLL is in power down mode,the respective lock detect output is always low.See programming descriptions2.4.2.2-2.4.2.4.

1.9OUT0/OUT1Output Modes(FastLock&CMOS Output Modes)

The OUT_0and OUT_1pins are normally used as general purpose CMOS outputs or as part of a FastLock scheme.There is also a production test mode that overrides the other two normal modes when activated.The selection of these modes is determined by the4bit CMOS register(F2_15–18)described in Table2.5.3.

The FastLock mode allows the user to open up the loop bandwidth momentarily while acquiring lock by increasing the charge pump output current magnitude while simultaneously switching in a second resistor element to ground via the OUT0output pin. The loop will lock faster without any additional stability considerations as the phase margin remains constant.

The loop bandwidth during FastLock can be opened up by as much as a factor of4.The amount of bandwidth increase is a function of the square root of the charge pump current increase.The maximum charge pump current ratio results from switching the charge pump current between100μA and1.6mA.The damping resistor ratio for these two charge pump current setting changes by the reciprocal of the bandwidth change.In the4to1bandwidth scenerio,the resulting damping resistor value would be1/4th of the steady state value.This would be achieved by switching3more identical resistors in parallel with the first to ground through the OUT_0pin.

1.10POWER CONTROL

The PLL is power controlled by the device enable pin(CE)or MICROWIRE power down bit.The enable pin overrides the power down bit except for the V2_EN bit.When CE is high,the power down bit determines the state of power control.Activation of any PLL power down mode results in the disabling of the N counter and de-biasing of f IN input(to a high impedance state).The R counter functionality also becomes disabled when the power down bit is activated.The reference oscillator block powers down and the OSC IN pin reverts to a high impedance state when CE or power down bit’s are asserted,unless the V2_EN bit(R[20]) is high.Power down forces the charge pump and phase comparator logic to a TRISTATE condition.A power down counter reset function resets both N and R counters.Upon powering up the N counter resumes counting in“close”alignment with the R counter (The maximum error is one prescaler cycle).The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes.

2.0Programming Description

2.1MICROWIRE INTERFACE

The LMX2353register set can be accessed through the MICROWIRE interface.A24-bit shift register is used as a temporary register to indirectly program the on-chip regis-ters.The shift register consists of a24-bit DATA[21:0]field and a2-bit ADDRESS[1:0]field as shown below.The ad-dress field is used to decode the internal register address. Data is clocked into the shift register in the direction from MSB to LSB,when the CLK signal goes high.On the rising edge of Latch Enable(LE)signal,data stored in the shift register is loaded into the addressed latch.

MSB LSB DATA[21:0]ADDRESS[1:0] 23210

2.1.1Registers’Address Map

When Latch Enable(LE)is transitioned high,data is trans-ferred from the24-bit shift register into the appropriate latch depending on the state of the ADDRESS[1:0]bits.A multi-plexing circuit decodes these address bits and writes the data field to the corresponding internal register.

ADDRESS[1:0]

FIELD

ADDRESSED

00F1Register

01F2Register

10R Register

11N Register

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NATIONAL-SEMICONDUCTOR

LMX2353TM/NOPB LMX2353TMX/NOPB LMX2353SLBX