ICS601M-01中文资料

The ICS601-01 is a low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10-27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V.

Block Diagram

Description

Features

? Packaged in 16 pin SOIC or TSSOP

? Uses fundamental 10 - 27 MHz crystal, or clock ? Patented PLL with the lowest phase noise ? Output clocks up to 156 MHz at 3.3 V ? Low phase noise: -132 dBc/Hz at 10 kHz ? Output Enable function tri states outputs ? Low jitter - 18 ps one sigma

? Full swing CMOS outputs with 25 mA drive capability at TTL levels

? Advanced, low power, sub-micron CMOS process ? Industrial temperature version available

? 3.3 V or 5 V operation

CLK

REFOUT

Pin Descriptions

Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, XO = crystal connections.

Pin Assignment

ICS601-01

1=connect directly to VDD

S0GND GND REFOUT OE CLK REFEN S1X2VDD VDD VDD X1/ICLK

S3GND S2

Multiplier Select Table

-140

-120

-100

10.0E+0

100.0E+0 1.0E+310.0E+3100.0E+3 1.0E+610.0E+6

Offset from Carrier (Hz)

P h a s e N o i s e (d B c /H z )

Figure 1. Phase Noise of ICS601-01 at 125 MHz out, 25 MHz crystal input.

VDD = 3.3 V, REFOUT disabled.

Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will increase the phase noise, so it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 μF in parallel with 0.01 μF. It is important to have these capacitors as close as possible to the ICS601-01 supply pins.

Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can reduce the phase noise by as much as 10 dBc/Hz.

Achieving Low Phase Noise

External Components/Crystal Selection

The ICS601-01 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01 μF and 0.1 μF should be connected between VDD and GND, as close to the part as possible. A series termination resistor of 33 ? may be used for each clock output. The crystal must be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these capacitors is given by the following equation, where C L is the crystal load capacitance: Crystal caps (pF) = (C L -5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board capacitance and recommend the exact capacitance value to use.

Electrical Specifications

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. The phase relationship between input and output can change at power up. For a fixed phase relationship, see the ICS570

or ICS670.

3. Switching occurs nominally at VDD/2.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its

use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

Package Outline and Package Dimensions

(For current dimensional specifications, see JEDEC no. 95.)

Ordering Information

16 pin narrow SOIC, TSSOP (in mm)