KK74HC14AD中文资料
TECHNICAL DATA
KK 74HC14A
Hex Schmitt-Trigger Inverter
The KK 74HC14A is identical in pinout to the LS/ALS14. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
The KK 74HC14A is useful to “square up” slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the KK 74HC14A finds
applications in noisy environments.
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 μA
? High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 14 =V CC PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output A Y L H
H L
MAXIMUM RATINGS*
Symbol Parameter Value
Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V
V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V
I IN DC Input Current, per Pin ±20 mA
I OUT DC Output Current, per Pin ±25 mA
I CC DC Supply Current, V CC and GND Pins ±50 mA
P D Power Dissipation in Still Air, Plastic DIP** SOIC Package** 750
500
mW
Tstg Storage Temperature -65 to +150 °C
T L Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min
Max
Unit V CC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V
T A Operating Temperature, All Package Types -55 +125 °C
t r , t f Input Rise and Fall Time (Figure 1) - No
Limit*
ns
* When V IN ≈50% V CC , I CC > 1mA
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or
V OUT)≤V CC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused
outputs must be left open.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V CC
Guaranteed Limit
Symbol Parameter
Test Conditions V 25 °C
to -55°C
≤85 °C ≤125 °C Unit
V T +max Maximum Positive-Going Input Threshold
Voltage V OUT =0.1 V ?I OUT ?≤ 20 μA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V
V T +min Minimum Positive-Going Input Threshold
Voltage V OUT =0.1 V ?I OUT ?≤ 20 μA 2.0 4.5 6.0 1.0 2.3 3.0 0.95 2.25 2.95 0.95 2.25 2.95 V
V T -max Maximum Negative-Going Input Threshold
Voltage V OUT =V CC -0.1 V ?I OUT ?≤ 20 μA 2.0 4.5 6.0 0.9 2.0 2.6 0.95 2.05 2.65 0.95 2.05 2.65 V
V T -min Minimum Negative-Going Input Threshold
Voltage V OUT =V CC -0.1 V ?I OUT ?≤ 20 μA
2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V
V H max *
Maximum Hysteresis Voltage
V OUT =0.1 V or V CC -0.1 V ?I OUT ?≤ 20 μA
2.0 4.5 6.0 1.2 2.25
3.0 1.2 2.25 3.0 1.2 2.25 3.0 V
V H min * Minimum Hysteresis Voltage
V OUT =0.1 V or V CC -0.1 V ?I OUT ?≤ 20 μA 2.0 4.5 6.5 0.2 0.4 0.5 0.2 0.4 0.5 0.2 0.4 0.5 V
V OH Minimum High-Level Output Voltage V IN ≤V T -min ?I OUT ? ≤ 20 μA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V
V IN ≤V T -min ?I OUT ?≤4mA ?I OUT ?≤5.2mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2
V OL
Maximum Low-Level Output Voltage V IN ≥V T +max ?I OUT ? ≤ 20 μA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V
V IN ≥V T +max ?I OUT ?≤ 4mA ?I OUT ?≤5.2mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4
I IN Maximum Input Leakage Current V IN =V CC or GND 6.0
±0.1
±1.0
±1.0
μA
I CC
Maximum Quiescent Supply Current (per Package)
V IN =V CC or GND I OUT =0μA
6.0 1.0 10 40 μA
* V H min>(V T +min)-(V T -max); V H max=(V T +max)-(V T -min)
.
AC ELECTRICAL CHARACTERISTICS (C L =50pF, t r =t f =6.0 ns)
V CC
Guaranteed Limit
Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C
Unit
t PLH , t PHL
Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2)
2.04.56.095 19 16 120 24 20 145 29 25 ns
t TLH , t THL Maximum Output Transition Time, Any Output (Figures 1 and 2)
2.04.56.075 15 13 95 19 16 110 22 19 ns
C IN Maximum Input Capacitance
-
10
10
10
pF Power Dissipation Capacitance (Per Inverter) T A =25°C,V CC =5.0 V
C PD
Used to determine the no-load dynamic power consumption:
P D =C PD V CC 2f+I CC V CC
22 pF
Figure 1. Switching Waveforms Figure 2. Test Circuit