Philips_I2S

1. Philips I 2S Serial Bus Protocol Overview

In consumer and professional audio products of recent years, the analog or digital ‘f ront-end’ of the DSP uses a digital audio

serial protocol known as I 2

S. Audio interfaces between various ICs in the past was hampered because each manufacturer had dedicated audio interfaces that made it extremely difficult to interface these devices to each other. Standardization of audio interfaces was promoted by Philips with the development of the Inter-IC-Sound (I 2S) bus , a serial interface developed for digital audio to enable easy connectivity and ensure successful designs. In short , I 2S is a popular 3 wire serial bus standard protocol developed by Philips for transmission of 2 channel (stereo) Pulse Code Modulation digital data, where each audio sample is sent MSB first . I 2S signals, shown in Figures 1 and 2, consist of a bit-clock, Left/Right Clock (also is often referred to as the Word Select) and alternating left and right channel data. This protocol can be compared to synchronous serial ports in TDM mode with 2 timeslots (or channels) active. This multiplexed protocol requires only 1 data path to send/receive 2channels of digital audio information.

I 2

S Digital Audio Serial Bus Interface Examples

Transmitter

Reciever

Transmitter

Reciever

Figure 1

Example I 2S Timing Diagram for 16-bit

Stereo PCM Audio Data

SCLK

FS Clock

M S B

L S B M S B

L S B

Left Sample

Right Sample

Audio data word sizes supported by various audio converter manufacturers range can be either

16, 18, 20, or 24 bits

Figure 2.As a result, today many analog and digital audio 'front-end' devices support the I 2

S protocol. Some of these devices include:

? Audio A/D and D/A converters ? PC Multimedia Audio Controllers

? Digital Audio Transmitters and Receivers that support serial digital audio transmission standards such as

AES/EBU, SP/DIF, IEC958, CP-340 and CP-1201.? Digital Audio Signal Processors ? Dedicated Digital Filter Chips ? Sample Rate Converters

The ADSP-21065L has 4 transmit and receive data pins (DT0A, DT0B, DT1A, DT1B), providing I 2S serial port support for interfacing to up to 8 commercially available I 2S stereo devices, yielding 16 channels of audio with only 2 serial ports. The ADSP-21065L's built-in support for the I 2S protocol eliminates the need for interface logic with a FPGA and result in a simple,glueless interface.

In addition to the master/slave timing generation of the word select and serial clock signals, it is also possible to generates the clocks with an external controller or another audio device, which in effect makes both I2S devices slaves. An example of this is shown in Figure 3. So for multiple devices, it is possible to synchronize all samples being transmitted or received with both SPORTs through a common clock and word select signal.

Figure 3. I2S Digital Audio Serial Bus Master Controller

Controller = Serial Bus

So this serial format efficiently transfers two-channel audio data for each I2S interconnection, while other control, status, and sub-coding signals (for example, AES/EBU devices used in ADAT equipment and SP/DIF devices found in DVD players) are transferred through a separate interface. As shown in the above figures, the buses three lines are:

?Continuous serial clock - SCK (RCLKx or TCLKx if the 21065L is the master)

?Word Select –WS (RFSx or TFSx if the 21065L is the master)

?Serial Data - SD ( DTx, DRx on the 21065L SPORTs), this is in a 2-channel time-division multiplexed format The transmitter, receiver or and system clock controller generates the serial clock and word select signals. Thus the I2S device that generates the serial clock and word select is the master I2S device.

The Philips I2S bus defines the following:

Serial Data Pins:

?Serial data is transmitted in two’s complement format, with the MSB transmitted first, because the transmitter and receiver may have different word lengths.

?The receiver ignores extra bits from the transmitter if greater than it’s capable (or programmed) serial length.

?If the receiver’s word length is greater than the data sent, all missing bits are set to zero internally

?The transmitter always sends the MSB of the next word one clock period after the WS changes.

?Serial data sent by the Transmitter can be sync’e d with either the trailing or leading edge of the SCLK.

?The Receiver (or the device in Slave Mode) always latches data on the leading edge of SCLK.

Word Select Pins:

?When WS = 0 or ‘l ow’, the data is Channel 1, or Left Channel data in a stereo system.

?When WS = 0 or ‘l ow’, the data is Channel 2, or Right Channel data in a stereo system.

?WS may change on a trailing or leading edge of the SCLK, but it does not need to be symmetrical.

?WS changes state one SCLK period before the MSB is transmitted.

?In slave mode, the data is latched on the leading edge of the serial clock signal.

?The slave determines synchronous timing of the serial data that will be transmitted, based on the external clock generated by the master. The WS signal is latched on the leading edge of the clock signal. The slave takes into

account the propagation delays between the master clock and the data and/or word select signals. Thus, the total

delay is simply the sum of

-The delay between the master clock and the slave’s internal clock

-The delay between the internal clock and the data and/or the word select signals.

Other I2S Specification Notes:

?To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal, always giving the reciever sufficient setup time.

?The data setup and hold time must not be less than the specified reciever set-up and hold time.

?In slave mode, the transmitter and receiver meed a clock signal with minimum HIGH and LOW periods so that they can detect the signal.

?Any device can act as the serial bus master by providing the necessary clock signals.