pg143-axi-uart16550
AXI UART 16550 v2.0 LogiCORE IP Product Guide
Vivado Design Suite
PG143 October 5, 2016
Table of Contents
IP Facts
Chapter1:Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter2:Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter3:Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter4:Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Synthesis and Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter5:Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example Design Directory Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter6:Test Bench
Appendix A:Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Appendix B:Debugging
Finding Help on https://www.wendangku.net/doc/1618221004.html, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix C:Additional Resources and Legal Notices
Xilinx Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction
The LogiCORE? IP AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the Advance Microcontroller Bus Architecture (AMBA?) AXI and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to connect through an AXI4-Lite interface.
The AXI UART 16550 detailed in this document incorporates features described in the PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs Data Sheet[Ref1].
The PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the PC16550D and the AXI UART 16550 product guide are highlighted in Interrupts in Chapter2.
Features
?AXI4-Lite interface for register access and data transfers
?Hardware and software register compatible with all standard 16450 and 16550 UARTs
?Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity ?Implements all standard serial interface protocols °5, 6, 7 or 8 bits per character
°Odd, Even or no parity detection and generation °1, 1.5 or 2 stop bit detection and generation
°Internal baud rate generator and separate
receiver clock input
°Modem control functions
°Prioritized transmit, receive, line status and modem control interrupts
°False start bit detection and recover
°Line break detection and generation
°Internal loopback diagnostic functionality
°16 character transmit and receive FIFOs
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family(1)
UltraScale+?
UltraScale?
Zynq?-7000,
7 Series Supported
User
Interfaces
AXI4-Lite Resources See Table2-2.
Provided with Core
Design Files VHDL Example
Design VHDL Test Bench VHDL Constraints
File Xilinx Design Constraints (XDC) File Simulation
Model Not Provided Supported
S/W Driver(2)Standalone and Linux
Tested Design Flows(3)
Design Entry Vivado? Design Suite
Simulation For supported simulators, see the
Xilinx Design Tools: Release Notes Guide. Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page Notes:
1.For a complete list of supported devices, see the
Vivado IP catalog.
2.Standalone driver details can be found in the software
development kit (SDK) directory
Linux OS and driver support information is available from the Xilinx Wiki page.
3.For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
Chapter1
Overview
The AXI UART 16550 IP core implements the hardware and software functionality of the PC16550D UART, which works in both the 16450 and 16550 UART modes. For complete
details, see the PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs data
sheet[Ref1].
The AXI UART 16550 core performs parallel-to-serial conversion on characters received
from the AXI master and serial-to-parallel conversion on characters received from a modem or serial peripheral. The AXI UART 16550 is capable of transmitting and receiving 8, 7, 6, or 5-bit characters, with 2, 1.5 or 1 stop bits and odd, even or no parity. The AXI UART 16550 can transmit and receive independently.
The AXI UART 16550 core has internal registers to monitor its status in the configured state.
The core can signal receiver, transmitter, and modem control interrupts. These interrupts can be masked and prioritized, and they can be identified by reading an internal register.
The core contains a 16-bit, programmable, baud-rate generator, and independent,
16-character-length transmit and receive FIFOs. The FIFOs can be enabled or disabled
through software.
The top-level block diagram for the AXI UART 16550 core is shown in Figure1-1. Array
Figure 1-1:UART 16550 Block Diagram
The AXI UART 16550 modules are described in these sections:
?AXI Interface: This block implements the AXI4-Lite slave interface for register access and data transfer.
?UART Control: This block consists of the following.
°RX Control – This block samples received data with respect to generated baud rate and writes it to Receive Data FIFO.
°TX Control – This block reads data from Transmit Data FIFO and sends it out on UART TX interface.
°BRG (Baud Rate Generator) – This block generates various baud rates that are user programmed.
°Interrupt Control
The AXI UART 16550 core provides separate interrupt enable and interrupt
identification registers. If interrupts are enabled, a level-sensitive interrupt is
generated for the following conditions. See Interrupts in Chapter2 for more details.
-Receiver line status
-Received data available
-Character timeout
-Transmitter holding register empty
-Modem status
Feature Summary
?AXI4-Lite interface for register access and data transfers
?Hardware and software register compatible with all standard 16450 and 16550 UARTs ?Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity
?Implements all standard serial interface protocols
°5, 6, 7 or 8 bits per character
°Odd, Even or no parity detection and generation
°1, 1.5 or 2 stop bit detection and generation
°Internal baud rate generator and separate receiver clock input
°Modem control functions
°Prioritized transmit, receive, line status and modem control interrupts
°False start bit detection and recover
°Line break detection and generation
°Internal loopback diagnostic functionality
°16 character transmit and receive FIFOs
Licensing and Ordering Information
This Xilinx LogiCORE? IP module is provided at no additional cost with the Xilinx Vivado? Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.
Chapter2 Product Specification
Performance
The AXI UART 16550 is characterized as per the benchmarking methodology described in Appendix A, IP Characterization and F MAX Margin System Methodology, Vivado Design Suite User Guide: Designing With IP (UG896) [Ref2]. Table2-1 shows the results of the
characterization runs.
Note:Frequency data for UltraScale? and Zynq?-7000 devices are expected to be similar to 7 series device numbers.
Table 2-1:Maximum Frequencies
Family Speed Grade Fmax (MHz) for AXI4-Lite
Virtex-7
-1180
Kintex-7180 Artix-7120
Virtex-7
-2200
Kintex-7200 Artix-7140
Virtex-7
-3220
Kintex-7220 Artix-7160
Resource Utilization
The AXI UART 16550 resource utilization for various parameter combinations measured with three architectures is shown in Table 2-2.Table 2-2:
Resource Estimations for 7 Series, Zynq, and UltraScale Devices
U A R T M o d e
U s e E x t e r n a l C l o c k f o r B a u d R a t e
E n a b l e E x t e r n a l R e c e i v e r C l o c k
S l i c e s /C L B
R e g i s t e r s
L U T s
UltraScale
16550
11683183421655000653083451645000522592627 Series and Zynq
16550
11120318352165500011830834716450
82
259
252
Port Descriptions
The I/O signals are listed and described in Table2-3. Table 2-3:I/O Signals
Signal Name Interface Signal
Type Initial
State Description System Signals
s_axi_aclk System I-AXI Clock
s_axi_aresetn System I-AXI Reset signal, active-Low
ip2intc_irpt System O0Device interrupt output to microprocessor interrupt
input or system interrupt controller (active-High)
freeze System I-This is used to freeze the UART. When pulled High, the interrupts are disabled and the internal state machine goes into idle state.
s_axi_*S_AXI--See Appendix A of the Vivado AXI Reference Guide
(UG1037) [Ref3] for description of AXI4 Signals.
UART Interface Signals
baudoutn Serial O116 x clock signal from the transmitter section of the
UART
rclk Serial I-Receiver 16x clock (Optional, can be driven externally under control of the Enable External Receiver CLK parameter)
sin Serial I-Serial data input sout Serial O1Serial data output
xin Serial I-Baud rate generator reference clock (Optional, can be driven externally under control of the Use External CLK for BAUD Rate parameter)
xout Serial O0If Use External CLK for BAUD Rate = 0, Xout is 0, if Use External CLK for BAUD Rate = 1 Xout can be used as reference feedback clock for Baud rate generator
ctsn Modem I-Clear to send (active-Low).
When Low, this indicates that the MODEM or data set is ready to exchange data.
dcdn Modem I-Data carrier detect (active-Low).
When Low, indicates that the data carrier has been detected by the MODEM or data set.
dsrn Modem I-Data set ready (active-Low).
When Low, this indicates that the MODEM or data set is ready to establish the communication link with the UART.
dtrn
Modem
O
1
Data terminal ready (active-Low).
When Low, this informs the MODEM or data set that the UART is ready to establish a communication link.rin Modem I -
Ring indicator (active-Low).
When Low, this indicates that a telephone ringing signal has been received by the MODEM or data set.rtsn Modem O 1
Request to send (active-Low).
When Low, this informs the MODEM or data set that the UART is ready to exchange data.
ddis User O 1Driver disable. This goes Low when CPU is reading data from UART.
out1n User O 1User controlled output our2n User O 1User controlled output rxrdyn User O 1DMA control signal txrdyn
User
O
DMA control signal
Table 2-3:
I/O Signals (Cont’d)
Signal Name
Interface
Signal Type Initial State
Description
Register Space
Some of the internal registers are accessible only when bit 7 of the Line Control register (LCR) is set. The AXI UART 16550 internal register set is described in Table 2-4.
Note:The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata ) signal,
and is not impacted by the AXI Write Data Strobe (*_wstrb ) signal. For a Write, both the AXI Write Address Valid (*_awvalid ) and AXI Write Data Valid (*_wvalid ) signals should be asserted together.
Receiver Buffer Register
This 32-bit read register is shown in Figure 2-1. The Receiver Buffer register contains the last received character. The bit definitions for the register are shown in Table 2-5. The offset and accessibility of this register value is as shown in Table 2-4.
Table 2-4:
Register Address Map
LCR(7)Address Offset Register Name Access Type Description
00x1000RBR RO Receiver Buffer Register 00x1000THR WO Transmitter Holding Register 00x1004IER R/W Interrupt Enable Register x 0x1008IIR RO Interrupt Identification Register x 0x1008FCR WO FIFO Control Register 10x1008FCR RO FIFO Control Register x 0x100C LCR R/W Line Control Register x 0x1010MCR R/W Modem Control Register x 0x1014LSR R/W Line Status Register x 0x1018MSR R/W Modem Status Register x 0x101C SCR R/W Scratch Register
10x1000DLL R/W Divisor Latch (Least Significant Byte) Register 1
0x1004
DLM
R/W
Divisor Latch (Most Significant Byte) Register
Figure 2-1:Receiver Buffer Register (RBR)
Transmitter Holding Register
This 32-bit write register is shown in Figure 2-2. The Transmitter Holding register contains the character to be transmitted next. The bit definitions for the register are shown in Table 2-6. The offset and accessibility of this register is shown in Table 2-4.
Interrupt Enable Register
This 32-bit read/write register is shown in Figure 2-3. The Interrupt Enable register contains the bits which enable interrupts. The bit definitions for the register are shown in Table 2-7. The offset and accessibility of this register value is shown in Table 2-4.
Table 2-5:Receiver Buffer Register Bit Definitions Bits
Field Name
Access Type
Reset Value
Description
31-8Reserved N/A N/A Reserved
7-0
RBR
RO
0x0
Last received character
Figure 2-2:
Transmitter Holding Register (THR)
Table 2-6:Transmitter Holding Register Bit Definitions Bits
Name
Access
Reset Value
Description
31-8Reserved N/A N/A Reserved
7-0
THR
WO
0xFF
Holds the character to be transmitted next
Figure 2-3:
Interrupt Enable Register (IER)
Table 2-7:Interrupt Enable Register Bit Definitions Bits
Name
Access
Reset Value
Description
31-4Reserved N/A N/A Reserved
3
EDSSI
R/W
0x0
Enable Modem Status Interrupt.0 = Disables Modem Status Interrupts.1 = Enables Modem Status Interrupts.
Interrupt Identification Register
This 32-bit read register is shown in Figure 2-4. The Interrupt Identification register
contains the priority interrupt identification. The bit definitions for the register are shown in Table 2-8. The offset and accessibility of this register value is shown in Table 2-4.
2
ELSI
R/W
0x0
Enable Receiver Line Status Interrupt.0 = Disables Receiver Line Status Interrupts.1 = Enables Receiver Line Status Interrupts.1ETBEI R/W 0x0
Enable Transmitter Holding Register Empty Interrupt.
0 = Disables Transmitter Holding Register Empty Interrupts.
1 = Enables Transmitter Holding Register Interrupts.
0ERBFI R/W 0x0
Enable Received Data Available Interrupt.0 = Disables Received Data Available Interrupts.
1 = Enables Received Data Available Interrupts.
Figure 2-4:
Interrupt Identification Register (IIR)
Table 2-8:Interrupt Identification Register Bit Definitions Bits
Name
Access
Reset Value
Description
31-8(2)
Reserved
N/A
N/A
Reserved
7-6FIFOEN (1)RO 0x0
FIFOs Enabled. Always zero if not in FIFO mode.
0 - 16450 mode 1 - 16550 mode 5-4Reserved RO 0
Reserved
Table 2-7:Interrupt Enable Register Bit Definitions (Cont’d)Bits
Name
Access
Reset Value
Description
FIFO Control Register
This is 32-bit write/read register is shown in Figure 2-5. The FIFO Control register contains the FIFO configuration bits. The bit definitions for the register are shown in Table 2-9. The offset and accessibility of this register value is shown in Table 2-4. The DMA mode signaling information is given in Table 2-10.
3-1
INTID2
RO
0x0
Interrupt ID.
011 = Receiver Line Status (Highest).(4)010 = Received Data Available (Second).
110 = Character Timeout (Second).001 = Transmitter Holding Register Empty (Third).
000 = Modem Status (Fourth).
INTPEND (3)RO 0x1
0 - Interrupt is pending 1 - No interrupt is pending
Notes:
1.Bits are always zero in 16450 UART mode.
2.Reading these bits always return 00
3.If INTPEND = 0, interrupt is pending. See the PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs data sheet [Ref 1] for more details.
4.Line status interrupt is generated for framing, parity, overrun error and break condition.
Figure 2-5:FIFO Control Register (FCR)
Table 2-8:Interrupt Identification Register Bit Definitions (Cont’d)Bits
Name
Access
Reset Value
Description
Line Control Register
This 32-bit write/read register is shown in Figure 2-6. The Line Control register contains the serial communication configuration bits. The bit definitions for the register are shown in Table 2-11. The offset and accessibility of this register value is shown in Table 2-4.
Table 2-9:FIFO Control Register Bit Definitions (1)Bits
Name
Access
Reset Value
Description
31-8
Reserved
N/A
N/A
Reserved
7-6
RCVR FIFO Trigger Level
R/W 0x0RCVR FIFO Trigger Level.00 = 1 byte.
01 = 4 bytes.10 = 8 bytes.11 = 14 bytes.
5-4Reserved RO 0Reserved
3
DMA Mode
Select R/W
0x0
DMA Mode Select.0 = Mode 0.1 = Mode 1.
2XMIT FIFO Reset R/W 0x0Transmitter FIFO Reset.1 = Resets XMIT FIFO.1
RCVR FIFO Reset R/W
0x0
Receiver FIFO Reset.1 = Resets RCVR FIFO.0
FIFOEN
R/W 0x0
FIFO Enable.1 = Enables FIFOs.0 = Disables FIFOs
Notes:
1.FCR is not included in 16450 UART mode.
Table 2-10:DMA Modes Signaling (1)DMA Mode
txrdyn
RXRDYn
Mode 0
In the 16450 mode or in mode 0, when there are
no characters in the THR or Transmitter FIFO, this
signal is Low. This signal goes High again after
the first character is loaded into the THR or FIFO.
In the 16450 mode or in mode 0, when there is at
least one character in the Receiver FIFO or
Receiver holding register, this signal is Low. This
signal goes High again when there are no
characters in FIFO or receiver holding register.Mode 1
When there are no characters in the Transmitter
FIFO, this signal goes Low. This signal goes High
again if the FIFO is completely full.
When the trigger level or the timeout has been
reached, this signal goes Low. This signal goes
High again when there are no characters in the
FIFO or receiver holding register.
Notes:
1.See Table 2-9, bit 3.
Figure 2-6:Line Control Register (LCR) Table 2-11:Line Control Register Bit Definitions
Bits Name Access Reset Value Description 31-8Reserved N/A N/A Reserved
7DLAB R/W0x0Divisor Latch Access Bit.
1 = Allows access to the Divisor Latch Registers and reading of the FIFO Control Register.
0 = Allows access to RBR, THR, IER and IIR registers.
6Set Break R/W0x0Set Break.
1 = Enables break condition. Sets SOUT to 0 and cause break condition.
0 = Disables break condition.
5Stick Parity R/W0x0Stick Parity.
1 = When bits 3, 4 are logic 1 the Parity bit is transmitted and checked as a logic 0. If bit 4 is a logic 0 and bit 3 is logic 1 then the Parity bit is transmitted and checked as a logic 1.
0 = Stick Parity is disabled.
4EPS R/W0x0Even Parity Select.
1 = Selects Even parity.
0 = Selects Odd parity.
3PEN R/W0x0Parity Enable.
1 = Enables parity.
0 = Disables parity.
2STB R/W0x0Number of Stop Bits.
0 = 1 Stop bit.
1 =
2 Stop bits or 1.5, if 5 bits/character selected.
The receiver checks for 1 stop bit only regardless of the number of stop bits selected.
1-0WLS R/W0x0Word Length Select.
00 = 5 bits/character.
01 = 6 bits/character.
10 = 7 bits/character.
11 = 8 bits/character.
Table 2-11:Line Control Register Bit Definitions (Cont’d)
Bits Name Access Reset Value Description
Modem Control Register
This 32-bit write/read register is shown in Figure 2-7. The Modem Control register contains the modem signaling configuration bits. The bit definitions for the register are shown in Table 2-12. The offset and accessibility of this register value is shown in Table 2-4.
Figure 2-7:
Modem Control Register (MCR)
Table 2-12:Modem Control Register Bit Definitions
Bits
Name
Access
Reset Value
Description
31-8Reserved N/A N/A Reserved 7-5
N/A
RO
0x0(1)
Always 0004Loop R/W 0x0Loop Back.
1 = Enables loopback.0 = Disables loopback.3Out2R/W 0x0User Output 2.
1 = Drives OUT2N Low.0 = Drives OUT2N High.2Out1R/W 0x0User Output 1.
1 = Drives OUT1N Low.0 = Drives OUT1N High.1RTS R/W 0x0Request To Send.
1 = Drives RTSN Low.0 = Drives RTSN High.0
DTR R/W 0x0Data Terminal Ready.
1 = Drives DTRN Low.0 = Drives DTRN High.
Notes:
1.Reading these bits always returns 000.
Line Status Register
This 32-bit write/read register as shown in Figure 2-8. The Line Status register contains the current status of receiver and transmitter. The bit definitions for the register are shown in Table 2-13. The offset and accessibility of this register value is shown in Table 2-4.
Figure 2-8:
Line Status Register (LSR)
Table 2-13:Line Status Register Bit Definitions
Bits
Name
Access
Reset Value
Description
31-8Reserved N/A N/A Reserved
7
Error in RCVR FIFO
R/W
0x0
Error in RCVR FIFO (1): RCVR FIFO contains at least one receiver error (Parity, Framing, Break condition).6TEMT R/W 0x1
Transmitter Empty:
0 - THR or Transmitter shift register contains data.
1 - THR and Transmitter shift register empty. In FIFO mode, Transmitter FIFO and shift register are both empty.
5THRE R/W 0x1
Transmitter Holding Register Empty.0 - THR or Transmitter FIFO has data to transmit.
1 - THR is empty. In FIFO mode, Transmitter FIFO is empty.4BI R/W 0x0
Break Interrupt.
Set when SIN is held Low for an entire
character time. (Start + data bits + Parity + Stop bits). In FIFO mode, this error is associated with a particular character in FIFO. The next character transfer is enabled if the Sin goes to marking state and receives the next valid start bit.3FE R/W 0x0
Framing Error.
Character missing a stop bit. In framing error, the UART attempts to re-synchronize by assuming that the framing error was due to next character start bit, so it samples start bit twice and then takes in following data. In FIFO mode, this error is associated with a particular character in the FIFO.