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74ABT899CQC中文资料

November 1992

Revised January 1999

74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker ? 1999 Fairchild Semiconductor Corporation DS011509.prf https://www.wendangku.net/doc/2955424.html, 74ABT899

9-Bit Latchable Transceiver

with Parity Generator/Checker

General Description

The ABT899 is a 9-bit to 9-bit parity transceiver with trans-

parent latches. The device can operate as a feed-through

transceiver or it can generate/check parity from the 8-bit

data busses in either direction.

The ABT899 features independent latch enables for the A-

to-B direction and the B-to-A direction, a select pin for

ODD/EVEN parity, and separate error signal output pins for

checking parity.

Features

s Latchable transceiver with output sink of 64mA

s Option to select generate parity and check or

“feed-through” data/parity in directions A-to-B or B-to-A

s Independent latch enables for A-to-B and B-to-A

directions

s Select pin for ODD/EVEN parity

s ERRA and ERRB output pins for parity checking

s Ability to simultaneously generate and check parity

s May be used in systems applications in place of the

543 and 280

s May be used in system applications in place of the

657 and 373 (no need to change T/R to check parity)

s Guaranteed output skew

s Guaranteed multiple output switching specifications

s Output switching specified for both 50 pF and

250 pF loads

s Guaranteed simultaneous switching noise level and

dynamic threshold performance

s Guaranteed latchup protection

s High impedance glitch free bus loading during entire

power up and power down cycle

s Nondestructive hot insertion capability

s Disable time less than enable time to avoid bus

contention

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignment

for PLCC

Pin Assignment for

SOIC and SSOP

Order Number Package Number Package Description

74ABT899CSC M28B28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body

74ABT899CMSA MSA2828-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT899CQC V28A28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square

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74A B T 899

Pin Descriptions

Functional Description

The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions.

?Bus A (B) communicates to Bus B (A), parity is gener-ated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA).?Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU).?Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function T able below).

Function Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Note 1: O/E = ODD/EVEN

Pin Names Descriptions

A 0–A 7 A Bus Data Inputs/Data Outputs

B 0–B 7 B Bus Data Inputs/Data Outputs APAR, BPAR A and B Bus Parity Inputs/Outputs ODD/EVEN ODD/EVEN Parity Select,Active LOW for EVEN Parity GBA, GAB Output Enables for A or B Bus,Active LOW

SEL

Select Pin for Feed-Through or

Generate Mode, LOW for Generate Mode

LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode

ERRA, ERRB

Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs

Inputs

Operation

GAB GBA SEL LEA LEB H H X X X Busses A and B are 3-ST ATE.

H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB.

Generates parity from B[0:7] based on O/E. Generated parity → APAR. Gener-ated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.

H L L X L Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB.H L H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB.H

BPAR/B[0:7] → APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.

L H L H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Gener-ated parity checked against APAR and output as ERRA.

Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Gener-ated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.

L H L L X Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA.L

APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as ERRA.

APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.

74ABT899

Functional Block Diagram

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74A B T 899

Absolute Maximum Ratings (Note 2)

Recommended Operating Conditions

Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 3: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Note 4: Guaranteed, but not tested.Note 5: Add 3.75 mA for each ERR LOW.

Storage Temperature

?65°C to +150°C Ambient T emperature under Bias ?55°C to +125°C

Junction T emperature under Bias Plastic

?55°C to +150°C V CC Pin Potential to Ground Pin ?0.5V to +7.0V Input Voltage (Note 3)?0.5V to +7.0V Input Current (Note 3)?30 mA to +5.0 mA Voltage Applied to Any Output in the Disable or Power-Off State ?0.5V to +5.5V in the HIGH State ?0.5V to V CC Current Applied to Output in LOW State (Max)

twice the rated I OL (mA)

DC Latchup Source Current ?500 mA

Over Voltage Latchup (I/O)

10V

Free Air Ambient Temperature ?40°C to +85°C Supply Voltage

+4.5V to +5.5V

Minimum Input Edge Rate (?V/?t)Data Input 50 mV/ns Enable Input

20 mV/ns Symbol Parameter

Min Typ Max Units V CC Conditions

V IH Input HIGH Voltage 2.0

Recognized HIGH Signal V IL Input LOW Voltage 0.8V Recognized LOW Signal

V CD Input Clamp Diode Voltage ?1.2

V Min I IN = ?18 mA (Non I/O Pins)V OH Output HIGH 2.5V Min I OH = ?3 mA, (A n , B n , AP AR, BP AR)Voltage

2.0

I OH = ?32 mA, (A n , B n , AP AR, BP AR)V OL Output LOW Voltage 0.55

V Min I OL = 64 mA, (A n , B n , AP AR, BP AR)V ID Input Leakage Test 4.75

V 0.0I ID = 1.9 μA, (Non-I/O Pins)All Other Pins Grounded

I IH Input HIGH Current 5μA Max V IN = 2.7V (Non-I/O Pins) (Note 4)V IN = V CC (Non-I/O Pins)I BVI Input HIGH Current 7μA Max V IN = 7.0V (Non-I/O Pins)Breakdown T est I BVIT Input HIGH Current 100

μA

Max

V IN = 5.5V (A n , B n , APAR, BPAR)

Breakdown T est (I/O)I IL

Input LOW Current

?5μA Max

V IN = 0.5V (Non-I/O Pins) (Note 4)V IN = 0.0V (Non-I/O Pins)

I IH + I OZH Output Leakage Current 50μA 0V–5.5V V OUT = 2.7V (A n , B n );

GAB and GBA = 2.0V

I IL + I OZL Output Leakage Current ?50

μA 0V–5.5V V OUT = 0.5V (A n , B n );

GAB and GBA = 2.0V

I OS Output Short-Circuit Current ?100

?275mA Max V OUT = 0V (A n , B n , AP AR, BP AR)I CEX Output HIGH Leakage Current 50μA Max V OUT = V CC (A n , B n , AP AR, BP AR)I ZZ Bus Drainage T est 100μA 0.0V V OUT = 5.5V (A n , B n , AP AR, BP AR);All Others GND I CCH Power Supply Current 250μA Max All Outputs HIGH

I CCL Power Supply Current 34mA Max All Outputs LOW, ERRA/B = HIGH (Note 5)I CCZ Power Supply Current 250μA Max Outputs 3-STA TE All Others at V CC or GND I CCT Additional I CC /Input 2.5mA Max V I = V CC ? 2.1V All Others at V CC or GND I CCD

Dynamic I CC :No Load

0.4

mA/MHz

Max

Outputs Open

(Note 4)

GAB or GBA = GND, LE = HIGH Non-I/O = GND or V CC

One bit toggling, 50% duty cycle

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74ABT899

DC Electrical Characteristics

(PLCC package)Note 6: Max number of outputs defined as (n). n ? 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Note 7: Max number of data inputs (n) switching. n ? 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD ), 0V to threshold (V IHD ).Guaranteed, but not tested.

Note 8: Max number of outputs defined as (n). n ? 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and PLCC Package)

Symbol Parameter

Min

Typ Max Units V CC Conditions C L = 50 pF, R L = 500?V OLP Quiet Output Maximum Dynamic V OL 0.8 1.1

V 5.0T A = 25°C (Note 6)V OLV Quiet Output Minimum Dynamic V OL

?1.3?0.8V 5.0T A = 25°C (Note 6)V OHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0V 5.0T A = 25°C (Note 8)V IHD Minimum HIGH Level Dynamic Input Voltage 2.2 1.8V 5.0T A = 25°C (Note 7)V ILD

Maximum LOW Level Dynamic Input Voltage

0.8

0.5V

5.0

T A = 25°C (Note 7)

Symbol

Parameter

T A = +25°C

T A = ?40°C to +85°C Units

V CC = +5.0V V CC = 4.5V–5.5V C L = 50 pF

C L = 50 pF Min

Typ Max Min

Max t PLH Propagation Delay 1.5 3.0 4.8 1.5 4.8ns t PHL A n , to B n

1.5 3.5 4.8 1.5 4.8t PLH Propagation Delay

2.5 5.99.2 2.59.2ns t PHL A n , B n to BP AR, AP AR 2.5 5.89.2 2.59.2t PLH Propagation Delay 2.5 5.48.5 2.58.5ns t PHL A n , B n to ERRA, ERRB 2.5 5.48.5 2.58.5t PLH Propagation Delay

1.5 3.7 6.0 1.5 6.0ns t PHL AP AR, BP AR to ERRA, ERRB 1.5 3.7 6.0 1.5 6.0t PLH Propagation Delay

2.0 4.4 6.9 2.0 6.9ns t PHL ODD/EVEN to APAR, BP AR 2.0 4.4 6.9 2.0 6.9t PLH Propagation Delay

1.8 4.0 6.0 1.8 6.0ns t PHL ODD/EVEN to ERRA, ERRB 1.8 4.0 6.0 1.8 6.0t PLH Propagation Delay 1.5 3.8 6.0 1.5 6.0ns t PHL SEL to AP AR, BP AR 1.5 3.8 6.0 1.5 6.0t PLH Propagation Delay 1.5 3.2 4.6 1.5 4.6ns t PHL LEA, LEB to B n , A n 1.5 3.2 4.6 1.5 4.6t PLH Propagation Delay

2.5 5.98.8 2.58.8ns t PHL LEA, LEB to BP AR, AP AR 2.5

5.7

8.8

2.5

8.8

Generate Mode t PLH Propagation Delay 1.5 3.6 5.1 1.5 5.1ns

t PHL LEA, LEB to BP AR, AP AR, 1.5

3.6

5.1

1.5

5.1

Feed Thru Mode t PLH Propagation Delay 1.6 5.48.4 1.68.4ns

t PHL LEA, LEB to ERRA, ERRB 1.6 5.48.4 1.68.4t PZH Output Enable Time 1.5 3.6 6.0 1.5 6.0ns t PZL GBA or GAB to A n , 1.5

3.4

6.0

1.5

6.0

AP AR or B n , BPAR t PHZ Output Disable Time 1.0 4.0 6.0 1.0 6.0ns

t PLZ GBA or GAB to A n , 1.0

3.3

6.0

1.0

6.0

AP AR or B n , BPAR t PLH t PHL

Propagation Delay

1.5 3.3 5.4 1.5 5.4ns

AP AR to BPAR, BPAR to AP AR

1.5

3.8

5.4

1.5

5.4

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74A B T 899

AC Electrical Characteristics

(SSOP Package)

AC Operating Requirements

Symbol

Parameter

T A = +25°C

T A = ?40°C to +85°C Units

V CC = +5.0V V CC = 4.5V–5.5V C L = 50 pF

C L = 50 pF Min

Typ Max Min

Max t PLH Propagation Delay 1.5 3.0 5.3 1.5 5.3ns t PHL A n , to B n

1.5 3.5 5.3 1.5 5.3t PLH Propagation Delay

2.5 5.99.9 2.59.9ns t PHL A n , B n to BP AR, AP AR 2.5 5.89.9 2.59.9t PLH Propagation Delay 2.5 5.49.4 2.59.4ns t PHL A n , B n to ERRA, ERRB 2.5 5.49.4 2.59.4t PLH Propagation Delay

1.5 3.7 6.5 1.5 6.5ns t PHL AP AR, BPAR to ERRA, ERRB 1.5 3.7 6.5 1.5 6.5t PLH Propagation Delay

2.0 4.47.4 2.07.4ns t PHL ODD/EVEN to AP AR, BP AR 2.0 4.47.4 2.07.4t PLH Propagation Delay

1.8 4.0 6.5 1.8 6.5ns t PHL ODD/EVEN to ERRA, ERRB 1.8 4.0 6.5 1.8 6.5t PLH Propagation Delay 1.5 3.8 6.5 1.5 6.5ns t PHL SEL to AP AR, BPAR 1.5 3.8 6.5 1.5 6.5t PLH Propagation Delay 1.5 3.2 5.1 1.5 5.1ns t PHL LEA, LEB to B n , A n 1.5 3.2 5.1 1.5 5.1t PLH Propagation Delay

2.5 5.99.2 2.59.2ns t PHL LEA, LEB to BP AR, AP AR 2.5

5.7

9.2

2.5

9.2

Generate Mode t PLH Propagation Delay 1.5 3.6 5.6 1.5 5.6ns

t PHL LEA, LEB to BP AR, AP AR, 1.5

3.6

5.6

1.5

5.6

Feed Thru Mode t PLH Propagation Delay 1.6 5.48.9 1.68.9ns

t PHL LEA, LEB to ERRA, ERRB 1.6 5.48.9 1.68.9t PZH Output Enable Time 1.5 3.6 6.5 1.5 6.5ns t PZL GBA or GAB to A n , 1.5

3.4

6.5

1.5

6.5

AP AR or B n , BPAR t PHZ Output Disable Time 1.0 4.0 6.5 1.0 6.5ns

t PLZ GBA or GAB to A n , 1.0

3.3

6.5

1.0

6.5

AP AR or B n , BPAR t PLH Propagation Delay

1.5 3.3 5.9 1.5 5.9ns

t PHL

AP AR to BPAR, BP AR to AP AR

1.5

3.8

5.9

1.5

5.9

Symbol

Parameter

T A = +25°C

T A = ?40°C to +85°C Units

V CC = +5.0V V CC = 4.5V–5.5V C L = 50 pF

C L = 50 pF

Min

Max

Min Max

t S (H)Setup Time, HIGH or LOW A n , 1.5 1.5ns t S (L)AP AR to LEA or B n , BP AR to LEB 1.5 1.5t H (H)Hold Time, HIGH or LOW A n , 1.0 1.0ns

t H (L)AP AR to LEA or B n , BP AR to LEB 1.0 1.0t W (H)

Pulse Width, HIGH 3.0

3.0

ns LEA or LEB

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74ABT899

Extended AC Electrical Characteristics

(SOIC and PLCC Package)

Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-itors in the standard AC load. This specification pertains to single output switching only.

Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load

Note 12: The 3-ST ATE delay time is dominated by the RC network (500?, 250 pF) on the output and has been excluded from the datasheet.Note 13: Not applicable for multiple output switching.

Symbol

Parameter

T A = +25°C T A = ?40°C to +85°C T A = ?40°C to +85°C Units

V CC = +5.0V

V CC = 4.5V–5.5V V CC = 4.5V–5.5V C L = 50 pF C L = 250 pF C L = 250 pF 9 Outputs Switching

1 Output Switching 9 Outputs Switching

(Note 9)

(Note 10)

(Note 11)Min

Typ Max Min Max Min Max

f TOGGLE Max Toggle Frequency 100

MHz

t PLH Propagation Delay 1.5 6.2 2.07.2 2.59.5ns t PHL A n to B n

1.5 6.2

2.07.2 2.59.5t PLH Propagation Delay 1.5 6.8 2.08.0 2.510.0ns t PHL APAR to BP AR 1.5 6.8 2.08.0 2.010.0t PLH Propagation Delay 2.510.0

3.012.5 3.513.5ns t PHL A n , B n to BP AR, AP AR 2.5

10.0

3.012.5 3.5

13.5

t PLH Propagation Delay (Note 13) 3.012.0(Note 13)

ns t PHL A n , B n to ERRA, ERRB 3.012.0t PLH Propagation Delay

(Note 13) 2.09.0(Note 13)

t PHL APAR, BPAR to ERRA, ERRB 2.09.0t PLH Propagation Delay

(Note 13) 2.59.9(Note 13)

t PHL ODD/EVEN to AP AR, BP AR 2.59.9t PLH Propagation Delay

(Note 13) 2.08.8(Note 13)

t PHL ODD/EVEN to ERRA, ERRB 2.08.8t PLH Propagation Delay (Note 13)

2.09.5(Note 13)

t PHL SEL to APAR, BPAR 2.0

9.5t PLH Propagation Delay 1.5 5.7 2.07.9 2.510.0ns

t PHL LEA, LEB to B n , A n 1.5 5.7 2.07.9 2.510.0t PLH Propagation Delay 1.59.5 2.012.0 2.513.0ns t PHL LEA, LEB to BP AR, APAR 1.5

9.5

2.012.0 2.5

13.0

t PLH Propagation Delay (Note 13)

2.011.5(Note 13)

ns t PHL LEA, LEB to ERRA, ERRB 2.0

11.5t PZH Output enable time 1.57.0 2.08.5 2.510.5t PZL GBA or GAB to A n , 1.57.0 2.0

8.5

2.5

10.5

APAR or B n , BP AR t PHZ Output disable time 1.0 6.5t PLZ

GBA or GAB to A n , 1.0

6.5

(Note 12)

APAR or B n , BP AR

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74A B T 899

Extended AC Electrical Characteristics

(SSOP Package)

Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-itors in the standard AC load. This specification pertains to single output switching only.

Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load

Note 17: The 3-ST ATE delay time is dominated by the RC network (500?, 250 pF) on the output and has been excluded from the datasheet.Note 18: Not applicable for multiple output switching.

Symbol

Parameter

T A = +25°C T A = ?40°C to +85°C T A = ?40°C to +85°C Units

V CC = +5.0V

V CC = 4.5V–5.5V V CC = 4.5V–5.5V C L = 50 pF C L = 250 pF C L = 250 pF 9 Outputs Switching

1 Output Switching 9 Outputs Switching

(Note 14)

(Note 15)

(Note 16)Min

Typ Max Min Max Min Max

f TOGGLE Max Toggle Frequency 100

MHz

t PLH Propagation Delay 1.5 6.7 2.07.7 2.510.1ns t PHL A n to B n

1.5 6.7

2.07.7 2.510.1t PLH Propagation Delay 1.57.3 2.08.5 2.510.6ns t PHL APAR to BP AR 1.57.3 2.08.5 2.010.6t PLH Propagation Delay 2.510.7

3.013.2 3.51

4.3ns t PHL A n , B n to BP AR, APAR 2.5

10.7

3.013.2 3.5

14.3

t PLH Propagation Delay (Note 18) 3.012.9(Note 18)

ns t PHL A n , B n to ERRA, ERRB 3.012.9t PLH Propagation Delay

(Note 18) 2.09.5(Note 18)

t PHL APAR, BP AR to ERRA, ERRB 2.09.5t PLH Propagation Delay

(Note 18) 2.510.4(Note 18)

t PHL ODD/EVEN to AP AR, BP AR 2.510.4t PLH Propagation Delay

(Note 18) 2.09.3(Note 18)

t PHL ODD/EVEN to ERRA, ERRB 2.09.3t PLH Propagation Delay (Note 18)

2.010.0(Note 18)

t PHL SEL to APAR, BP AR 2.0

10.0t PLH Propagation Delay 1.5 6.2 2.08.4 2.510.6ns

t PHL LEA, LEB to B n , A n 1.5 6.2 2.08.4 2.510.6t PLH Propagation Delay 1.510.0 2.012.5 2.513.6ns t PHL LEA, LEB to BPAR, APAR 1.5

10.0

2.012.5 2.5

13.6

t PLH Propagation Delay (Note 18)

2.012.0(Note 18)

ns t PHL LEA, LEB to ERRA, ERRB 2.0

12.0t PZH Output enable time 1.57.5 2.09.0 2.511.1t PZL GBA or GAB to A n , 1.57.5 2.0

9.0

2.5

11.1

APAR or B n , BP AR t PHZ Output disable time 1.07.0t PLZ

GBA or GAB to A n , 1.0

7.0

(Note 17)

APAR or B n , BP AR

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74ABT899

Skew

(PLCC package) (Note 2)

Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.The specification applies to any outputs switching HIGH to LOW (t OSHL ), LOW to HIGH (t OSLH ), or any combination switching LOW to HIGH and/or HIGH to LOW (t OST ). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., A n to B n separate from LEA to A n .

Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and V CC ) from device to device. This specification is guaranteed but not tested.

Capacitance

Note 24: C I/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012.

Symbol

Parameter

T A = ?40°C to +85°C T A = ?40°C to +85°C Units

V CC = 4.5V–5.5V

V CC = 4.5V–5.5V C L = 50 pF C L = 250 pF 9 Outputs Switching

9 Outputs Switching

(Note 19)(Note 20)Max

Max t OSHL Pin to Pin Skew 1.0

2.0

ns (Note 21)HL Transitions t OSLH Pin to Pin Skew 1.1

2.1

(Note 21)LH Transitions t PS Duty Cycle 2.0

3.5

(Note 22)LH–HL Skew t OST Pin to Pin Skew 2.0

3.5

(Note 21)LH/HL T ransitions t PV Device to Device Skew 3.0

4.0

(Note 23)

LH/HL T ransitions

Symbol

Parameter

Typ Units Conditions T A = 25°C

C IN

Input Pin Capacitance 5.0pF V CC = 0V C I/O (Note 24)

Output Capacitance

11.0

V CC = 5.0V

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74A B T 899

AC Path

A n , APAR →

B n , BPAR (B n , BPAR → A n , APAR)

FIGURE 1.

A n → BPAR (

B n → APAR)

FIGURE 2.

A n → ERRA (

B n → ERRB)

FIGURE 3.

O/E → ERRA O/E → ERRB

FIGURE 4.

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74ABT899

AC Path

(Continued)

O/E → BPAR (O/E → APAR)

FIGURE 5.

APAR → ERRA (BPAR → ERRB)

FIGURE 6.

FIGURE 7.

ZH, HZ

FIGURE 8.

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74A B T 899

AC Path

(Continued)

ZL, LZ

FIGURE 9.

SEL → BPAR (SEL → APAR)

FIGURE 10.

LEA → BPAR, B[0:7](LEB → APAR, A[0:7])

FIGURE 11.

TS(H), TH(H)LEA → APAR, A[0:7](LEB → BPAR, B[0:7])

FIGURE 12.

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74ABT899

AC Path (Continued)

TS(L), TH(L)LEA → APAR, A[0:7](LEB → BPAR, B[0:7])

FIGURE 13.

FIGURE 14.

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74A B T 899

AC Loading

*Includes jig and probe capacitance

FIGURE 15. Standard AC Test Load

V M = 1.5V FIGURE 16. Input Pulse Requirements

FIGURE 17. Test Input Signal Requirements

AC Waveforms

FIGURE 18. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions FIGURE 19. Propagation Delay,

Pulse Width Waveforms FIGURE 20. 3-STATE Output HIGH and LOW Enable and Disable Times

FIGURE 21. Setup Time, Hold Time and Recovery Time Waveforms

Amplitude Rep. Rate t W t r t f 3.0V

1 MHz

500 ns

2.5 ns

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74ABT899

Physical Dimensions inches (millimeters) unless otherwise noted

28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body

Package Number M28B

28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA28

F a irch ild d o e s n o t a ssu m e a n y re spo n sib ility fo r u se o f a n y circu itry de scrib e d , n o circu it pa ten t lice nse s a re im p lie d a nd F a irch ild re se rv e s the rig h t a t a n y tim e w ith ou t n o tice to cha n g e sa id circu itry an d sp e cifica tio n s.

74A B T 899 9-B i t L a t c h a b l e T r a n s c e i v e r w i t h P a r i t y G e n e r a t o r /C h e c k e r

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.

2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or https://www.wendangku.net/doc/2955424.html, Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square

Package Number V28A