DM9000A-DS-F01-051006
DM9000A
Ethernet Controller with General Processor Interface
Final 1
Version: DM9000A-17-DS-F01
May 10, 2006
DA VICOM Semiconductor, Inc.
DM9000A
Ethernet Controller with General Processor Interface
Final
Version : DM9000A-DS-F01
May 10, 2006
DM9000A
Ethernet Controller with General Processor Interface
Final 2
Version: DM9000A-17-DS-F01
May 10, 2006
Content
1. General Description............................................................................................................................................................6 2. Block Diagram....................................................................................................................................................................6 3. Features...............................................................................................................................................................................7 4. Pin Configuration...............................................................................................................................................................8 4.1 (16-bit mode).................................................................................................................................................................8 4.2 (8-bit mode)...................................................................................................................................................................9 5. Pin Description..................................................................................................................................................................10 5.1 Processor Interface......................................................................................................................................................10 5.1.1 8-bit mode pins..........................................................................................................................................................10 5.2 EEPROM Interface.......................................................................................................................................................11 5.3 Clock Interface..............................................................................................................................................................11 5.4 LED Interface...............................................................................................................................................................11 5.5 10/100 PHY/Fiber.........................................................................................................................................................11 5.6 Miscellaneous..............................................................................................................................................................12 5.7 Power Pins...................................................................................................................................................................12 5.8 strap pins table ............................................................................................................................................................12 6. Vendor Control and Status Register Set.........................................................................................................................13 6.1 Network Control Register (00H)..................................................................................................................................14 6.2 Network Status Register (01H)....................................................................................................................................15 6.3 TX Control Register (02H)...........................................................................................................................................15 6.4 TX Status Register I ( 03H ) for packet index I............................................................................................................15 6.5 TX Status Register II ( 04H ) for packet index I I.........................................................................................................16 6.6 RX Control Register ( 05H )........................................................................................................................................16 6.7 RX Status Register ( 06H )...........................................................................................................................................16 6.8 Receive Overflow Counter Register ( 07H )................................................................................................................17 6.9 Back Pressure Threshold Register (08H).....................................................................................................................17 6.10 Flow Control Threshold Register ( 09H )..................................................................................................................17 6.11 RX/TX Flow Control Register ( 0AH ).......................................................................................................................19 6.12 EEPROM & PHY Control Register ( 0BH )...............................................................................................................19 6.13 EEPROM & PHY Address Register ( 0CH )..............................................................................................................19 6.14 EEPROM & PHY Data Register (EE_PHY_L 0DH EE_PHY_H 0EH). (19)
DM9000A
Ethernet Controller with General Processor Interface
Final 3
Version: DM9000A-17-DS-F01
May 10, 2006
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode)....................................................................................................20 6.16 Physical Address Register ( 10H~15H )....................................................................................................................20 6.17 Multicast Address Register ( 16H~1DH )..................................................................................................................20 6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H)....................20 6.19 General purpose Register ( 1FH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H)...................................22 6.20 TX SRAM Read Pointer Address Register (22H~23H)..............................................................................................22 6.21 RX SRAM Write Pointer Address Register (24H~25H)..............................................................................................22 6.22 Vendor ID Register (28H~29H).................................................................................................................................22 6.23 Product ID Register (2AH~2BH)...............................................................................................................................22 6.24 Chip Revision Register (2CH)...................................................................................................................................22 6.25 Transmit Control Register 2 ( 2DH ).........................................................................................................................22 6.26 Operation Test Control Register ( 2EH )...................................................................................................................23 6.27 Special Mode Control Register ( 2FH ).....................................................................................................................23 6.28 Early Transmit Control/Status Register ( 30H ).........................................................................................................24 6.29 Check Sum Control Register ( 31H )..........................................................................................................................24 6.30 Receive Check Sum Status Register ( 32H )...............................................................................................................24 6.31 MII PHY Address Register ( 33H ).............................................................................................................................25 6.32 LED Pin Control Register ( 34H ).............................................................................................................................25 6.33 Processor Bus Control Register ( 38H )....................................................................................................................25 6.34 INT Pin Control Register ( 39H )...............................................................................................................................26 6.35 System Clock Turn ON Control Register ( 50H ).......................................................................................................26 6.36 Resume System Clock Control Register ( 51H ).........................................................................................................26 6.37 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H).............................................26 6.38 Memory Data Read Command without Address Increment Register (F1H)..............................................................26 6.39 Memory Data Read Command with Address Increment Register (F2H)...................................................................26 6.40 Memory Data Read_address Register (F4H~F5H)...................................................................................................26 6.41 Memory Data Write Command without Address Increment Register (F6H)..............................................................26 6.42 Memory data write command with address increment Register (F8H).....................................................................27 6.43 Memory data write_address Register (F AH~FBH)....................................................................................................27 6.44 TX Packet Length Register (FCH~FDH)...................................................................................................................27 6.45 Interrupt Status Register (FEH).................................................................................................................................27 6.46 Interrupt Mask Register (FFH). (27)
7. EEPROM Format.............................................................................................................................................................28 8. PHY Register Description (29)
DM9000A
Ethernet Controller with General Processor Interface
Final 4
Version: DM9000A-17-DS-F01
May 10, 2006
8.1 Basic Mode Control Register (BMCR) - 00.................................................................................................................30 8.2 Basic Mode Status Register (BMSR) - 01.....................................................................................................................31 8.3 PHY ID Identifier Register #1 (PHYID1) - 02.............................................................................................................33 8.4 PHY ID Identifier Register #2 (PHYID2) - 03.............................................................................................................33 8.5 Auto-negotiation Advertisement Register (ANAR) - 04................................................................................................34 8.6 Auto-negotiation Link Partner Ability Register (ANLP AR) – 05..................................................................................35 8.7 Auto-negotiation Expansion Register (ANER)- 06.......................................................................................................36 8.8 DAVICOM Specified Configuration Register (DSCR) - 16.........................................................................................36 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17......................................................................38 8.10 10BASE-T Configuration/Status (10BTCSR) - 18......................................................................................................39 8.11 Power Down Control Register (PWDOR) - 19..........................................................................................................40 8.12 (Specified config) Register – 20 (40)
9. Functional Description.....................................................................................................................................................42 9.1 Host Interface..............................................................................................................................................................42 9.2 Direct Memory Access Control....................................................................................................................................42 9.3 Packet Transmission....................................................................................................................................................42 9.4 Packet Reception..........................................................................................................................................................42 9.5 100Base-TX Operation................................................................................................................................................43 9.5.1 4B5B Encoder......................................................................................................................................................43 9.5.2 Scrambler.............................................................................................................................................................43 9.5.3 Parallel to Serial Converter..................................................................................................................................43 9.5.4 NRZ to NRZI Encoder.........................................................................................................................................43 9.5.5 MLT-3 Converter..................................................................................................................................................43 9.5.6 MLT-3 Driver.......................................................................................................................................................43 9.5.7 4B5B Code Group................................................................................................................................................44 9.6 100Base-TX Receiver...................................................................................................................................................45 9.6.1 Signal Detect........................................................................................................................................................45 9.6.2 Adaptive Equalization..........................................................................................................................................45 9.6.3 MLT-3 to NRZI Decoder......................................................................................................................................45 9.6.4 Clock Recovery Module......................................................................................................................................45 9.6.5 NRZI to NRZ.......................................................................................................................................................45 9.6.6 Serial to Parallel...................................................................................................................................................45 9.6.7 Descrambler.........................................................................................................................................................45 9.6.8 Code Group Alignment........................................................................................................................................46 9.6.9 4B5B Decoder......................................................................................................................................................46 9.7 10Base-T Operation.....................................................................................................................................................46 9.8 Collision Detection......................................................................................................................................................46 9.9 Carrier Sense...............................................................................................................................................................46 9.10 Auto-Negotiation........................................................................................................................................................46 9.11 Power Reduced Mode................................................................................................................................................47 9.11.1 Power Down Mode (47)
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
9.11.2 Reduced Transmit Power Mode (47)
10. DC and AC Electrical Characteristics..........................................................................................................................48 10.1 Absolute Maximum Ratings ( 25°C )..........................................................................................................................48 10.1.1 Operating Conditions.........................................................................................................................................48 10.2 DC Electrical Characteristics (VDD = 3.3V)............................................................................................................48 10.3 AC Electrical Characteristics & Timing Waveforms..................................................................................................49 10.3.1 TP Interface........................................................................................................................................................49 10.3.2 Oscillator/Crystal Timing...................................................................................................................................49 10.3.3 Processor I/O Read Timing................................................................................................................................49 10.3.4 Processor I/O Write Timing ...............................................................................................................................50 10.3.5 EEPROM Interface Timing................................................................................................................................51 11. Application Notes............................................................................................................................................................52 11.1 Network Interface Signal Routing..............................................................................................................................52 11.2 10Base-T/100Base-TX Auto MDIX Application.........................................................................................................52 11.3 10Base-T/100Base-TX ( Non Auto MDIX Transformer Application )........................................................................53 11.4 Power Decoupling Capacitors...................................................................................................................................54 11.5 Ground Plane Layout.................................................................................................................................................55 11.6 Power Plane Partitioning..........................................................................................................................................56 11.7 Magnetics Selection Guide.........................................................................................................................................57 11.8 Crystal Selection Guide..............................................................................................................................................57 12. Package Information......................................................................................................................................................58 13. Ordering Information. (59)
DM9000A
Ethernet Controller with General Processor Interface
Final 6
Version: DM9000A-17-DS-F01
May 10, 2006
1. General Description
The DM9000A is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM. It is designed with low power and high performance process that support 3.3V with 5V IO tolerance.
The DM9000A supports 8-bit and 16-bit data interfaces to internal memory accesses for various
processors. The PHY of the DM9000A can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX. It is fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000A to take the maximum advantage of its abilities. The DM9000A also supports IEEE 802.3x full- duplex flow control..
2. Block Diagram
DM9000A
Ethernet Controller with General Processor Interface
Final 7
Version: DM9000A-17-DS-F01
May 10, 2006
3. Features
48-pin LQFP
Supports processor interface: byte/word of I/O
command to internal memory data operation Integrated 10/100M transceiver
with HP Auto-MDIX Supports back pressure mode for half-duplex mode flow control IEEE802.3x flow control for full-duplex mode Supports wakeup frame, link status change and
magic packet events for remote wake up Integrated 16K Byte SRAM Build in 3.3V to 2.5V regulator
Supports early
Transmit Supports IP/TCP/UDP checksum generation and
checking
Supports automatically load vendor ID and product ID from EEPROM Optional EEPROM configuration Very low power consumption mode:
Power reduced mode (cable detection) Power down mode
Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
Compatible with 3.3V and 5.0V tolerant I/O
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
4. Pin Configuration
4.1 (16-bit mode)
B G R E S
T X V D D 25
R X +
T X -
R X -
R X G N D
T X G N D T X +
R X V D D 25
S D 7
S D 6S D 5
CS#LED2LED1TEST PWRST#VDD X2X1GND SD RXGND BGGND
EEDIO SD4
SD3GND SD2SD1SD0EECS SD15VDD EECK SD14S D 13
S D 9
S D 11S D 12S D 10
V D D
S D 8
C M D
I N T
G N D
I O R #
I O W #
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Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
4.2 (8-bit mode)
B G R E S
T X V D D 25
R X +
T X -
R X -
R X G N D
T X G N D
T X +
R X V D D 25
S D 7
S D 6
S D 5
CS#LED2LED1TEST PWRST#VDD X2X1GND SD RXGND BGGND
EEDIO SD4
SD3GND SD2SD1SD0EECS WAKE VDD EECK LED3G P 6
G P 2
G P 4G P 5G P 3
V D D
G P 1
C M D
I N T
G N D I O R #
I O W #
DM9000A
Ethernet Controller with General Processor Interface
Final 10
Version: DM9000A-17-DS-F01
May 10, 2006
5. Pin Description
I = Input O = Output I/O = Input/Output O/D = Open Drain P = Power
# = asserted low PD = internal pull-low about 60K
5.1 Processor Interface
Pin No.
Pin Name
Type
Description
35 IOR# I,PD Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail 36 IOW# I,PD Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail 37 CS# I,PD Chip Select
A default low active signal used to select the DM9000A. Its polarity can be
modified by EEPROM setting. See the EEPROM content description for detail.
32 CMD I,PD Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is INDEX port 34 INT O,PD
Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or by strap pin EECK. See the EEPROM content description for detail
18,17,16, 14,13,12, 11,10 SD0~7 I/O,PD
Processor Data Bus bit 0~7
31,29,28, 27,26,25, 24,22
SD8~15 I/O,PD
Processor Data Bus bit 8~15
In 16-bit mode, these pins act as the processor data bus bit 8~15;
When EECS pin is pulled high , they have other definitions. See 8-bit mode pin description for details.
5.1.1 8-bit mode pins
Pin No.
Pin Name
Type
Description
22 WAKE O,PD
Issue a wake up signal when wake up event happens 24 LED3 O,PD
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY In LED mode 0, Its low output indicates that the internal PHY is operated in 10M mode, or it is floating for the 100M mode of the internal PHY Note: LED mode is defined in EEPROM setting. 25,26,27 GP6~4 O,PD
General Purpose output pins:
These pins are output only for general purpose that are configured by register 1Fh.
GP6 pin also act as trap pin for the INT output type.
When GP6 is pulled high, the INT is Open-Drain output type; Otherwise it is force output type. 28,29,31 GP3,GP2,GP1 I/O
General I/O Ports
Registers GPCR and GPR can program these pins
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
These pins are input ports at default.
5.2 EEPROM Interface
Pin No.
Pin Name
Type
Description
19 EEDIO I/O,PD
IO Data to EEPROM 20 EECK O,PD
Clock to EEPROM This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT pin is high active
21 EECS O,PD
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data bus
width. When it is pulled high, the memory access bus is 8-bit; Otherwise it is 16-bit. 5.3 Clock Interface
Pin No.
Pin Name
Type
Description
43 X2 O Crystal 25MHz Out 44 X1
I
Crystal 25MHz In
5.4 LED Interface
Pin No.
Pin Name
Type
Description
39 LED1 O Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY .
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit mode.
38 LED2 O Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM setting in 16-bit mode.
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
Type
Description
46 SD I Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels 48 BGGND P
Bandgap Ground 1 BGRES I/O Bandgap Pin 2 RXVDD25 P
2.5V power output for TP RX 9 TXVDD25 P 2.5V power output for TP TX 3 RX+ I/O
TP RX Input
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01 May 10, 2006
4 RX- I/O TP RX Input 5,47 RXGND P
RX Ground 6 TXGND P
TX Ground 7 TX+ I/O TP TX Output 8 TX- I/O TP TX Output 5.6 Miscellaneous
Pin No.
Pin Name
Type
Description
41 TEST I
Operation Mode
Force to ground in normal application 40 PWRST# I Power on Reset
Active low signal to initiate the DM9000A
The DM9000A is ready after 5us when this pin deasserted
5.7 Power Pins
Pin No.
Pin Name
Type
Description
23,30,42 VDD P
Digital VDD 3.3V power input 15,33,45 GND P
Digital GND 5.8 strap pins table
1: pull-high 1K~10K, 0: floating (default)
Pin No.
Pin Name
Description
20 EECK Polarity of INT
1: INT pin low active;
0: INT pin high active 21
EECS
DATA Bus Width
1: 8-bit 0: 16-bit
22 WAKE
Polarity of CS# in 8-bit mode 1: CS# pin active high 0: CS# pin active low
25 GP6
INT output type in 8-bit mode 1: Open-Drain 0: force mode
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Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
6. Vendor Control and Status Register Set
The DM9000A implements several control and status
registers, which can be accessed by the host. These CSRs are byte aligned. All CSRs are set to their default values by hardware or software reset unless they are specified
Register Description Offset
Default value
after reset
NCR
Network Control Register 00H 00H NSR Network Status Register 01H 00H TCR TX Control Register 02H 00H TSR I TX Status Register I 03H 00H TSR II TX Status Register II 04H 00H RCR RX Control Register 05H 00H RSR RX Status Register
06H 00H ROCR Receive Overflow Counter Register 07H 00H BPTR Back Pressure Threshold Register 08H 37H FCTR Flow Control Threshold Register 09H 38H FCR RX Flow Control Register
0AH 00H EPCR EEPROM & PHY Control Register 0BH 00H EPAR EEPROM & PHY Address Register
0CH 40H EPDRL EEPROM & PHY Low Byte Data Register 0DH XXH EPDRH EEPROM & PHY High Byte Data Register 0EH XXH WCR Wake Up Control Register (in 8-bit mode) 0FH 00H PAR
Physical Address Register
10H-15H Determined by
EEPROM
MAR Multicast Address Register 16H-1DH XXH GPCR General Purpose Control Register (in 8-bit mode) 1EH 01H GPR General Purpose Register 1FH XXH TRPAL TX SRAM Read Pointer Address Low Byte 22H 00H TRPAH TX SRAM Read Pointer Address High Byte 23H 00H RWPAL RX SRAM Write Pointer Address Low Byte 24H 00H RWPAH RX SRAM Write Pointer Address High Byte 25H 0CH VID Vendor ID 28H-29H 0A46H PID Product ID 2AH-2BH 9000H CHIPR CHIP Revision 2CH 19H TCR2 TX Control Register 2 2DH 00H OCR Operation Control Register 2EH 00H SMCR Special Mode Control Register 2FH 00H ETXCSR Early Transmit Control/Status Register 30H 00H TCSCR Transmit Check Sum Control Register 31H 00H RCSCSR Receive Check Sum Control Status Register 32H 00H MPAR MII PHY Address Register 33H 00H LEDCR LED Pin Control Register 34H 00H BUSCR Processor Bus Control Register 38H 61H INTCR INT Pin Control Register 39H 00H SCCR System Clock Turn ON Control Register
50H 00H
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01 May 10, 2006
RSCCR Resume System Clock Control Register 51H XXH
MRCMDX Memory Data Pre-Fetch Read Command Without Address
Increment Register
F0H XXH MRCMDX1 Memory Data Read Command With Address Increment
Register
F1H XXH MRCMD Memory Data Read Command With Address Increment
Register
F2H XXH MRRL Memory Data Read_ address Register Low Byte F4H 00H MRRH Memory Data Read_ address Register High Byte
F5H 00H
MWCMDX Memory Data Write Command Without Address Increment
Register
F6H XXH MWCMD Memory Data Write Command With Address Increment
Register
F8H XXH MWRL Memory Data Write_ address Register Low Byte FAH 00H MWRH Memory Data Write _ address Register High Byte FBH 00H TXPLL TX Packet Length Low Byte Register FCH XXH TXPLH TX Packet Length High Byte Register FDH
XXH
ISR Interrupt Status Register FEH 00H IMR Interrupt Mask Register FFH
00H
Key to Default
In the register description that follows, the default column takes the form:
RW/C1=Read/Write and Cleared by write 1 WO = Write only
Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access.
6.1 Network Control Register (00H) Bit Name Default Description 7 RESERVED P0,RW Reserved
6 WAKEEN
P0,RW When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5 RESERVED 0,RO Reserved 4 FCOL PS0,RW Force Collision Mode, used for testing 3 FDX PS0,RO Full-Duplex Mode of the internal PHY.
2:1 LBK
PS00, RW
Loopback Mode Bit 2 1
0 0 Normal
0 1 MAC Internal loopback 1 0 Internal PHY 100M mode digital loopback 1 1 (Reserved)
0 RST P0,RW Software reset and auto clear after 10us
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Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01
May 10, 2006
6.2 Network Status Register (01H)
Bit Name Default Description
7 SPEED X,RO
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6 LINKST X,RO Link Status 0:link failed 1:link OK,
5 WAKEST
P0, RW/C1 Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode)
This bit will not be affected after software reset
4 RESERVED 0,RO Reserved
3 TX2END
PS0, RW/C1 TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2 2 TX1END
PS0, RW/C1 TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
1 RXOV PS0,RO RX FIFO Overflow 0 RESERVED 0,RO Reserved
6.3 TX Control Register (02H)
Bit Name Default Description 7 RESERVED 0,RO Reserved
6 TJDIS PS0,RW Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is
Enable
5 EXCECM PS0,RW
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
4 PAD_DIS2 PS0,RW PAD Appends Disable for Packet Index 2 3 CRC_DIS2 PS0,RW CRC Appends Disable for Packet Index 2 2 PAD_DIS1 PS0,RW PAD Appends Disable for Packet Index 1 1 CRC_DIS1 PS0,RW CRC Appends Disable for Packet Index 1 0 TXREQ PS0,RW TX Request. Auto clears after sending completely
6.4 TX Status Register I ( 03H ) for packet index I Bit Name Default Description
7 TJTO PS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted 6 LC PS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode 5 NC PS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode 4 LC PS0,RO
Late Collision
It is set when a collision occurs after the collision window of 64 bytes 3 COL PS0,RO
Collision Packet
It is set to indicate that the collision occurs during transmission 2 EC PS0,RO
Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01 May 10, 2006
1:0 RESERVED 0,RO Reserved
6.5 TX Status Register II ( 04H ) for packet index I I Bit Name Default Description
7 TJTO PS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted 6 LC PS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal loopback mode 5 NC PS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal loopback mode 4 LC PS0,RO
Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3 COL PS0,RO Collision packet, collision occurs during transmission
2 EC PS0,RO
Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0 RESERVED 0,RO Reserved
6.6 RX Control Register ( 05H )
Bit Name Default Description 7 RESERVED PS0,RW Reserved
6
WTDIS PS0,RW Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled 5 DIS_LONG PS0,RW
Discard Long Packet
Packet length is over 1522byte
4 DIS_CRC PS0,RW Discard CRC Error Packet 3 ALL PS0,RW Pass All Multicast 2 RUNT PS0,RW Pass Runt Packet 1 PRMSC PS0,RW Promiscuous Mode 0 RXEN PS0,RW RX Enable
6.7 RX Status Register ( 06H ) Bit Name Default Description
7 RF PS0,RO
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes 6 MF PS0,RO
Multicast Frame
It is set to indicate that the received frame has a multicast address 5 LCS PS0,RO
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception 4 RWTO PS0,RO
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes 3 PLE PS0,RO
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception 2 AE PS0,RO
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
DM9000A
Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01 May 10, 2006
1 CE PS0,RO
CRC Error
It is set to indicate that the received frame ends with a CRC error 0 FOE PS0,RO
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H ) Bit Name Default Description
7 RXFU PS0,R/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition 6:0 ROC PS0,R/C
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.9 Back Pressure Threshold Register (08H) Bit Name Default Description
7:4 BPHW PS3, RW
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold value
The default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
3:0 JPT PS7, RW
Jam Pattern Time. Default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us 0 1 1 0 150us
0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us
6.10 Flow Control Threshold Register ( 09H ) Bit Name Default Description
7:4 HWOT PS3, RW RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space. The
default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
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Ethernet Controller with General Processor Interface
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Version: DM9000A-17-DS-F01 May 10, 2006
3:0 LWOT PS8, RW
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SRAM free space is larger than this value. This pause packet is enabled after the high water pause packet is
transmitted. The default SRAM free space is 8K-byte. Please do not exceed SRAM size
(1 unit=1K bytes)
DM9000A
Ethernet Controller with General Processor Interface
Final 19
Version: DM9000A-17-DS-F01
May 10, 2006
6.11 RX/TX Flow Control Register ( 0AH ) Bit Name Default Description
7 TXP0 PS0,RW TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h 6 TXPF PS0,RW TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5 TXPEN PS0,RW
Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control 4 BKPA PS0,RW Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW of register 8. 3 BKPM PS0,RW Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW of register 8.
2 RXPS PS0,R/C RX Pause Packet Status, latch and read clearly 1 RXPCS PS0,RO RX Pause Packet Current Status
0 FLCE PS0,RW
Flow Control Enable
Set to enable the flow control mode (i.e. can disable DM9000A TX function)
6.12 EEPROM & PHY Control Register ( 0BH ) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 REEP P0,RW Reload EEPROM. Driver needs to clear it up after the operation completes 4 WEP P0,RW Write EEPROM Enable
3 EPOS P0,RW
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2 ERPRR P0,RW
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1 ERPRW P0,RW
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0 ERRE P0,RO
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.13 EEPROM & PHY Address Register ( 0CH ) Bit Name Default Description
7:6 PHY_ADR P01,RW
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 in
application.
5:0 EROA P0,RW EEPROM Word Address or PHY Register Number.
6.14 EEPROM & PHY Data Register (EE_PHY_L 0DH EE_PHY_H 0EH) Bit Name Default Description
7:0 EE_PHY_L P0,RW
EEPROM or PHY Low Byte Data
The low-byte data read from or write to EEPROM or PHY. 7:0 EE_PHY_H P0,RW
EEPROM or PHY High Byte Data
The high-byte data read from or write to EEPROM or PHY.
DM9000A
Ethernet Controller with General Processor Interface
Final 20
Version: DM9000A-17-DS-F01
May 10, 2006
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode) Bit Name Type Description 7:6 RESERVED 0,RO Reserved
5 LINKEN P0,RW
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4 SAMPLEEN P0,RW
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset 3 MAGICEN P0,RW
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2 LINKST P0,RO
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1 SAMPLEST P0,RO
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0 MAGICST P0,RO
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H ) Bit Name Default Description
7:0 PAB5 E,RW Physical Address Byte 5 (15H) 7:0 PAB4 E,RW Physical Address Byte 4 (14H) 7:0 PAB3 E,RW Physical Address Byte 3 (13H) 7:0 PAB2 E,RW Physical Address Byte 2 (12H) 7:0 PAB1 E,RW Physical Address Byte 1 (11H) 7:0 PAB0 E,RW Physical Address Byte 0 (10H)
6.17 Multicast Address Register ( 16H~1DH ) Bit Name Default Description 7:0 MAB7 X,RW Multicast Address Byte 7 (1DH) 7:0 MAB6 X,RW Multicast Address Byte 6 (1CH) 7:0 MAB5 X,RW Multicast Address Byte 5 (1BH) 7:0 MAB4 X,RW Multicast Address Byte 4 (1AH) 7:0 MAB3 X,RW Multicast Address Byte 3 (19H) 7:0 MAB2 X,RW Multicast Address Byte 2 (18H) 7:0 MAB1 X,RW Multicast Address Byte 1 (17H) 7:0 MAB0 X,RW Multicast Address Byte 0 (16H)
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H) Bit Name Default Description 7 RESERVED PH0,RO Reserved
6:4 GPC64 P,
111,RO
General Purpose Control 6~4
Define the input/output direction of pins GP6~4 respectively.
These bits are all forced to “1”s, so pins GP6~4 are output only.