Gate Oxide Leakage and Delay Tradeoffs for DualìóüCircuits
Gate Oxide Leakage and Delay Tradeoffs for Dual Circuits Anup Kumar Sultania,Dennis Sylvester,and Sachin S.Sapatnekar
Calypto Design Systems,Inc.,Santa Clara,CA95054.
Department of EECS,University of Michigan,Ann Arbor,MI48109.
Department of ECE,University of Minnesota,Minneapolis,MN55455.
Abstract—Gate oxide tunneling current()is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness()is below15?.Increasing the value of reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible values to each transistor.In this paper,we propose an algorithm for dual assignment to optimize the total leakage power under delay constraints,and generate a leakage/delay tradeoff curve.As compared to the case where all transistors are set to low,our approach achieves an average leakage reduction of86%under 100nm models and81%under70nm models.We also propose a transistor and pin reordering technique that has minimal layout impact to further reduce the total leakage current up to12%and up to27%without incurring any delay penalty.
I.INTRODUCTION
Leakage current is a primary concern for low power,high performance digital CMOS circuits for portable applications, and industry trends show that leakage will be roughly50% of the total power in future technologies.New leakage mech-anisms,such as tunneling across thin gate oxides,leading to gate oxide leakage current(),come into play at the90nm technology and remain a daunting challenge for a number of technology nodes.
The International Technological Roadmap for Semiconduc-tors(ITRS)[1]predicts that physical oxide thickness() values of7–12?will be required for high performance CMOS circuits by2006,and quantum effects that cause tunneling will play a dominant role in such ultra-thin oxide devices. The probability of electron tunneling is a strong function of the barrier height(i.e.,the voltage drop across gate oxide)and the barrier thickness,which is simply,and a small change in can have a tremendous impact on.For example, in MOS devices with SiO gate oxides,a difference in of only2?can result in an order of magnitude increase in [2],so that reducing from18?to12?increases
by approximately1000.1Moreover,the other component of leakage,subthreshold leakage(),forms a reducing fraction of the total leakage as is reduced,so that the development of reduction techniques is vital.The most effective way to control is through the use of high-dielectrics,but such materials are not expected to come online until the2007-2010timeframe.
This paper explores the use of dual values for perfor-mance optimization,considering a leakage-delay tradeoff.In This work was supported in part by the SRC under contract2003-TJ-1092, and by the NSF under award CCR-0205227.
1The fundamental limit of scaling is projected to be about8?[3].order to simplify the search space,we divide this optimization in two stages.We?rst perform assignment based on a cost function,and then postprocess the result to perform tran-sistor and pin reordering.Although this optimization can be exploited at a number of points in the design methodology,our solution considers assignment as a step that is performed after placement and transistor sizing,at which point it is used to achieve a?nal performance improvement.Unlike earlier stages of design,there is less design uncertainty at this point and minor changes in layout parasitics due to assignment can be dealt with as an incremental update.As a result,all of the delay gains from our procedure are guaranteed in the ?nal design,with a low leakage power overhead.Furthermore, transistor and pin reordering is a postprocessing step that has a low layout impact,and is therefore an inexpensive optimization in terms of the changes that it may induce in the design.
Leakage power can be broadly divided into two categories, depending on the mode of operation of the circuit:standby leakage,which corresponds to the situation when the circuit is in a non-operating or sleep mode,and active leakage, which relates to leakage during normal operation.Numerous effective techniques for controlling standby leakage have been proposed in the past,including state assignment[4],the use of multiple threshold CMOS(MTCMOS)sleep transistors[5], body-biasing[6],and dual combined with state assignment [7].Active leakage,on the other hand,has not been widely addressed in the literature to date,primarily because it has not been a major issue in present technologies.However, leakage power dissipation in the active mode has grown to over 40%in some high-end parts today[8].Therefore,reducing active leakage is vital for advanced technologies in current-generation circuits and for next-generation technologies.The range of options that are available for reducing active leakage is considerably more limited than for standby leakage,and the use of dual assignments is a powerful method for this purpose.
Prior research related to our work2is summarized as fol-lows.In[11],the impact of on delay is discussed,but its impact on leakage power is not addressed.The work in[12] presents an approach to reducing,but not,using separate optimizations to select the values of.Similarly, several research works[13]–[15]pertaining to transistor re-ordering techniques have been reported.These approaches aim at reducing the dynamic power dissipation due to the switching activity of transistors,rather than reducing the leakage power 2This paper is based on our two previous conference publications[9],[10].
(a)(b)(c)(d)
LEGEND
NMOS
NMOS
(=)(=)
Fig.1.All possible con?gurations using pin and transistor reordering for two NMOS transistors in a series-(a)initial con?guration,(b)after pin reordering is applied to the initial con?guration,(c)after transistor reordering is applied to initial con?guration,and(d)after both transistor and pin reordering is applied to the initial con?guration.The transistor gates with thick dotted lines correspond to a,while those with thin dotted line correspond to assignment.
dissipation in the active mode.In[16],the authors examine the interaction between and,and their state depen-dencies.They apply two different pin reordering techniques: one attempts to minimize standby,while the other reduces runtime leakage.In both approaches,the effect of this transformation on circuit delay is not considered.Furthermore, pin reordering without transistor reordering limits the search space in dual circuits.To illustrate this,consider two NMOS transistors connected in series,as shown in Figure1. Applying pin reordering leads to only two possible cases((a) and(b))whereas if transistor reordering is also allowed,the number of cases double as the search space now also includes the con?gurations in cases(c)and(d)3.
In our context,where we optimize the total leakage com-prising both and,the rationale for optimizing is as follows.Choosing a lower value of can result in lower delays,but at the cost of increased leakage,and the value of can therefore be optimized to obtain a leakage/delay tradeoff.To maintain manufacturability and avoid enhanced short channel effects,it is important to scale the effective channel length along with[17].Similarly,while applying transistor and pin reordering,the best con?guration for each logic gate is chosen such that it results in maximum total leakage reduction without increasing circuit delay.
Due to processing constraints,rather than an unlimited range of values,it is more reasonable to choose between two permissible values.A suitable choice of should keep the to ratio to a reasonable value,as otherwise would completely dominate the total leakage current in the circuit.Furthermore,the two permissible values for should be fairly far apart in order to observe a noticeable tradeoff between total leakage and delay.
The organization of this paper is as follows.In Section II, we describe a method for selecting appropriate values of the low and high values of the oxide thickness,referred to as and,respectively,and the corresponding values for the channel length.Next,in Sections III and IV,respectively, we introduce the leakage and delay models that are used in this work,and demonstrate that they show a good degree of accuracy compared to simulation results.Our iterative algo-rithm for?nding the leakage/delay tradeoff is then presented in Section V.Next,we describe a transistor and pin reordering technique for minimization and reordering algorithm in Section VI and Section VII,respectively.Our experimental 3This assumes the possibility of having different values in a series-connected stack,which may or may not be easily achievable from a technology standpoint results are discussed in Section VIII and concluding remarks given in Section IX.
II.CHOOSING AND
While an increased value of can signi?cantly reduce ,several other physical effects must be taken into consid-eration.Increasing the value of while keeping the channel length constant may adversely impact the functionality of the transistor.Speci?cally,due to drain induced barrier lowering (DIBL),an increase in may result in a situation where the drain terminal takes additional control of the channel,so that the“on”or“off”state of the transistor is no longer completely governed by the gate terminal.
This effect is easily recognized during technology scaling, and scaling trends have shown that reduces nearly in proportion with[18].We maintain this proportion for each of the chosen values of by setting
(1) The term in this equation refers to the electrical, which is related to the physical value of as follows4
offset
(2)
The
offset
term is added to account for the gate depletion and channel quantization effects,and a typical value is0.7nm [19].In the remainder of this paper,it will be implicit that as we change,the value of is also scaled.
Before determining reasonable values for and, we study the effect of varying on leakage for an inverter, whose NMOS and PMOS transistors are sized to be0.8m and0.4m,respectively,in a100nm technology.The gate oxide leakage,,and the subthreshold leakage,,for both the NMOS and PMOS transistors in the inverter,are graphically depicted in Figure2(a)for various values of, at?;the sum of these components is shown by the bottommost curve in Figure2(b).The values of are obtained through SPICE simulations on predictive technology models[20],and an analytical model(described in Section III-B)is used to generate.5The average leakage of the inverter is calculated as the sum of the average and leakages(as described in greater detail in Section III),and is shown in Figure2(b).
4Henceforth,our discussions will be with reference to,the physical value of the gate oxide thickness.
5We cannot use simulations here since the Berkeley predictive technology model[20]uses BSIM3,which does not model.
10
10
10
10
10
10
and
for the NMOS and PMOS transistors,respectively)as a function of the gate oxide
thickness.(b)The total leakage of an inverter for different values of and .At each point,is scaled with respect to the minimum
value on the curve;at this point,nm.
(?)
(ps)(fF)1933.84 1.982133.77 1.992333.71 1.992533.67 1.992733.64 2.002933.62 2.00
T 4
T T T 1
2
3
(a)
(nA)Lo Lo 34.70Lo Hi 34.83Lo Lo 34.85Lo Hi 34.99Hi Lo 34.78Hi Hi 34.92Hi Lo 34.93Hi Hi
35.08
(b)
Fig.4.(a)A four-input NAND gate.(b)The variation of
in a 100nm technology through the pull-down chain,for the dominant state when only transistor (which uses )is off,under various combinations of for the other transistors.Here,?(Lo ),?(Hi ),and is at .
A change in of a transistor leaves the load capacitance
presented to the previous stage of logic unchanged.As a result,the delay of a fanin logic gate does not change signi?cantly,and hence our optimization method needs only to consider the delay change of a given logic gate
when its
is altered.Since the capacitance is unchanged,the (dynamic)power remains unaffected by changes in .This is extremely important since our optimization is therefore guaranteed to reduce the total power,even though it focuses on minimizing leakage.
III.LEAKAGE MODELS
We will now describe the models used to calculate and for each transistor,and the approach for computing the average and values for a given logic gate.The total leakage current for a logic gate is then computed as the sum of its corresponding average and .
A.Subthreshold Leakage Model
As seen in the Figure 3(b),the value of changes by
a very small amount as
is changed.In spite of this,it can have signi?cant effects on ,which is exponentially
dependent on
.For convenience,we use a simple look-up table (LUT)to determine .Conceptually,such an LUT could be extremely large:for a -input NAND gate,for instance,we would store the leakage current for each of the possible assignments 6,and each assignment would require entries for the leakage states corresponding to
different input logic values 7
,resulting in a total of entries.
The LUT size can be reduced signi?cantly using the fol-lowing ideas:
6Series-connected
devices can have different
and the design rules that take this into account would increase the spacing between such devices as compared to the case where all devices have identical
values.
7The only input assignment with no leakage due to NMOS is the case when all transistors in the pull-down chain are on.
Dominant input states:It has been shown [21]that can
be accurately captured by using a set of dominant states,corresponding to the cases where only one transistor on each path to a supply node is on.
Weak
dependencies:In a dominant state,for a given choice for the leaking transistor the subthreshold
leakage is only weakly dependent on the
values of other transistors.Intuitively,this relates to the fact that the leaking transistor is the largest resistance on the path.We have validated this through SPICE simulations,and the results for a 4-input NAND gate are shown in Figure 4(b).When is the leaking transistor and is set to ,it can be seen that has a range of only about 1%over all possible assignments for the other inputs.Similar results are seen for other logic gates over various assignments.
For a -input NAND gate,there are dominant states.The weak dependencies require that for each of these states,
two
numbers must be maintained:one at and one at .As a result,the LUT size can be brought down to entries.
For a logic gate with -parallel transistors (such as the pull-up in a -input NAND,or a pull-down in a -input NOR),two entries (one each for and )are suf?cient as
the value of
per unit
regions.The latter type of tunneling,referred to as edge direct tunneling(EDT)is ignored in our case for three reasons:?rst, because the gate-to-drain/source overlap region is signi?cantly smaller than the channel region[11],second,because the oxide thickness in this overlap region can be increased after gate patterning to further suppress EDT[22]and third,because EDT is smaller than tunneling in gate-to-channel region[23]. We also neglect the OFF state gate oxide leakage and consider only the ON state values[24].
Our work focuses on gate-to-channel tunneling,and we use the following analytic tunneling current density() model based on the electron[hole]tunneling probability through a barrier height()[25].
where is the effective electron[hole]mass in the oxide,is the operating temperature,and is the barrier height.
It was shown in[16]that like,also exhibits a state dependency.When the gate node of the NMOS transistor is at logic0,the only possible tunneling component is EDT,which is neglected in our work;therefore,we will only consider the cases where the gate node is at logic1.For example,while determining for transistor in the4-input NAND gate in Figure4(a),it can be shown that the maximum leakage for occurs at the input state8,and that the values for the states,and can be ignored.This is because,for the later three sets of states, voltage level at the source node of transistor increases due to the combined effect of and.This results in a smaller gate-to-source voltage for.It is known that reduces by an order of magnitude for each0.3v reduction in gate-to-source voltage[2].A reduction in gate-to-source voltage by0.3v is possible for transistors at.Thus the dominant state of for is.Observe that for transistors at,is not of concern as dominates the total leakage current.For further details,the reader is referred to[16].
In general,this may be restated as follows:the dominant state for for a particular transistor in a stack corresponds to the case when all of the transistors below(above)it in the NMOS(PMOS)stack are on.The average for a logic gate can then be calculated as:
transistor logic gate
(5) Here,for NMOS(PMOS)transistors connected in parallel, as in a NOR(NAND)gate,is the probability that the input is at logic1(0).For a stack of NMOS(PMOS)transistors in series as in a NAND(NOR)gate,for a transistor is the 8“State”=logic values at the inputs to.
TABLE I
D ELAYS FROM TH
E INPUT O
F SWITCHIN
G TRANSISTOR IN A4-INPUT
NAND[F IGURE4(A)]@(?,?).
Delay
Spice Error
Lo Lo—
Lo Hi14.51
Lo Hi14.21 2.11%
Lo Lo14.51
Lo Hi15.13
Hi Lo15.47-2.20%
Lo Lo15.13
Lo Hi—
(6)
where and are delay values(stored in the LUT)for the extreme cases of non-switching transistors being at all and all,respectively,as shown in Table I,is the number of transistors(other than the switching transistor)at and(k-1)is3for a4-input Nand gate.The errors under this method are shown in Table I.Therefore,all possible fall delay scenarios for a-input NAND gate can be compacted into LUT entries.This technique was applied to several gate types,and in most cases,the error was under2%,with a worst-case error of3%.
A similar compression for the case of output rise LUTs of a-input NAND is possible.Since the PMOS transistors are in parallel,only the gate-to-drain overlap capacitance at the output node changes for different combinations for the transistors;this has an insigni?cant impact on the delay,and hence,2LUT entries(corresponding to and for each PMOS input)are suf?cient.
A similar approach can be applied to build LUTs for a-input NOR gate,and for other types of logic gates.Therefore, the total number of LUT entries varies linearly with the number of inputs to the logic gate.Furthermore,the input transition time can be accounted for in this model by creating one such LUT for each candidate transition time.
V.DUAL ASSIGNMENT
In this section we describe our heuristic to obtain acceptable tradeoffs between leakage and delay in a dual circuit. The input to the algorithm is a combinational netlist.The circuit is represented by a graph where each gate corresponds to a node and the interconnections between gates correspond to edges.We use a TILOS(TImed LOgic Synthesizer)like [26]sensitivity-based heuristic for assigning values to individual transistors in a circuit.A standard static timing analysis(STA)approach is used to?nd the critical path. The propagation delay for each gate is computed using the LUTs described in Section IV.In principle,the STA must be repeated after each change;however,we observe that every such change is suf?ciently local and only changes delays and arrival times in its transitive fanout region. Therefore,after the?rst iteration,we achieve ef?ciency by performing incremental STA that processes only the affected regions.
Once this critical path is found,the core of the optimizer iteratively changes one transistor on this path from
to in each iteration.This transistor is identi?ed by measuring the increase in the total average leakage,, with respect to the delay reduction,,observed on the critical path when such a change is made.In other words, we evaluate
Cost Algorithm1Pseudocode for Dual Assignment()
;=NULL;
15:for each node on a critical path do
16:if(critical path transistor(s)of are at)then 17:?nd
then
24:Assign to the worst transistor in
25:Update,,,of
26:Perform Incremental STA and recalculate
27:else
28:Report;Exit()
29:end if
30:end while
Exit
Find AT, RT for each node (STA)
Choose a critical path
(incremental STA)
Update AT, RT NO
NO
target delay
Is
met ?YES
YES
NO
Are all transistors on this critical path already at
?each transistor on chosen critical path
Transistor with most negative cost is assigned to
Set all transistors to
Compute cost for
,where’state’corresponds to logic values at inputs to.
in Figure6(d)may not be acceptable if it increases the circuit delay.We perform an exhaustive search on a gate-by-gate basis and accept the permissible con?guration that satis?es the delay constraints.The total leakage of individual logic gates is considered during this exhaustive search in order to obtain reductions in the total expected leakage of the circuit rather than just.
VII.REORDERING ALGORITHM
We now describe our algorithm for?nding the leakage-optimal con?guration for the logic gates in a circuit under a speci?ed delay constraint.The input to the algorithm is a netlist that has undergone dual optimization,i.e.,a speci?c design choice on the leakage/delay tradeoff curve obtained in Section V.
The optimization for leakage reduction through reordering is performed under the constraint that the circuit delay must remain the same.For a speci?c node,the improved reordering con?gurations will lead to a reduction in the total leakage ()while either increasing or decreasing the node delay:any increase in the node delay must be within the slack at the node,so as not to increase the circuit delay.
To ensure that the slack remains positive,we divide the search space of possible con?gurations into two categories: Search_spc1contains nodes that have a reordering con?gu-ration resulting in an increase in the node delay. Search_spc2contains those with a corresponding reduction in the node delay.
The nodes in Search_spc2are preferred since they reduce both leakage and delay.The cost function10assigned to 10This is something of a misnomer since the“cost”is actually a bene?t in this case.each node is the reduction in total leakage.Therefore,the con?guration for each node in the second search space that has the maximum cost is chosen?rst,and these selections result in additional slack being created in the circuit.
This slack,and any existing slack in the circuit,can be consumed using node con?gurations from Search_spc1.The order in which these nodes are chosen is based once again on a TILOS-like[26]sensitivity-based method.The node that provides maximum ratio of leakage reduction to node delay increase is chosen.If is the decrease in node leakage and is increase in node delay,we evaluate
Cost
1:Input:A dual-circuit
2:Output:A transistor/pin reordered dual-circuit
3:/*Circuit is represented as an acyclic graph*/ 4:Propagate state probabilities from PIs to internal nodes 5:for each node do
6:Find output load=fanout nodes gate capacitance+ interconnect capacitance
7:Get rise,fall delays(,)from delay LUT 8:Find,based on leakage models
9:end for
10:Perform STA to?nd rise and fall,for each node 11:Create empty sets,Search_spc1and Search_spc2
12:for each node do
13:Update-Search-Space()
14:end for
15:while(Search_spc1and Search_spc2are not empty)do 16:if(Search_spc2is not empty)then
17:=most negative cost node in Search_spc2 18:else
19:=most negative cost node in Search_spc1 20:end if
21:Assign the best con?guration to
22:Update,,,of
23:Perform STA to update rise and fall, of effected nodes.
24:for each node encountered during STA do
25:if(Search_spc1)then
26:Search_spc1=Search_spc1-{}
27:else if(Search_spc2)then
28:Search_spc2=Search_spc2-{}
29:end if
30:Update-Search-Space()
31:/*nodes might be added,removed or their cost might change while updating the search space.*/
32:end for
33:end while Algorithm3Update-Search-Space()
5:else
6:Search_spc2=Search_spc2{} 7:cost()=
8:end if
9:end if
Delay (ns)T o t a l L e a k a g e C u r r e n t (μ A )
(a)
(b)
Fig.8.Leakage/Delay tradeoff curves for C3540and C2670at the (a)100nm and (b)70nm technology nodes.In (I),all transistor
values are optimized,in (II),all PMOS devices ?xed at and all NMOS values are optimized,and in (III),the optimization is performed at the stack level,by assigning
a single
value to an entire stack of
transistors.
(a)
(b)
Fig.9.Leakage/Delay tradeoff curves for C5315for (a)100nm,and (b)70nm technology nodes,for ?ve different circuit structures obtained from SIS [28].
which correspond to a case where all PMOS transistors are set to and the values of only the NMOS devices are optimized.This curve is clearly inferior to the curves (I)that correspond to a full optimization for both NMOS and PMOS transistors.
In each of the possible design choices on tradeoff curves (I)and (II),series-connected devices,i.e.,a stack of transistors,
can have different
values.Design rules that take this into account would increase the spacing between such devices compared to the case where all of the series-connected devices have identical .It is possible that this would lead to a signi?cant increase in total chip area.In order to avoid such area increases,we explored a coarse-grained assignment strategy.If a stack of transistors is on the critical path,we
assign all of the transistor to
instead of assigning only one transistor in a stack to
.The tradeoff for this is shown by the curves (III)in Figure 8.Observe that for all points on the right knee region,curve (III)and curve (I)overlap.However,the points to the left of the knee have a small to moderate leakage overhead for the same delay.Hence,if the design choice is only limited to the knee or to points right
of the knee,then a coarse-grained
assignment would be preferable as it could achieve designs with smaller area than
the original strategy of assigning to individual transistors.It should be pointed out that,the percentage of three-and four-input logic gates in all of our benchmark circuits range between 0–17%.Therefore,it is possible that owing to small percentage of large stacked transistors,curves (I)and (III)may have a large overlap.We expect that as the percentage of large stacked transistor increases,this overlap region will not only shrink,but may also lead to higher leakage overhead in curve (III),as compared to curve (I),for the same delay.
There are various techniques to reduce delay of a circuit,such as restructuring and resizing.In order to examine whether
dual-approach is consistent with these techniques,leak-age/delay tradeoff curves were generated for ?ve different circuit structures for C5315(using SIS [28]for mapping).Figure 9shows tradeoff curves obtained at the 100nm and 70nm technology nodes.The results are consistent across dif-ferent restructured circuits,i.e.,for all of the ?ve restructured circuits,our optimization yields a maximum possible delay reduction of about 20%for 100nm node,and about 17%for
70nm node.These results also suggest that dual-approach is orthogonal to other delay optimization approaches,and does
TABLE II
L EAKAGE/DELAY TRADEOFFS FROM DUAL OPTIMIZATION.F OR EACH CIRCUIT,R OW1=ALL TRANSISTORS AT,R OWS2=END RESULTS BASED ON OUR OPTIMIZATION,R OW3=ALL TRANSISTORS AT,R OW4=STARTING FROM“ALL”POINT,ALL TRANSISTOR OF CRITICAL PATH LOGIC GATES ARE BLINDLY ASSIGNED TO.R OW2MATCHES THE DELAY FOR THE“ALL”POINT WITH A LEAKAGE SAVINGS OF“%R,”AND“%D”IN R OW1SHOWS THE DELAY PENALTY OF THE ALL CASE RELATIVE TO THIS POINT.E ACH ROW SHOWS,AND,AND THE CPU TIME REQUIRED TO GENERATE THE ENTIRE LEAKAGE-DELAY TRADEOFF CURVE IS IN THE LAST COLUMN.
70nm Technology
Circuit CPU Time Delay Leakage Current()
(ns)(D)(s)(ns)(D)(s)
1.38(25.6)0.88 1.32(20.3)0.20
3.1633.44(75.8) 5.6229.65(73.4)
1.10134.16 1.10106.52
2.9936.60 5.6731.84
C4997.058.5414.3014.64
0.8945.7612.10.9054.9213.8
9.61238.6812.66195.50
1.1011.92 1.088.28
1.06(25.5) 1.16 1.02(21.0)0.26
4.8314.50(92.2)9.1821.17(86.0)
0.85179.100.84143.05
4.7720.789.1921.08
C13557.559.2215.4315.81
0.9031.9711.30.9031.9113.3
10.08264.4113.29215.73
1.131
2.83 1.099.29
1.44(25.1) 1.91 1.42(20.9)0.43
9.3651.97(83.1)16.5350.66(79.9)
1.15295.53 1.17236.66
8.5923.0716.8527.48
C267011.3114.7722.7023.49
1.1526.487.0 1.1421.37 6.9
15.24541.5219.82437.92
1.3323.15 1.2517.03
1.87(25.3) 4.29 1.83(20.9)0.97
16.8565.40(90.4)31.5772.38(87.0)
1.49660.41 1.52527.72
16.0147.2031.7352.94
C531524.3732.4849.1751.01
1.4555.6933.1 1.4656.1635.6
33.041267.4343.211023.67
1.7935.79 1.7325.37
5.10(25.7)8.80 5.02(20.7) 2.00
41.67361.89(74.0)73.48350.23(69.1)
4.061340.37 4.16106
5.20
37.71110.5175.41129.75
C755236.0045.7172.7074.91
1.6725.3330.9 1.6218.9833.5
49.111533.6964.361246.22
2.0317.70 1.869.28
TABLE III
R ESULTS OF TRANSISTOR AND PIN REORDERING,APPLIED TO A SET OF DESIGN POINTS ON THE LEAKAGE/DELAY TRADEOFF CURVE.
CPU Time
C2(sec)
C432 3.2 5.4 5.80.59
4.0 4.69.0
5.911.9
6.5
C880 6.0 6.4 6.70.39
3.9 3.57.5
4.49.5 4.8
C1908 3.5 3.6 3.7 1.20
17.110.025.011.826.512.1
C3540 5.3 5.6 5.6 3.12
11.38.119.39.720.39.9
C6288 2.9 2.9 3.119.45
10.1 6.213.3 6.713.7 6.7
70nm Technology
C432 3.1 3.3 3.50.66
2.1 2.7
3.6 3.39.4 3.5
C880 4.6 4.6 4.90.42
1.4
2.1 2.7 2.28.1 2.4
C1908 2.7 2.9 2.9 1.32
11.8 5.320.4 5.427.0 5.7
C3540 4.3 4.4 4.5 2.64
6.7 4.416.7 4.620.6 4.7
C6288 1.9 1.9 1.920.48
6.7 3.212.2 3.313.6 3.3
lower,with maximum reductions of17%and11%for the 100nm and70nm nodes,respectively,and the reasons for this are described above.The reduction in is under7%and is practically constant for all benchmarks.The CPU times for all circuits are shown in the table,and each number corresponds to the maximum of the CPU times over all points on the leakage/delay tradeoff curve.It is clear that the procedure is extremely fast,only requiring a few seconds.Observe that transistor reordering is not performed for the case of coarse-grained assignment(see Figure8curve(III))as all of the transistors in a stack are assigned to either or. Hence,the reordering search space is signi?cantly reduced and so we do not perform reordering on this coarse-grained tradeoff curve.
The table also shows the reductions in total leakage,which are seen to be up to12.0%(for point C3of C2670).Although these are not startlingly dramatic numbers,they still corre-spond to solid reductions in the total leakage with no delay penalties.An important point to note is that this is an in-place optimization with low layout impact,so that the reductions can actually be guaranteed,and are not likely to suffer from signi?cant estimation errors.
IX.CONCLUSION
We have presented a technique for reducing the total active mode leakage current,including gate oxide leakage,by deter-mining appropriate values of,and iteratively assigning them to individual transistors in the circuit.Our approach provides the complete tradeoff curve between leakage and delay,and achieves delay reductions of20%and17%for predictive100nm and70nm technologies,respectively. Furthermore,complex gates with series-connected devices show some?exibility in varying the relative ordering of the pins and transistors.We have presented a simple transistor and pin reordering technique that exploits this design space for reducing the total active leakage in dual circuits.A major advantage of this optimization is its low impact on layout.It has been shown that this optimization results in an overall leakage reduction of up to12.0%,and a reduction in gate leakage of up to26.0%with no delay penalties while the optimization requires under25seconds on all benchmarks. In this work,we have shown a technique for computing by estimating and individually.This approach is based on the concept of dominant states with the assumption that EDT in the ON state of the device is negligible.While we are aware of commercial technologies where this assumption is valid,this may not be true of all devices in the future.In such a case,the in the on state can still be estimated using a similar calculation that sums up its gate-to-channel and EDT currents,invoking the dominant states.Effectively,this implies that the constant used to express the gate leakage per unit width is changed.
The results in this work are based on a heuristic approach, and there is room for the use of more sophisticated algorithmic methods to be applied to this problem in future work.
R EFERENCES
[1]Semiconductor Industry Association,“International Technol-
ogy Roadmap for Semiconductors,”2003.Available at https://www.wendangku.net/doc/205783709.html,.
[2] F.Hamzaoglu and M.R.Stan,“Circuit-Level Techniques to Control
Gate Leakage for Sub-100nm CMOS,”in Proceedings of International Symposium on Low Power Electronics and Design,pp.60–63,Aug.
2002.
[3]M.Hirose,M.Koh,W.Mizubayashi,H.Murakami,K.Shibahara,
and S.Miyazaki,“Fundamental Limit of Gate Oxide Thickness Scal-ing in Advanced MOSFETs,”Semiconductor Science and Technology, vol.15(5),pp.485–490,May2000.
[4] D.Lee and D.Blaauw,“Static Leakage Reduction through Simultaneous
Threshold Voltage and State Assignment,”in Proceedings of ACM/IEEE Design Automation Conference,pp.191–194,Jun.2003.
[5]J.Kao,A.Chandrakasan,and D.Antoniadis,“Transistor Sizing Issues
and Tool for Multi-Threshold CMOS Technology,”in Proceedings of ACM/IEEE Design Automation Conference,pp.409–414,Jun.1997. [6]Y.Oowaki,M.Noguchi,S.Takagi,D.Takashima,M.Ono,Y.Mat-
sunaga,et al.,“A sub-0.1Circuit Design with Substrate-Over-Biasing,”in IEEE International Solid-State Circuits Conference Digest of Techinal Papers,pp.88–89,Feb.1998.
[7] D.Lee,H.Deogun,D.Blaauw,and D.Sylvester,“Simultaneous State,
and Assignment for Total Standby Power Minimization,”in Proceedings of ACM/IEEE Design,Automation and Test in Europe, pp.494–499,Feb.2004.
[8]S.Narendra,D.Blaauw,A.Devgan,and F.Najm,“Leakage Issues in
IC design:Trends,Estimation,and Avoidance.”Tutorial at ACM/IEEE International Conference on Computer Aided Design,Nov.2003. [9] A.Sultania,D.Sylvester,and S.S.Sapatnekar,“Tradeoffs between
Gate Oxide Leakage and Delay for Dual Circuits,”in Proceedings of ACM/IEEE Design Automation Conference,pp.761–766,June2004.
[10] A.Sultania,D.Sylvester,and S.S.Sapatnekar,“Transistor and Pin
Reordering for Gate Oxide Leakage Reduction in Dual Circuits,”
in Proceedings of IEEE International Conference on Computer Design, pp.228–233,Oct.2004.
[11] C.-H.Choi,Z.Yu,and R.W.Dutton,“Impact of Gate Direct Tunneling
on Circuit Performace:A Simulation Study,”IEEE Transactions on Electron Devices,pp.2823–2829,Dec.2001.
[12]N.Sirisantana,L.Wei,and K.Roy,“High-Performace Low-Power
CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness,”in Proceedings of IEEE International Conference on Com-puter Design,pp.227–232,Sept.2000.
[13]R.Hossain,M.Zheng,and A.Albicki,“Reducing Power Dissipation
in CMOS Circuits by Signal Probability Based Transistor Reordering,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol.15(3),pp.361–368,Mar.1996.
[14] E.Musoll and J.Cortadella,“Optimizing CMOS Circuits for Low Power
using Transistor Reordering,”in Proceedings of European Design and Test Conference,pp.219–223,Mar.1996.
[15]S. C.Prasad and K.Roy,“Circuit Optimization for Minimization
of Power Consumption under Delay Constraint,”in Proceedings of International VLSI Design Conference,pp.305–309,Jan.1995. [16] D.Lee,W.Cong,D.Blaauw,and D.Sylvester,“Analysis and Minimiza-
tion Techniques for Total Leakage Considering Gate Oxide Leakage,”
in Proceedings of ACM/IEEE Design Automation Conference,pp.175–180,Jun.2003.
[17]K.Bernstein,“Private Communication.”IBM T.J.Watson Research
Center,Yorktown Heights,NY,2003.
[18]Y.Taur,“CMOS Design Near the Limits of Scaling,”IBM Journal of
Research and Development,vol.46(2/3),pp.213–222,Mar./May2002.
[19]K.Chen,C.Hu,P.Fang,M.R.Lin,and D.L.Wollensen,“Predicting
CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects,”IEEE Transactions on Electron Devices,vol.44(11), pp.1951–1957,Nov.1997.
[20]Device Group at UC Berkeley,“Berkeley Predictive
Technology Model,”2002.Available at https://www.wendangku.net/doc/205783709.html,/ptm/.
[21]S.Sirichotiyakul,T.Edwards,O.Chanhee,R.Panda,and D.Blaauw,
“Duet:An Accurate Leakage Estimation and Optimization Tool for Dual-Circuits,”IEEE Transactions on Very Large Scale Integration Systems,vol.10(2),pp.79–90,Apr.2002.
[22] A.Chandrakasan,W.J.Bowhill,and F.Fox,Design of High-
Performance Microprocessor Circuits.Piscataway,NJ:IEEE Press, 2001.
[23]M.Draˇz dˇz iulis and https://www.wendangku.net/doc/205783709.html,rsson-Edefors,“A Gate Leakage Reduction
Strategy for Future CMOS Circuits,”in Proceedings of European Solid-State Circuits Conference,pp.317–320,Sept.2003.
[24]W.Henson,N.Yang,S.Kubicek,E.M.V ogel,J.J.Wortman,K.D.
Meyer,and A.Naem,“Analysis of Leakage Currents and Impact on Off-State Power Consumption for CMOS Technology in the100-nm Regime,”IEEE Transactions on Electron Devices,vol.47(7),pp.1393–1400,July2000.
[25]K.A.Bowman,L.Wang,X.Tang,and J.D.Meindl,“A Circuit-Level
Perspective of the Optimum Gate Oxide Thickness,”IEEE Transactions on Electron Devices,vol.48(8),pp.1800–1810,Aug.2001.
[26]J.Fishburn and A.Dunlop,“TILOS:A Posynomial Programming Ap-
proach to Transistor Sizing,”in Proceedings of ACM/IEEE International Conference on Computer Aided Design,pp.326–328,Nov.1985. [27] F.Brglez and H.Fujiwara,“A Neutral Netlist of10Combinatorial
Benchmark Circuits,”in Proceedings of IEEE International Symposium on Circuits and Systems,pp.695–698,Jun.1985.
[28] E.M.Sentovich,K.J.Singh,https://www.wendangku.net/doc/205783709.html,vagno, C.Moon,R.Murgai,
A.Saldanha,et al.,“SIS:A System for Sequential Circuit Synthesis,”
Tech.Rep.UCB/ERL M92/41,Electronics Research Laboratory,De-partment of Electrical Engineering and Computer Sciences,University of California,Berkeley,May1992.[29]Capo:A Large-Scale Fixed-Die Placer from UCLA.Available at:
https://www.wendangku.net/doc/205783709.html,/GSRC/bookshelf/Slots/
Placement/.
[30]J.Hu and S.Sapatnekar,“A Timing-Constrained Simultaneous Global
Routing Algorithm,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol.21,pp.1025–1036,Sept.2002.
[31]J.Cong,“Challenges and Opportunities for Design Innovations in
Nanometer Technologies,”in SRC Design Sciences Concept Paper,Dec.
1997.
Anup Kumar Sultania received the B.E.degree in
electrical engineering from Birla Institute of Tech-
nology and Science,Pilani in2002,the M.S.degree
in electrical engineering from University of Min-
nesota,Twin-Cities in2004.He is currently working
in Calypto Design System,Inc.,Santa Clara,CA.He
has previously worked as an intern for six months
at ST Microelectronics,India.His present research
interests are power analysis and
optimization.
Dennis Sylvester(S’95,M’00,SM’04)received
the B.S.degree in electrical engineering summa cum
laude from the University of Michigan,Ann Arbor,
in1995.He received the M.S.and Ph.D.degrees in
electrical engineering from University of California,
Berkeley,in1997and1999,respectively.His disser-
tation research was recognized with the2000David
J.Sakrison Memorial Prize as the most outstanding
research in the UC-Berkeley EECS department.
He is now an Associate Professor of Electrical
Engineering at the University of Michigan,Ann Arbor.He previously held research staff positions in the Advanced Technology Group of Synopsys,Mountain View,CA,and at Hewlett-Packard Laboratories in Palo Alto,CA.He has published numerous articles along with one book and several book chapters in his?eld of research,which includes low-power circuit design and design automation techniques,design-for-manufacturability,and on-chip interconnect modeling.He also serves as a consultant and technical advisory board member for several electronic design automation?rms in these areas.
Dr.Sylvester received an NSF CAREER award,the2000Beatrice Winner Award at ISSCC,a2004IBM Faculty Award,and several best paper awards and nominations.He is the recipient of the ACM SIGDA Outstanding New Faculty Award,the1938E Award from the College of Engineering Award for teaching and mentoring,and the Henry Russel Award,which is the highest award given to faculty at the University of Michigan.He has served on the technical program committee of numerous design automation and circuit design conferences and was general chair of the2003ACM/IEEE System-Level Interconnect Prediction(SLIP)Workshop and2005ACM/IEEE Workshop on Timing Issues in the Synthesis and Speci?cation of Digital Systems(TAU).He is currently an Associate Editor for IEEE Transactions on VLSI Systems.He also helped de?ne the circuit and physical design roadmap as a member of the International Technology Roadmap for Semiconductors (ITRS)U.S.Design Technology Working Group from2001to2003.He is a member of ACM,American Society of Engineering Education,and Eta Kappa
Nu.
Sachin Suresh Sapatnekar received the B.Tech.
degree from the Indian Institute of Technology,
Bombay in1987,the M.S.degree from Syracuse
University in1989,and the Ph.D.degree from the
University of Illinois at Urbana-Champaign in1992.
From1992to1997,he was an assistant professor
in the Department of Electrical and Computer En-
gineering at Iowa State University.He is currently
the Robert and Marjorie Henle Professor in the
Department of Electrical and Computer Engineering
at the University of Minnesota.
He has authored several books and papers in the areas of timing and layout. He has held positions on the editorial board of the IEEE Transactions on VLSI Systems,and the IEEE Transactions on Circuits and Systems II,IEEE Design and Test,and the IEEE Transactions on CAD.He has served on the Technical Program Committee for various conferences,and as Technical Program and General Chair for Tau and ISPD,and Techical Program co-chair for DAC. He has been a Distinguished Visitor for the IEEE Computer Society and a Distinguished Lecturer for the IEEE Circuits and Systems Society.He is a recipient of the NSF Career Award,three best paper awards at DAC and one at ICCD,and the SRC Technical Excellence award.He is a fellow of the IEEE.
公司网络现状及整改建议
公司网络现状及整改建议 一、网络现状 通过现场的调研了解到，原有网络布局，随着公司业务的发展，员工逐渐增加，现有的网络情况已经不能满足公司的网络发展。 存在的问题 1、网络规模小：目前无线覆盖率极低，无线AP8个,规模过小，而且无线AP 使用多年，老化，带用户数量极少，只能达到54M 带宽，用户承载数不到9个且极不稳定。 2、可靠性差：现有的网络构造，容易因为一条线路或者交换机出现问题都会给后面楼层的网络造成严重影响。去年至今出现多次交换机烧坏，导致整个楼层上不了网。如下图，如果一层的交换机出现问题，后面二、三等楼均无法使用网络，导致公司网络瘫痪。 3、网络稳定性差：公司目前网络经常性掉线。原来3、4楼的华为交换机烧坏后采用现有的中兴交换机设备，品牌兼容性，稳定性，匹配性都不能达到正常水平。
4、网络拓扑结构的不清晰：走线到各个办公室后，网络由多种路由、交换机连接起来，并且这些终端品牌杂乱，分散的布置在办公桌下、天花板顶等难以维护的位置。这些网络拓扑结构的不清晰、零乱的布置、维护难度大等问题困扰着公司网络稳定。 二、整改建议 1、本次改造遵循以下原则： 1.1，可靠性：采用完全可靠的连接方式，在单台交换机出现故障的时候，保障其他 网络不受影响。 1.2，兼容性：新增或更换的网络设备必须是成熟配套的产品，遵循国际标准。 1.3，可扩展性：根据未来业务的增长和变化，网络可以平滑的扩充和升级，最大程 度的减少对网络架构和现有设备的调整。 1.4，可实施性：工程实施应该尽可能简单易行，尽量减少对已有设备的影响和已有 线路的更换。 2、设计方案比较解析 2.1，有线部分解析 2.1.1 目前方案简易拓仆图：
提升工作效率、改善工作
提升工作效率、改善工作收入之我见 就目前我公司现状，时间紧、任务重但多数人员对收入却不是很满意，甚至部分人员很有想法。我站在我个人角度，我认为有以下几方面问题； 一、工程师方面。 前期因为工程师，特别是生产值班长流失严重，使公司下决心多培养全方面的综合管理人员，使每一位目前的现场工程师都能够在必要的时候提升或胜任值班长或主管工作。但目前的情况是通过招聘而来现场工程师良莠不齐，各种待遇一样，甚至出现多干错误愈多，问题越多的情况，打消了部分工程师的积极性，同时比较差的工程师也起到了反作用。 具体表现为：每天上班混日子，工作态度差，责任心弱；遇到问题两手一滩，不思进取； 整治方法：对于这样不适合公司目前岗位要求的人员提出警告、通过一定时间观察，若不能改变工作态度、提高工作能力，就不要心慈手软。 我认为目前班组五、六名工程技术人员配置过多、臃肿，我建议挑选得力人员组成三人班组即：值班长、设备工程师、质量工程师，以及非脱产区域小组长配合工作的局面。这样方方面面的工作都有人担当，设备人员素质较高解决问题用时少、有助产能保证；质量管理人员精干，质量又得以保证，而非现在人人管质量人人管不好的现象。 二、非生产工位人员 目前，公司内维修、检验人员过多且工作不饱满，同时又普遍工资较生产计件人员工资低。我认为目前的维修人员不应参与质量考核，而应考核多少维修问题用时和不能解决问题的能力方面。 在检验人员方面我赞同把公司班组入库检验与发运检验合并，因为在这两个环节存在一些不负责任的工人，可以利用我们的产品质量稳定混取时间和工资，表现为平时不能发现问题，一旦出现质量问题，就会暴露在顾客东岳处；另外我认为当日发货比较紧数量大的时候发货人员是否能够有合理的时间执行检验工作。三、全体员工 以下是我在两年前提出的建议，部分已采纳，希望公司领导采纳或提高幅度。（本人自2006年3月来中瑞公司，业已近半年因水平有限，故对公司贡献不大，但我认为以下建议有利于公司三方面对发展。仅供参考。 1，，创建企业文化，提高企业形象 2，充分发挥员工的能动性和积极性； 3，配合目前生产经营状况，稳定提高员工队伍 建议1：增加满勤奖30元/人。月（月、季、年满勤） 任何原因缺勤1天，扣发当月满勤奖 任何原因缺勤2天，扣发当月及下月的满勤奖 注：本奖能有利于消除计件工资造成的负面影响；同时降低计件分值，利用计件分值节省的钱采用月满期+季满勤+年满勤的方式发放，有助于班组人员管理。
现状及改进建议
对《金泰简报》的现状分析和改进性建议 一、现状的分析 《金泰简报》的创办是金泰氯碱成立以来企业文化建设的一件大事。她的创办对于传达公司经营发展理念、提升企业管理水平、了解公司发展动态、活跃员工精神文化生活发挥了不可替代的积极作用，并取得了良好的效果。但在发掘、孵化、培育和建设企业文化上还存在力度性和形式上的欠缺。 力度上的欠缺主要是指办刊定位和宗旨可能不明确，导致选材主体思想模糊，服务于办刊宗旨的功能不清晰。形式上的欠缺主要是个别选材文字组织还有进一步提升的空间，版面的编排美观性还存在不足，专题栏目过多内涵界限模糊存在功能上的重叠。 要办好简报必须对简报的功能实质有一个充分完整深刻的理解，必须对企业文化的基本内涵有一个总体的把握，这是提高简报质量实现简报本质功能的关键。 我个人理解，企业文化是企业经营、发展活动中自觉持续的一种健康、积极、向上的态度或者习惯，是一套先进科学的经营管理和发展理念，是一个企业的性格、做事方式、价值观和精气神…… 企业文化是一种软实力。成熟先进的企业文化会赋予企业各种资源一种活力，为各种资源的合理高效配置、整合提供一种自觉的动能。她对企业发展和经营管理的提升是一种随风潜入夜润物细无声式潜移默化的正向效应。企业文化的不断建设可以使企业从以资金实力、经营规模、供货价格等要素
为基础的传统同质化竞争转变为以独特先进企业文化统领下企业全要素协同作用为基础的差异化竞争，为企业在普遍竞争中取得差别利润实现企业更大发展提供了一种可能。 区别于设备和生产资料需要花费巨资，企业文化建设不需要过多的投入。她的形成和建设需要的是发掘文化基因、孵化企业精神、培育和建设企业文化的平台。 我认为《金泰简报》就是这一平台，应该成为企业文化建设的主阵地和战斗堡垒。目前《金泰简报》基本上发挥了这一作用，在企业文化建设中的这种特殊贡献应该予以肯定，但更应该在发展中紧扣经营管理现实，把握公司发展战略，脚踏实地，举头望远，阔步前进不断进行功能性完善和品质化提高，将公司企业文化建设推进到一个新的高度，为企业的经营管理和长远发展提供强大精神动力、深厚的理论支持和正确的方向保证。 二、进一步改进的建议： (一)进一步明确办刊定位强化办刊宗旨，确立以下四条为《金泰简报》 的办刊定位和办刊宗旨： 1.宣传决策层管理意图、经营理念、发展战略的忠诚喉舌； 2.明确目标、凝聚共识、提振士气、协力同心的战斗号角； 3.孵化企业精神的暖箱培育企业文化的摇篮； 4.彰显职工精神风貌的橱窗展示公司成长进步的平台。 (二)形式上的改进： 形式上应当在维持目前发行期的同时改目前的A4期刊版为A3幅面的报刊版。更换目前的排版工具，使用其他平面处理软件，进一步优化版面设计，
提高工作效率的总结
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RE：我是这么调用的（C语言） extern void DSP28x_usDelay(long time); 在需要延时的地方加入 DSP28x_usDelay(0x100000);//根据延迟时间写入参数
关于提高工作效率的建议
关于提高工作效率加快回款力度的几点建议 经过现阶段的工作，本人对目前所负责的工作有一定的认识，认为大部分工作开展的较为不错，但还有个别工作未能及时完成、部分按揭款未能及时回款的问题。这其中有主观因素也有客观因素，主观因素主要是某些经办人员业务素质有待提升，工作作风拖拉。客观因素主要是人员少、事情多、银行及相关职能部门政策变动等诸多原因影响了部分工作的正常进行速度，致使部分业务的办理进度滞后。我们如何能克服缺点，在提高自身素质的情况下，找到能够解决客观困难的方法，在现有的条件下使工作能够更好，更快地完成是我们的当务之急。本人对此谈几点个人的看法： 一、明确各岗位职责；引入月度计划、总结及绩效考核制度 明确各部门、各岗位职责，以便合理分工责任到人。调整现有薪酬制度，将固定工资改为基本工资+绩效工资的形式。每月第二个工作日前上报上月工作总结、本月工作计划，由各经办人分别提交后由部门经理汇总、整理、修改后统一上报（超时未上报的处罚相关当事人20元/人/次），经领导审批后确定当月任务，临时任务例外。每月底根据当月工作完成情况进行绩效考核，按照考核结果发放绩效工资。另外绩效考核结果与员工转正、岗位调整等人事行为直接挂钩。 ①、考核方式 A、上级分管领导对经理进行考核，评分权重占60%、40%。 B、上级分管领导和经理对主管进行考核，评分权重各占40%、40%、20%。 C、经理和主管对部门员工进行考核，评分权重各占40%、40%、20%。 ②、考核内容 A、工作计划的完成情况（80分） B、综合能力(10分) C、工作态度（10分） ③、绩效考核的等级分类及指导原则 A、等级分类 优秀：非常出色。考评得分：90分以上；
STM32延时函数
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人力资源管理工作存在问题与改进建议(百度文库)
人力资源管理存在问题与改进建议为了确保公司发展战略和年度经营目标的实施，贯彻并落实公司节约人力成本、提高工作效率、强化服务意识，打造一支“务实高效”团队的工作思路和要求，切实做好人力资源管理工作。2012年度人力资源管理工作应从以下几个方面开展： 一、围绕公司的发展战略和2012年度销售目标，对公司的组织构架进 行梳理与整合。 ●存在问题： 1、现有部门较多，部门职责存在相互交叉或重叠； 2、工作流程不畅，公司整体工作效率不高。 ●改进建议： 1、公司应本着“开源节流”的原则，对现有公司各部门工作进 行分析，据此对组织架构进行整合、优化。即对部门工作情 况进行工作分析和评估，对达不到工作成效的部门进行撤并， 对相应人员编制进行压缩和精减，如人事、行政、财务、企 划、项目部等。对直接创造效益的部门进行优化，适当增加 相应的人员编制，如销售、产品及技术支持等部门。 2、梳理部门工作流程，本着合理、简化及提高效率的原则，制 定部门工作流程和部门之间的无缝衔接，使部门与部门工作 之间不存在脱节，从而提高公司工作的整体效率。 二、做好部门内各岗位工作分析，梳理工作关系，明确各岗位的岗位职 责，制定工作标准程序（SOP）和工作流程。
存在问题： 1、有些部门岗位人员工作量不饱和，工作的积极性缺乏； 2、一些部门内部工作分工过细，部门人员之间缺乏团队协作 精神，出现有些岗位忙，有些岗位闲，工作量分布不均衡； 3、岗位缺乏工作标准程序（SOP），新员工入职不能很快进入 工作状态，效率不高。 改进建议： 1、进行岗位工作分析和评估，将相关联的岗位和工作量不饱和 的岗位进行合并，压缩部门人员编制，压缩后的岗位适当调整 薪资。 2、将多余的人员剥离出来，进行相应的调整或转岗，充实销售 部一线人员。从而在整个公司里形成一种无形的工作压力，促 使现有人员具有紧迫感，进而提高员工的工作效率。 3、制定各岗位的工作标准程序文件（SOP），这样不管哪个岗位 人员离职，通过简单的培训，很快进入工作状态，不会造成工 作脱节，影响工作效果。 三、加强对用人部门招聘岗位的评估、测评工具的使用，避免招聘的盲 目性和随意性。 ●存在问题： 1、最近一个时期公司人员变动大，需求部门缺乏对岗位做认 真的工作分析，有些部门存在编制不合理，缺乏统筹考虑， 也是造成现有人员工作量不足的原因之一；
单片机C延时时间怎样计算
C程序中可使用不同类型的变量来进行延时设计。经实验测试，使用unsigned char类型具有比unsigned int更优化的代码，在使用时 应该使用unsigned char作为延时变量。以某晶振为12MHz的单片 机为例，晶振为12M H z即一个机器周期为1u s。一. 500ms延时子程序 程序: void delay500ms(void) { unsigned char i,j,k; for(i=15;i>0;i--) for(j=202;j>0;j--) for(k=81;k>0;k--); } 计算分析: 程序共有三层循环 一层循环n:R5*2 = 81*2 = 162us DJNZ 2us 二层循环m:R6*(n+3) = 202*165 = 33330us DJNZ 2us + R5赋值 1us = 3us 三层循环: R7*(m+3) = 15*33333 = 499995us DJNZ 2us + R6赋值 1us = 3us
循环外: 5us 子程序调用 2us + 子程序返回2us + R7赋值 1us = 5us 延时总时间 = 三层循环 + 循环外 = 499995+5 = 500000us =500ms 计算公式:延时时间=[(2*R5+3)*R6+3]*R7+5 二. 200ms延时子程序 程序: void delay200ms(void) { unsigned char i,j,k; for(i=5;i>0;i--) for(j=132;j>0;j--) for(k=150;k>0;k--); } 三. 10ms延时子程序 程序: void delay10ms(void) { unsigned char i,j,k; for(i=5;i>0;i--) for(j=4;j>0;j--) for(k=248;k>0;k--);
现场管理的现状及改善
论我国企业生产现场管理的现状及改善 随着我国踏入WTO的大门，市场竞争已呈现出全方位、全球化的态势，不少企业在各种竞争中纷纷落马，幸存企业的利润空间也大幅度缩水，不具备竞争优势者即被淘汰已成铁的定律。现今我国的企业，实际上已面临管理差距或管理落后的严峻挑战，企业如果还只注重短期利益，竞争力只会越来越弱，所以企业应将眼光放在长期利益上，才能永续经营，也就是必须始终以质量为中心进行经营，才能达此目标，在质量活动中加强现场管理是根本。企业要提高生产力、降低成本，持续挖掘内部潜力，树立竞争优势的关键管理途径。就必须将目光投到企业的现场管理中来，本文拟对目前我国企业的现场管理的现状进行分析，并提出科学的改进方法。 在社会逐步进入信息时代，知识经济和现代化管理成为发展主流的今天，企业之间的竞争变得异常激烈，市场经济日益发展，市场竞争日趋激烈，产品和服务的质量、生产成本和交货期已成为企业竞争成败的重要条件，稳定保持产品质量已日益成为企业在市场竞争中取胜的法宝。优胜劣汰的客观规律决定了企业生存主要取决于两个因素：一个是市场/产品，一个是管理。质优价廉的产品是在现场（设计现场、生产现场、销售现场）形成和实现的，这已形成了共识，所以市场/产品在很大程度上也依赖于管理。因此，卓越的产品质量必须通过对现场进行科学、细致的管理才能实现。 一、现场管理的含义及重要性 1、现场和现场管理的含义 所谓现场，就是指企业为顾客设计、生产和销售产品和服务以及与顾客交流的地方、现场为企业创造出附加值，是企业活动最活跃的地方。例如制造业，开发部门设计产品，生产部门制造产品，销售部门将产品销售给顾客。企业的每一个部门都与顾客的需求有着密切的联系。从产品设计到生产及销售的整个过程都是现场，也就都有现场管理，这里我们所探讨的侧重点是现场管理的中心环节--生产部门的制造现场，但现场管理的原则对其他部门的现场管理也都是适用的。 我们学过《管理学原理》这门课，都知道关于管理的定义有很多种说法，要是我们从现场管理的角度来看，管理就是一个组织为了实现自己的经营目标，有效地利用所拥有的资源，有计划、高效率地进行运作所采取的措施，它对生产的范围、时间、进度等各个方面进行规范，设置目标，把握进程的时间情况，为完成目标寻求最好的方法所实施的行动。所以现场管理就是设置目标、编制实施计划，充分地利用人、物、设备等物资去实现既定的目标。 前面提到企业要及时为顾客提供质量好的产品，当然，好的产品和服务还应具备价格的竞争力，满足顾客的价格要求，这就需要企业不断的降低成本，而降低成本与现场管理也有着密不可分的关系。回溯到２０世纪７０年代，那时的日本已能制造出比欧美国家更好的照相机了，成本只是其一半。现在，日本产品仍然是优良品质的代名词，这是日本企业低成本的改善方法、良好的环境维持、消除不良品以及标准化作业方式的结果，同时也是现场管理的结果。 现场管理是现代企业管理的有机组成部分,它是运用科学的管理思想、管理方式，对生产现场的各种要素进行合理配置和优化组合的动态过程。企业的管理活动同人的生命活动是一样的，投入的资源可以看成是人的骨骼，消化系统，大脑等，结果就是输出。如面部表情、手足的运动能力、知识能力和人的魅力等等，而最终的输出结果就是人所取得的业绩。在我们日常生活中，为了使身体保持良好的状态，就要摄取营养，注意休息，还要进行适度的活动，自我保健等等。人身体的各种器官只有都处于良好的状态下才能保证人的各人生理功能实现，如果哪一个器官出了问题，就会给整个身体造成威胁，甚至会导致死亡。 2、现场管理的重要性
delay延时教程
delay延时教程（用的是12MHz晶振的MCS-51） 一、 1)NOP指令为单周期指令 2)DJNZ指令为双周期指令 3)mov指令为单周期指令 4)子程序调用（即LCALL指令）为双周期指令 5)ret为双周期指令 states是指令周期数， sec是时间,=指令周期×states，设置好晶振频率就是准确的了 调试>设置/取消断点”设置或移除断点，也可以用鼠标在该行双击实现同样的功能 二、编程最好： 1.尽量使用unsigned型的数据结构。 2.尽量使用char型，实在不够用再用int，然后才是long。 3.如果有可能，不要用浮点型。 4.使用简洁的代码，因为按照经验，简洁的C代码往往可以生成简洁的目标代码（虽说不是在所有的情况下都成立）。 5.在do…while，while语句中，循环体内变量也采用减减方法。 三、编辑注意： 1、在C51中进行精确的延时子程序设计时，尽量不要或少在延时子程序中定义局部变量，所有的延时子程序中变量通过有参函数传递。 2、在延时子程序设计时，采用do…while，结构做循环体要比for结构做循环体好。 3、在延时子程序设计时，要进行循环体嵌套时，采用先内循环，再减减比先减减，再内循环要好。 四、a:delaytime为us级 直接调用库函数： #include
影响工作效率的现象和原因分析及如何改进提高工作效率
影响工作效率的现象和原因分析及如何改进提高工作效率 一、工作效率低的现象因素表现形式： 1、重复劳动、重复工作； 2、推诿扯皮； 3、以制度为挡箭牌，以开会、没时间等为理由； 4、工作计划不分主次，抓不住主要矛盾和主要工作，眉毛胡子一把抓，做事事倍功半； 5、缺乏团队合作精神，只顾自己，不顾别人 6、不会沟通，不会交流； 7、牢骚、抱怨、怪话、散布负能量的话； 8、看待问题简单化，只注重眼前，不能长远的看问题； 9、专业知识和技能不熟练，做事找不到方向，老虎啃天，无从下口，个人执行能力差； 10、工作氛围差，积极向上的正气少，歪风邪气占了上风，唯利是图多，追求少； 11、工作方法、管理方法简单粗暴，团队没有向心力、凝聚力，领导缺乏号召力； 12、没有责任感，缺乏敬业的工作精神和工作的激情，消极、悲观情绪有时主导自己； 13、工作中不能尊重别人，并抱怨别人不能尊重自己； 14、个人的素质、素养尚需提高，做人做事要求别人高，而放低对自己的要求标准，正如老辈讲的只许州官放火，不许百姓点灯； 15、职能服务不足，企业宣传不够； 16、生活和工作不能有效的分开，而是相互的影响，让自己的注意力不能集中； 17、客观方面的影响：电脑配置低，缺少工作方法和提高效率的培训；
A.微信群 B.手机提醒功能 C.即时贴 D.例行工作的时时提醒 E.电脑知识的匮乏，不懂信息万事难 F.工作职责，业务管理的不清 18、领导不能以身作则，起不到榜样的引导作用； 二、如何来改进提高工作效率 1、对照以上18条现象，进行自我对照，自我检查和改进，拿出整改计划； 2、变要我做为我要做，人力资源部在本月拿出2016年考核激励政策初步政策导向方案，最大化激发各级员工的工作主动性； 3、进一步推动集团行政职能部门服务提升工作，变现在各部门提意见和建议为人力、财务、后勤、房地产公司、家纺管理事业部，自己制定2016年职能服务项目及提高计划和激励政策的报告，在本月完成报慈总和周助理。 4、工作职能和岗位职责进一步明晰、各部门可将工作中最细节的职责不清晰的方面发给人力李部长，由人力资源部进行明确职责； 5、各级领导特别是各子公司、事业部的最高领导必须要以身作则，给员工树立好的榜样作用，提升自己的沟通艺术，避免管理的简单粗暴，营造良好的部门工作氛围，建立正能量的积极情绪，人力下周对各子公司、事业部负责人要进行民主测评。 6、推行提高工作效率活动。
单片机几个典型延时函数
软件延时：（asm） 晶振12MHZ,延时1秒 程序如下： DELAY:MOV 72H,#100 LOOP3:MOV 71H,#100 LOOP1:MOV 70H,#47 LOOP0:DJNZ 70H,LOOP0 NOP DJNZ 71H,LOOP1 MOV 70H,#46 LOOP2:DJNZ 70H,LOOP2 NOP DJNZ 72H,LOOP3 MOV 70H,#48 LOOP4:DJNZ 70H,LOOP4 定时器延时： 晶振12MHZ,延时1s，定时器0工作方式为方式1 DELAY1:MOV R7,#0AH ;;晶振12MHZ，延时0.5秒 AJMP DELAY DELAY2:MOV R7,#14H ;;晶振12MHZ，延时1秒DELAY:CLR EX0 MOV TMOD,#01H ;设置定时器的工作方式为方式1 MOV TL0,#0B0H ;给定时器设置计数初始值 MOV TH0,#3CH SETB TR0 ;开启定时器 HERE:JBC TF0,NEXT1 SJMP HERE NEXT1:MOV TL0,#0B0H MOV TH0,#3CH DJNZ R7,HERE CLR TR0 ;定时器要软件清零 SETB EX0 RET
C语言延时程序： 10ms延时子程序（12MHZ）void delay10ms(void) { unsigned char i,j,k; for(i=5;i>0;i--) for(j=4;j>0;j--) for(k=248;k>0;k--); } 1s延时子程序（12MHZ）void delay1s(void) { unsigned char h,i,j,k; for(h=5;h>0;h--) for(i=4;i>0;i--) for(j=116;j>0;j--) for(k=214;k>0;k--); }
培训现状及改进措施
培训现状及改进思路 通过一天的培训，好不夸张的说，触目惊心，没有见过培训是这么进行的。一个培训的进行，尤其是岗前培训，对于一个新员工的归属感和认同感起着非常重要的作用。具体来说，主要包含以下问题存在： 1、培训资源分散，协调配合效率低。培训组织实施比较被动。因为讲师都是由公司领导担任，而领导的时间又很难把握，所以难免会造成临时没时间的情况，这样以来，就存在临时拼凑老师的现象。而拼凑来的老师对课件不熟悉，讲课内容和时间都难以控制。 2、培训部门规范度不够。比如讲师的统一性、课件的统一性等。 3、培训讲师的专业度不够，缺乏相关的讲师管理制度。 4、培训课题较多，且存在重复性讲解。不同的讲师讲解的知识有重复性。 5、培训形式单一，互动性不强，学员难免有疲劳感，影响培训效果。 6、培训的深度不够，每个模块没有展开来讲。 7、培训没有相关的考核，培训效果难以追踪。 由于这些问题的存在，导致培训工作名存实亡。岗前培训的目的本是让新员工认同这个行业、认同这个企业，从而在以后的工作中更加具有积极主动性，有一种企业荣誉感。而如果
岗前培训照此进行下去，参训学员听完一头雾水，在客户那里甚至不能更好的介绍自己的企业。
基于此，遵照轻重缓急的原则，建议目前阶段的改进措施如下： 1、减少培训课题，建议岗前培训阶段保留企业文化培训、行业知识（含产品介绍）和行政人事制度三项内容。 2、培训部门统一安排培训，包括培训课件的制作、讲解、培训的组织实施。但是行业知识这一项由业务部门精英负责讲解。 3、增加培训后测试，对学员的培训效果进行跟踪。 当然，培训的顺利进行不仅仅是培训部门的事情，需要公司领导及兄弟部门的支持与配合，包括培训的宣传，资料的提供等。培训完善不会是一蹴而就，还需要相关配套制度及考核的支持，此问题待以后再做进一步完善。 培训部 二0一五年十二月二十三日如有侵权请联系告知删除，感谢你们的配合！
浅谈提高工作效率
浅谈提高工作效率 概念 工作效率，一般指工作投入与产出之比，通俗地讲就是在进行某任务时，取得的成绩与所用时间、精力、金钱等的比值。产出大于投入，就是正效率；产出小于投入，就是负效率。工作效率是评定工作能力的重要指标。提高工作效率就是要求正效率值不断增大。一个人的工作能力如何，很大程度上看工作效率的高低。 意义 1、提高工作效率可以增加二者利益。即有利于单位的劳动生产率和经济效益的提高，增加活力；有利于工作人员个人实现多劳多得，增加收入。 2、提高工作效率以后，就可缩短工作时间，从而有更多的时间让员工自行支配，去从事学习、娱乐、旅游、社交和休息。 3、提高工作效率以后，可以克服机构臃肿，人浮于事，浪费时间的现象。 4、提高工作效率之后，在优化劳动组合中，具有更大的竞争优势。 提高工作效率的方法 1、保持最佳的工作激情。工作激情也可以说是工作意愿，就是想不想做，想不想又好又快的做，是积极主动、认真负责的工作，还是敷衍了事、拖拖拉拉的工作，两种截然不同的心态，使得工作效率的具体表现也大相径庭，因此工作激情成为提高工作效率的首要，就是说提高和保持工作激情是提高工作效率的前提。 2、选择正确的工作方向。工作方向就是工作目标或工作目的，是一切工作的源头和指导，我们可以选择不同的工作方向，但是正确的工作方向只有一个，一旦选错了工作方向，工作效率将无从谈起，或者说劳民伤财、徒劳无功，对企业、对个人带来的只有损失，因此工作之前，一定要慎重选择、辨认正确。 3、选择最好的工作方法。做任何工作都有各种方法可以选择，也许也都可以殊途同归。就像解数学题，方法有多种，既然同样可以得出答案，那么你会选择什么方法呢？自然是最简便的。这样，才可以有更多的时间解其他难题，才能保证试卷的质量。同理，找到最好的方法就能为我们节约不必要的时间的浪费。所以，在工作前，请认真思考什么才是最好的方法，“磨刀不费砍柴工”说的就是这个。 4、工具的选择和使用。“工欲善其事，必先利其器”，选择好的工具能使得事半功倍，而工具的使用就要求我们不懂莫装懂，能够虚心请教他人。自己懂的，也能不因自己的私利而无视工作同伴的求教，毕竟，每个工作都不是仅凭个人能力就能完成的。工作本是一个集体项目，愉快的合作才能提高效率。 5、懂得劳逸结合。无论学习还是工作，劳逸结合是很重要的，它能使人事半功倍。如果为工作操劳过度，影响的不仅仅是身体的健康，也会伴随工作效率的降
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