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M13S128168A-5T中文资料

Revision History

Revision 0.1 (15 Jan. 2002)

- Original

Revision 0.2 (19 Nov. 2002)

-changed ordering information & DC/AC characteristics

Revision 0.1 Revision 0.2

M13S128168A - 5T M13S128168A - 6T

M13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)

-Change IDD6 from 3mA to 5mA.

Revision 0.4 (27 Aug. 2003)

-Change ordering information & DC / AC characteristics.

Revision 1.0 (21 Oct. 2003)

-Modify tWTR from 2tck to 1tck.

Revision 1.1 (10 Nov. 2003)

-Correct some refresh interval that is not revised.

-Correct some CAS Lantency that is not revised.

Revision 1.2 (12 Jan. 2004)

-Correct IDD1; IDD4R and IDD4W test condition.

-Correct tRCD; tRP unit

-Add tCCD spec.

-Add tDAL spec.

Revision 1.3 (12 Mar. 2004)

-Add Cas Latency=2; 2.5

Revision 1.4 (23 Jun. 2005)

-Add Pb-free to ordering information

-Modify IDD0 and IDD1 spec

-Modify some AC timing unit from tCK to ns.

Revision 1.5 (29 May. 2006)

-Delete CL2 ; CL2.5

-Modify tREFI

-Delete Non-pb-free form ordering information

Revision 1.6 (3 Jan. 2007)

-Add CL2.5

Revision 1.7 (12 Apr. 2007)

-Add BGA package

Revision 1.8 (01 Jun. 2007)

-Delete CL 2.5

DDR SDRAM 2M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Features

z JEDEC Standard

z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL

z Differential clock inputs (CLK and CLK )

z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 3

z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8

z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS)

z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z V DD = 2.375V ~ 2.75V, V DDQ = 2.375V ~ 2.75V z Auto & Self refresh

z 15.6us refresh interval (64ms refresh period, 4K cycle) z SSTL-2 I/O interface z

66pin TSOPII package

Ordering information :

PRODUCT NO. MAX FREQ VDD

PACKAGE

COMMENTS M13S128168A -5TG 200MHz Pb-free M13S128168A -6TG 166MHz 2.5V TSOPII

Pb-free M13S128168A -5BG 200MHz Pb-free M13S128168A -6BG

166MHz

2.5V BGA

Pb-free

Functional Block Diagram

Pin Arrangement

DQS

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 PIN TSOP(II)

(400mil x 875mil) (0.65 mm PIN PITCH)

V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N C

V DDQ LDQS N C

V DD N C LDM WE CAS RAS CS

N C BA0 BA1

A10/A P A0

V DD

V SS

DQ15

V SSQ

DQ14

DQ13

V DDQ

DQ12

DQ11

V SSQ

DQ10

DQ9

V DDQ

DQ8

N C

V SSQ

UDQS

N C

V REF

V SS

UDM

CLK

CKE

N C

A11

V SS 66

x16 x16

60 Ball BGA

Pin Description

(M13S128168A)

Absolute Maximum Rating

Unit

Value

Parameter Symbol

Voltage on any pin relative to V SS V IN, V OUT-0.5 ~ 3.6 V

Voltage on V DD supply relative to V SS V DD, V DDQ-1.0 ~ 3.6 V

Voltage on V DDQ supply relative to V SS V DDQ-0.5 ~ 3.6 V

Storage temperature T STG-55 ~ +150 C

Power dissipation P D TBD W

Short circuit current I OS 50 mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operation Condition & Specifications

DC Operation Condition

Recommended operating conditions (Voltage reference to V SS = 0V, T A = 0 to 70C

°)

Notes 1. V REF is expected to be equal to 0.5* V DDQ of the transmitting device, and to track variations in the DC level of the same.

Peak-to-peak noise on V REF may not exceed 2% of the DC value.

2. V TT is not applied directly to the device. V TT is system supply for signal termination resistors, is expected to be set equal

to V REF, and must track variations in the DC level of V REF .

3. V ID is the magnitude of the difference between the input level on CLK and the input level on CLK.

DC Specifications

Note 1. Enable on-chip refresh and address counters.

AC Operation Conditions & Timing Specification

2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the

same.

Input / Output Capacitance

(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A = 25C

°, f = 1MHz)

AC Operating Test Conditions

Parameter Value Unit Input reference voltage for clock (V REF ) 0.5*V DDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate

1.0

V/ns

Input levels (V IH /V IL ) V REF +0.31/V REF -0.31 V Input timing measurement reference level V REF V Output timing reference level V TT V

AC Timing Parameter & Specifications

(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A =0C ° to 70C °)(Note)

AC Timing Parameter & Specifications-continued

-5 -6 Parameter Symbol

min max min max Half Clock Period t HP t CL min or t CH min- t CL min or t CH min - ns

DQ-DQS output hold

time

t QH t HP-0.45 - t HP-0.5 - ns

ACTIVE to PRECHARGE command t RAS40 120Kns 42 120Kns

Row Cycle Time t RC60 - 60 -

AUTO REFRESH Row Cycle Time t RFC70 - 72 -

ACTIVE to READ,WRITE delay t RCD18 - 18 -

PRECHARGE command period t RP18 - 18 -

ACTIVE to READ with

AUTOPRECHARGE command t RAP 18 120K 18 120K

ACTIVE bank A to ACTIVE bank B command t RRD10 - 12 -

Write recovery time t WR 2 - 2 -

t CK

Write data in to READ command delay t WTR 1 - 1 -

t CK

Col. Address to Col. Address delay t CCD 1 - 1 -

t CK

Average periodic refresh interval t REFI - 15.6 - 15.6

Write preamble t WPRE0.25 - 0.25 -

t CK Write postamble t WPST0.4 0.6 0.4 0.6

t CK DQS read preamble t RPRE0.9 1.1 0.9 1.1

t CK DQS read postamble t RPST0.4 0.6 0.4 0.6

t CK

Clock to DQS write preamble setup time t WPRES0 - 0 -

Load Mode Register /

Extended Mode register cycle time t MRD 2 - 1 -

t CK

Exit self refresh to READ command t XSRD200 - 200 -

t CK

Exit self refresh to non-READ command t XSNR75 - 75 -

Autoprecharge write recovery+Precharge time t DAL

(t WR/t CK)

(t RP/t CK)

(t WR/t CK)

(t RP/t CK)

t CK

Command Truth Table

1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 1 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by “Auto”..

Auto/self refresh can be issued only at all banks precharge state.

4. BA0~BA1 : Bank select addresses.

If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.

If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.

If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.

5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t RP after end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

Basic Functionality

Power-Up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)

-Apply VDD before or at the same time as VDDQ.

-Apply VDDQ before or at the same time as V TT & V REF).

2. Start clock and maintain stable condition for a minimun of 200us.

3. The minimun of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.

4. Issue precharge commands for all banks of the device.

*1 5. I ssue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1)

*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.

(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)

*2 7. Issue precharge commands for all banks of the device.

8. Issue 2 or more auto-refresh commands.

9. Issue a mode register set command with low to A8 to initialize device operation.

*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6 & 7 is regardless of the order.

Mode Register Definition

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.

Bus BA1 BA0 A11 A10A9 A8 A7A6A5A4A3A2A1 A0 Address

Burst Address Ordering for Burst Length

Burst Length Starting

Address (A2, A1,A0)

Sequential Mode Interleave Mode xx0 0, 1 0, 1 2

xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4

x11 3, 0, 1, 2

3, 2, 1, 0

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

DLL Enable / Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S128168A also support a weak drive strength option, intended for lighter load and/or point-to-point environments.

Mode Register Set

Extended Mode Register Set (EMRS)

The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

*QFC is not used; don’t care.

Precharge

The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, t WR(min.) must be satisfied until the precharge command can be issued. After t RP from the precharge, an active command to the same bank can be initiated.

Burst Selection for Precharge by Bank address bits

A10/AP BA1 BA0 Precharge

Only

Bank

0 0 0

Only

Bank

0 0 1

Only

Bank

0 1 0

Only

Bank

0 1 1

All

Banks

1 X X

NOP & Device Deselect

The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued.

Row Active

The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t RCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD min).

Read Bank

This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS, CAS, and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.

Write Bank

This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS, CAS, and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.

Essential Functionality for DDR SDRAM

Burst Read Operation

Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t RCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed.

Burst Write Operation

The Burst Write command is issued by having CS, CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins t DS (Data-in setup time) prior to data strobe edge enabled after t DQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.

Read Interrupted by a Read

A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.

Read Interrupted by a Precharge

A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.

When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.

1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the

rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after t RP (RAS precharge time).

2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge

which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after t RP.

3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after t RP where t RP

begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.

During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.

4. For all cases above, t RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a

Precharge command and a new Bank Activate command to the same bank equals t RP / t CK (where t CK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles.

In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where t RAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.

Write Interrupted by a Write

A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.

The following functionality establishes how a Write command may interrupt a Read burst.

1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst

and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].

2. It is illegal for a Write command to interrupt a Read with autoprecharge command.