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Depth-dependent etch pit density in Ge epilayer

Depth-dependent etch pit density in Ge epilayer on Si substrate with a self-patterned Ge coalescence island template

Shihao Huang a ,Cheng Li a ,d ,?,Zhiwen Zhou b ,Chengzhao Chen a ,c ,Yuanyu Zheng a ,Wei Huang a ,Hongkai Lai a ,Songyan Chen a

Department of Physics,Semiconductor Photonics Research Center,Xiamen University,Xiamen,Fujian 361005,People's Republic of China

b Department of Electroni

c Communication Technology,Shenzhen Institute of Information an

d Technology,Shenzhen,Guangdong 518029,People's Republic of China c

Department of Physics and Electronics Engineering,Hanshan Normal University,Chaozhou 521041,People's Republic of China d

State Key Laboratory of Functional Materials for Informatics,Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences,865Changning Road,Shanghai 200050,People's Republic of China

a b s t r a c t

a r t i c l e i n f o Article history:

Received 1March 2011

Received in revised form 8September 2011Accepted 13September 2011Available online xxxx

Keywords:Ge-on-Si

Dislocation density

Ge coalescence island template

Ge epilayer with low dislocation density is prepared on a low temperature self-patterned Ge coalescence is-land template on Si substrate by ultra-high vacuum chemical vapor deposition.The depth pro ?le of disloca-tion density in the Ge epilayer measured by etch-pit counting indicates that the dislocation density decreases drastically when the thickness of Ge layer is larger than 270nm,and then depends weakly on the further in-crease of Ge thickness.The reduction of dislocations is ascribed to the Ge islands coalescence and lateral growth during deposition of Ge at higher temperature.1.05-μm-thick Ge epilayer on Si with a dislocation density of the order of 106cm ?2and root-mean-square surface roughness of 0.45nm are achieved without any additional thermal treatments.

1.Introduction

As germanium (Ge)is being investigated to be integrated into the future complementary metal-oxide semiconductor and photonic de-vices,Ge-on-Si substrates have attracted much interests for their compatibility with Si process ?ow and scarce source of germanium in the world [1,2].However,the natural large lattice mismatch (4.18%)between Ge and Si always causes high dislocation density in Ge epilayer directly on Si substrate.In the past decades,several methods have been proposed to make Ge epilayer on Si substrate with a low threading dislocation density (TDD),such as using compo-sitionally graded SiGe buffer layer [3–6],two thin SiGe buffer layers [7,8],surfactant-mediated epitaxy [9,10],selective area epitaxy [11,12],and low and high temperature two-step growth approach combined with thermal annealing [13,14].The lowest dislocation density in Ge epilayer of about 2.1×106cm ?2has been achieved with compositionally graded SiGe buffer layer and selective epitaxy approaches [3,11].However,10-μm-thick graded SiGe buffer layer is required to reach such a low dislocation density and the process of se-lective epitaxy is complex.

The two-step growth process is perspective in preparing Ge epilayer on Si substrate with a low temperature Ge (LT-Ge)seed layer.The main viewpoint is that the thin Ge layer is ?rst grown on Si at low

temperature to relieve the stress induced by the lattice mis ?t between Ge and Si and hamper three dimensional islands growth.And then the Ge epilayer is grown on the ?at Ge template at high temperature to im-prove crystal quality of Ge for device applications.The surface of the Ge ?lm is quite smooth and the root-mean square surface roughness (RMS)is less than 1nm.However,TDD is found to be extremely high,close to 1×109cm ?2[13,14].Thermal annealing has to be carried out to reduce the TDD.The TDD of 2×107cm ?2in a 1-μm-thick Ge epilayer after a ten time {780°C ,10min/900°C ,10min}cyclic thermal annealing [13]and 6×106cm ?2in a 2.5-μm-thick Ge layer after an eight time {750°C ,10min/900°C ,10min}cyclic thermal annealing [14]are reported.However,thermal anneal at high temperature has been prov-en to induce out-diffusion of Si from the substrate towards the surface of the Ge layer [14].

In those studies,it was found that TDD depends strongly on the thickness of Ge epilayer.Several theoretical models have been proposed to predict the TDD dependence on epilayer thickness in the large lattice-mismatched heteroepitaxial systems [15–21].The reaction model [17–20]predicts that TDD is inversely proportional to ?lm thickness,which works well for some GaAs or Ge epitaxial ?lms on Si.The thermodynam-ic model developed by Wang et al.[21]predicts that TDD scales down with ?lm thickness in a square law,which is in good agreement with some experimental results on Ge and GaAs ?lms on Si.In these models,the role of buffer layer in reducing TDD has not been considered due to its complexity.

In this work,a low temperature self-patterned Ge coalescence island template is proposed to fabricate a low dislocation density Ge epilayer

Thin Solid Films xxx (2011)xxx –xxx

?Corresponding author at:Department of Physics,Semiconductor Photonics Research Center,Xiamen University,Xiamen,Fujian 361005,People's Republic of China.

E-mail address:lich@https://www.wendangku.net/doc/2610216227.html, (C.Li).

TSF-29818;No of Pages 4

Contents lists available at SciVerse ScienceDirect

Thin Solid Films

j o u r n a l h o me p a g e :w ww.e l se v i e r.c om /l oc a te /ts f

on Si substrate.The dependence of dislocation density on thickness of Ge epilayer is investigated by counting etch pit density(EPD),and high-resolution transmission electron microscopy(HRTEM).We?nd that the depth pro?le of etch pit density deviates from the general the-oretical prediction and the possible mechanism for reducing TDD in the Ge epilayer grown on Ge coalescence island template is discussed.

2.Experimental details

The samples were prepared on10-cm-diameter n-type(001)Si wafers with a resistivity of0.1–1.2Ω.cm by a cold-wall ultrahigh vacuum chemical vapor deposition system,with a base pressure of 5×10?8Pa.After standard RCA(Radio Corporation of American) etching and thermal cleaning of the silicon substrate at850°C for 30min,a300-nm-thick Si buffer layer was grown at750°C.And then a low temperature Ge(LT-Ge)coalescence island template was grown at330°C with a growth rate of0.5nm/min(labeled as sample A).The nominal thickness of the LT-Ge layer is designed to be about90nm,at which the compressive strain in the Ge coalescence islands is almost fully relaxed,as evaluated by Raman spectroscopy. On the LT-Ge coalescence island template,240-nm-thick and960-nm-thick Ge layers were grown at630°C with a growth rate of 2.1nm/min for samples B and C,respectively.The thickness of Ge layer was measured by surface pro?le after selectively pattern etching and con?rmed by TEM measurements.The surface morphologies of the samples were analyzed by atomic force microscopy(AFM)in a tap-ping mode.The depth pro?le of threading dislocation density is mea-sured by etch-pit counting.

3.Results and discussion

Fig.1(a)and(b)shows depth pro?le of TDD in the Ge epilayer on Si substrate and several typical optical images at various depths in sample C after etched by I2solution(HF:HNO3:CH3COOH:I2= 10ml:40ml:100ml:30mg)for EPD counting[13,22].Each dislo-cation density is an average value by counting etch pits in4–6

pictures across the surface and only one typical picture is displayed. All the etching experiments were done on the same piece.It is found that TDD weakly depends on etch depth until the removed Ge layer is up to780nm and only the size of the etch pit becomes larger with increasing etch depth.The typical TDD is in a range of 9.5×105cm?2–1.2×106cm?2.Further increasing etch depth,the TDD begins to increase quickly,up to larger than1×108cm?2(limita-tion of EPD method).Those results evidence that the dislocations should thread from the underlayer rather than nucleate in the high temperature Ge(HT-Ge)layer,and then amount of them annihilate in a region at the beginning of the HT-Ge layer.This observation is differ-ent from the theoretical predicted inversely proportional law or square law of TDD downscaling with?lm thickness[15–21].We also notice that TDD in a1-μm-thick Ge epilayer grown by reduced pressure chem-ical vapor depostion is in the range of107cm?2–108cm?2,even after thermal annealing,which is in good agreement with the theoretical model.[13,14]What differences are that the?at LT-Ge templates were used in the samples reported in Ref.[13]and Ref.[14].In the the-oretical models,the roles of coalescence islands in the buffer layer are not included.The application of LT-Ge coalescence island template might be responsible for the behavior in reduction of TDD with?lm thickness in our samples.

Fig.2shows cross-sectional HRTEM images of sample C.Although we cannot evaluate the exact TDD by HRTEM for its localized view, the TDD distribution can still be outlined by analyzing HRTEM images. It can be seen that most of mis?t dislocations are con?ned at the LT-Ge and Si interface as shown in the inset.Some of them thread up-ward and generate threading dislocations and then some of the threads meet and annihilate in a region at the beginning of the HT-Ge layer, which is in fair agreement with the EPD measurements.This behavior is very likely due to the annihilation of dislocations in lateral growth mode observed in the other material system with large lattice mis-match,such as GaN,and others[23].

The observation of TDD distribution in Ge epilayer suggests that the growth of HT-Ge on LT-Ge coalescence island template may be re-lated to the lateral growth mode.In order to verify our conjecture on the growth behavior,the morphology evolution of samples A,B and C with increasing Ge thickness is measured by AFM As shown in Fig.3

Fig.1.(a)Depth pro?le of TDD in Ge epilayer on Si substrate,(b)Schematic and optical images of sample C etched at various depths to reveal etch pit density.

20nm Si Sub.

Fig.2.Cross-sectional images of HRTEM of sample C.The generation of mis?t disloca-tions at Ge/Si interface is shown in the inset.

2S.Huang et al./Thin Solid Films xxx(2011)xxx–xxx

The coalescence islands are clearly observed in sample A with nominal 90-nm-thick LT-Ge layer.The undulation scale of the Ge coalescence islands is about 104.7nm and RMS is about 16.7nm.After the growth of 240nm and 960nm HT-Ge layer,the surface becomes smooth and

the RMS is reduced to about 2.0nm and 0.45nm for samples B and C,respectively.The evolution of morphology of the Ge epilayer on Si from Ge coalescence islands to smooth ?lms has been demonstrated with increasing thickness of Ge epilayer.

With those experimental data,a model to grow Ge epilayer on Si with a low TDD is proposed,as schematically shown in Fig.4.When the Ge epilayer is grown at relatively lower temperature on Si sub-strate,large self-organized Ge islands are formed due to 4.18%lattice mismatch between Si and Ge.During this process,the formation of self-organized islands and the generation of mis ?t dislocations at the interface between Si and Ge completely relieve the compressive strain in the LT-Ge layer when the thickness reaches a certain value (here is 90nm).The arms of some mis ?t dislocations thread upwards to generate original high density threading dislocations.The Ge islands coalesce to provide a fully relaxed Ge template.At the begin-ning of the HT-Ge deposition,the further coalescence or lateral growth of Ge islands due to the enhanced migration of Ge atoms in-duces the bending of threading dislocations giving rise to the reduc-tion in TDD density as the bent-over dislocations meet and annihilate.The bending and annihilation of threading dislocation might be related to the multiple small crystal surfaces on the Ge islands,which need further investigation.Once the TDD drops to a critical value,the interaction between neighboring dislocations be-comes negligible for the long distance between them.The TDD will be slightly affected by increasing thickness of HT-Ge layer.Thus,the drastic reduction of TDD in our samples is observed when the thick-ness of Ge layer is larger than 270nm (the thickness may be varied with the size of Ge islands and growth temperature).Above 270nm,the dependence of TDD on thickness of Ge epilayer becomes weak.

4.Conclusion

The dependence of dislocation density on thickness of Ge epilayer on Si has been investigated by etch pit counting and TEM images.The depth pro ?le of dislocation density in the Ge epilayer indicates that threading dislocation density decreases drastically when the thick-ness of Ge epialyer is larger than 270nm.We ascribe the reduction of dislocations to the Ge islands coalescence and lateral growth at high temperature.1.05-μm-thick Ge epilayer on Si with low disloca-tion density of the order of 106cm ?2and root-mean-square surface roughness of 0.45nm are achieved without any additional thermal treatments.

2 μm

nm 104.7

X10

2 μm

nm 10.1

2 μm

2.98

Sample A

Sample B

SampleC

Fig.3.Morphologies of samples A,B,C measured by AFM.The RMS of surface rough-ness is about 16.7nm,2.0nm,0.45nm,respectively.

Fig.4.Schematic illustration on meet and annihilation of dislocations in the epitaxial Ge layer on Si substrate with a low temperature self-patterned Ge coalescence island template.

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Acknowledgments

This work was supported in part by the National Basic Research Program of China under grant no.2012CB933503,the National Natu-ral Science Foundation of China under grant nos.:61036003, 61176092,60837001,the Fundamental Research Funds for the Cen-tral Universities no.2010121056and the Open Project of State Key Laboratory of Functional Materials for Informatics.

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