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AT6005LV-4QC中文资料

Features

?High-performance

–System Speeds > 100 MHz

–Flip-flop Toggle Rates > 250 MHz –1.2 ns/1.5 ns Input Delay –3.0 ns/6.0 ns Output Delay ?Up to 204 User I/Os

?Thousands of Registers ?

Cache Logic ? Design

–Complete/Partial In-System Reconfiguration –No Loss of Data or Machine State –Adaptive Hardware

?Low Voltage and Standard Voltage Operation –5.0 (V CC = 4.75V to 5.25V)–3.3 (V CC = 3.0V to 3.6V)

?Automatic Component Generators

–Reusable Custom Hard Macro Functions ?Very Low-power Consumption

–Standby Current of 500 μA/ 200 μA

–Typical Operating Current of 15 to 170 mA ?

Programmable Clock Options

–Independently Controlled Column Clocks –Independently Controlled Column Resets –Clock Skew Less Than 1 ns Across Chip ?

Independently Configurable I/O (PCI Compatible)–TTL/CMOS Input Thresholds –Open Collector/Tristate Outputs –Programmable Slew-rate Control

–I/O Drive of 16 mA (combinable to 64 mA)

Easy Migration to Atmel Gate Arrays for High Volume Production

Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute-intensive logic.Supporting system speeds greater than 100 MHz and using a typical operating current of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive designs. These FPGAs are designed to implement Cache Logic ?, which provides the user with the ability to implement adaptive hardware and perform hardware acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O.

AT6000 Series Field Programmable Gate Arrays

(continued)

AT6000(LV) Series

Devices range in size from 4,000 to 30,000 usable gates,and 1024 to 6400 registers. Pin locations are consistent throughout the AT6000 Series for easy design migration.High-I/O versions are available for the lower gate count devices.

AT6000 Series FPGAs utilize a reliable 0.6 μm single-poly,double-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based Integrated Develop-ment System is used to create AT6000 Series designs.Multiple design entry methods are supported.

The Atmel architecture was developed to provide the high-est levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, very efficient and contain the most important and most commonly used logic and wiring functions. The cell’s small size leads to arrays with large numbers of cells,greatly multiplying the functionality in each cell. A simple,high-speed busing network provides fast, efficient commu-nication over medium and long distances.

The Symmetrical Array

At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous and completely uninterrupted from one edge to the other,except for bus repeaters spaced every eight cells (Figure 2).

In addition to logic and storage, cells can also be used as wires to connect functions together over short distances and are useful for routing in tight spaces.

The Busing Network

There are two kinds of buses: local and express (see Figures 2 and 3).

Local buses are the link between the array of cells and the busing network. There are two local buses – North-South 1and 2 (NS1 and NS2) – for every column of cells, and two local buses – East-West 1 and 2 (EW1 and EW2) – for every row of cells. In a sector (an 8 x 8 array of cells enclosed by repeaters) each local bus is connected to every cell in its column or row, thus providing every cell in the array with read/write access to two North-South and two East-West buses.

Figure 1.

Symmetrical Array Surrounded by I/O

AT6000(LV) Series

Figure 2. Busing Network (one sector)

Figure 3. Cell-to-cell and Bus-to-bus Connections

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AT6000(LV) Series

Each cell, in addition, provides the ability to route a signal on a 90° turn between the NS1 bus and EW1 bus and between the NS2 bus and EW2 bus.

Express buses are not connected directly to cells, and thus provide higher speeds. They are the fastest way to cover long, straight-line distances within the array.

Each express bus is paired with a local bus, so there are two express buses for every column and two express buses for every row of cells.

Connective units, called repeaters, spaced every eight cells, divide each bus, both local and express, into segments spanning eight cells. Repeaters are aligned in rows and columns thereby partitioning the array into 8 x 8sectors of cells. Each repeater is associated with a local/express pair, and on each side of the repeater are connections to a local-bus segment and an express-bus segment. The repeater can be programmed to provide any one of twenty-one connecting functions. These functions are symmetric with respect to both the two repeater sides and the two types of buses.

Among the functions provided are the ability to: ?Isolate bus segments from one another ?Connect two local-bus segments ?Connect two express-bus segments ?Implement a local/express transfer

In all of these cases, each connection provides signal regeneration and is thus unidirectional. For bidirectional connections, the basic repeater function for the NS2 and EW2 repeaters is augmented with a special programmable connection allowing bidirectional communication between local-bus segments. This option is primarily used to imple-ment long, tristate buses.

The Cell Structure

The Atmel cell (Figure 4) is simple and small and yet can be programmed to perform all the logic and wiring functions needed to implement any digital circuit. Its four sides are functionally identical, so each cell is completely symmetrical.

Read/write access to the four local buses – NS1, EW1,NS2 and EW2 – is controlled, in part, by four bidirectional pass gates connected directly to the buses. To read a local bus, the pass gate for that bus is turned on and the three-input multiplexer is set accordingly. To write to a local bus,the pass gate for that bus and the pass gate for the associ-ated tristate driver are both turned on. The two-input multiplexer supplying the control signal to the drivers per-mits either: (1) active drive, or (2) dynamic tristating controlled by the B input. Turning between L NS1 and L EW1 or between L NS2 and L EW2 is accomplished by turning on the two associated pass gates. The operations of reading, writ-ing and turning are subject to the restriction that each bus can be involved in no more than a single operation.

Figure 4.

Cell Structure

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AT6000(LV) Series

In addition to the four local-bus connections, a cell receives two inputs and provides two outputs to each of its North (N), South (S), East (E) and West (W) neighbors.These inputs and outputs are divided into two classes: “A ”and “B ”. There is an A input and a B input from each neigh-boring cell and an A output and a B output driving all four neighbors. Between cells, an A output is always connected to an A input and a B output to a B input.

Within the cell, the four A inputs and the four B inputs enter two separate, independently configurable multiplexers. Cell flexibility is enhanced by allowing each multiplexer to select also the logical constant “1”. The two multiplexer outputs enter the two upstream AND gates.

Downstream from these two AND gates are an Exclusive-OR (XOR) gate, a register, an AND gate, an inverter and two four-input multiplexers producing the A and B outputs.These multiplexers are controlled in tandem (unlike the A and B input multiplexers) and determine the function of the cell.

?In State 0 – corresponding to the “0” inputs of the

multiplexers – the output of the left-hand upstream AND gate is connected to the cell ’s A output, and the output of the right-hand upstream AND gate is connected to the cell ’s B output.?In State 1 – corresponding to the “1” inputs of the

multiplexers – the output of the left-hand upstream AND gate is connected to the cell ’s B output, the output of the right-hand upstream AND gate is connected to the cell ’s A output.?In State 2 – corresponding to the “2” inputs of the multiplexers – the XOR of the outputs from the two upstream AND gates is provided to the cell ’s A output, while the NAND of these two outputs is provided to the cell ’s B output.

?In State 3 – corresponding to the “3” inputs of the

multiplexers – the XOR function of State 2 is provided to the D input of a D-type flip-flop, the Q output of which is connected to the cell ’s A output. Clock and

asynchronous reset signals are supplied externally as described later. The AND of the outputs from the two upstream AND gates is provided to the cell's B output.

Logic States

The Atmel cell implements a rich and powerful set of logic functions, stemming from 44 logical cell states which per-mutate into 72 physical states. Some states use both A and B inputs. Other states are created by selecting the “1” input on either or both of the input multiplexers.

There are 28 combinatorial primitives created from the cell ’s tristate capabilities and the 20 physical states repre-sented in Figure 5. Five logical primitives are derived from the physical constants shown in Figure 7. More complex functions are created by using cells in combination.A two-input AND feeding an XOR (Figure 8) is produced using a single cell (Figure 9). A two-to-one multiplexer selects the logical constant “0” and feeds it to the right-hand AND gate. The AND gate acts as a feed-through, let-ting the B input pass through to the XOR. The three-to-one multiplexer on the right side selects the local-bus input,LNS1, and passes it to the left-hand AND gate. The A and LNS1 signals are the inputs to the AND gate. The output of the AND gate feeds into the XOR, producing the logic state (A l L) XOR B.

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AT6000(LV) Series

Figure 5. Combinatorial Physical States

Figure 6. Register States

Figure 7. Physical Constants

Figure 8. Two-input AND Feeding XOR

Figure 9. Cell Configuration (A l

L) XOR B

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AT6000(LV) Series

Clock Distribution

Along the top edge of the array is logic for distributing clock signals to the D flip-flop in each logic cell (Figure 10). The distribution network is organized by column and permits columns of cells to be independently clocked. At the head of each column is a user-configurable multiplexer providing the clock signal for that column. It has four inputs:?Global clock supplied through the CLOCK pin ?Express bus adjacent to the distribution logic ?“A ” output of the cell at the head of the column ?Logical constant “1” to conserve power (no clock)Through the global clock, the network provides low-skew distribution of an externally supplied clock to any or all of the columns of the array. The global clock pin is also con-nected directly to the array via the A input of the upper left and right corner cells (AW on the left, and AN on the right).The express bus is useful in distributing a secondary clock to multiple columns when the global clock line is used as a primary clock. The A output of a cell is useful in providing a clock signal to a single column. The constant “1” is used to reduce power dissipation in columns using no registers.Figure 10. Column Clock and Column Reset

Asynchronous Reset

Along the bottom edge of the array is logic for asynchro-nously resetting the D flip-flops in the logic cells (Figure 10). Like the clock network, the asynchronous reset network is organized by column and permits columns to be independently reset. At the bottom of each column is a user-configurable multiplexer providing the reset signal for that column. It has four inputs:

?Global asynchronous reset supplied through the pin ?Express bus adjacent to the distribution logic ?“A ” output of the cell at the foot of the column ?Logical constant “1” to conserve power

The asynchronous reset logic uses these four inputs in the same way that the clock distribution logic does. Through the global asynchronous reset, any or all columns can be reset by an externally supplied signal. The global asynchro-nous reset pin is also connected directly to the array via the A input of the lower left and right corner cells (AS on the left, and AE on the right). The express bus can be used to distribute a secondary reset to multiple columns when the global reset line is used as a primary reset, the A output of a cell can also provide an asynchronous reset signal to a single column, and the constant “1” is used by columns with registers requiring no reset. All registers are reset dur-ing power-up.

Input/Output

The Atmel architecture provides a flexible interface between the logic array, the configuration control logic and the I/O pins.

Two adjacent cells – an “exit ” and an “entrance ” cell – on the perimeter of the logic array are associated with each I/O pin.

There are two types of I/Os: A-type (Figure 11) and B-type (Figure 12). For A-type I/Os, the edge-facing A output of an exit cell is connected to an output driver, and the edge-facing A input of the adjacent entrance cell is connected to an input buffer. The output of the output driver and the input of the input buffer are connected to a common pin. B-type I/Os are the same as A-type I/Os, but use the B inputs and outputs of their respective entrance and exit cells. A- and B-type I/Os alternate around the array Control of the I/O logic is provided by user-configurable memory bits.

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AT6000(LV) Series

Figure 11. A-type I/O Logic Figure 12. B-type I/O Logic

TTL/CMOS Inputs

A user-configurable bit determines the threshold level –TTL or CMOS – of the input buffer.Open Collector/Tristate Outputs

A user-configurable bit which enables or disables the active pull-up of the output device.

Slew Rate Control

A user-configurable bit controls the slew rate – fast or slow – of the output buffer. A slow slew rate, which reduces noise and ground bounce, is recommended for outputs that are not speed-critical. Fast and slow slew rates have the same DC-current sinking capabilities, but the rate at which each allows the output devices to reach full drive differs. Pull-up

A user-configurable bit controls the pull-up transistor in the I/O pin. It ’s primary function is to provide a logical “1” to unused input pins. When on, it is approximately equivalent to a 25K resistor to V CC .Enable Select

User-configurable bits determine the output-enable for the output driver. The output driver can be static – always on or always off – or dynamically controlled by a signal gener-ated in the array. Four options are available from the array:(1) the control is low and always driving; (2) the control is high and never driving; (3) the control is connected to a ver-tical local bus associated with the output cell; or (4) the control is connected to a horizontal local bus associated with the output cell. On power-up, the user I/Os are config-ured as inputs with pull-up resistors.

In addition to the functionality provided by the I/O logic, the entrance and exit cells provide the ability to register both inputs and outputs. Also, these perimeter cells (unlike inte-rior cells) are connected directly to express buses: the edge-facing A and B outputs of the entrance cell are con-nected to express buses, as are the edge-facing A and B inputs of the exit cell. These buses are perpendicular to the edge, and provide a rapid means of bringing I/O signals to and from the array interior and the opposite edge of the chip.

Chip Configuration

The Integrated Development System generates the SRAM bit pattern required to configure a AT6000 Series device. A PC parallel port, microprocessor, EPROM or serial configu-ration memory can be used to download configuration patterns.

Users select from several configuration modes. Many fac-tors, including board area, configuration speed and the number of designs implemented in parallel can influence the user ’s final choice.

Configuration is controlled by dedicated configuration pins and dual-function pins that double as I/O pins when the device is in operation. The number of dual-function pins

required for each mode varies.

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AT6000(LV) Series

The devices can be partially reconfigured while in opera-tion. Portions of the device not being modified remain operational during reconfiguration. Simultaneous configu-ration of more than one device is also possible. Full configuration takes as little as a millisecond, partial configu-ration is even faster.

Refer to the Pin Function Description section following for a brief summary of the pins used in configuration. For more information about configuration, refer to the AT6000 Series Configuration data sheet.

Pin Function Description

This section provides abbreviated descriptions of the vari-ous AT6000 Series pins. For more complete descriptions,refer to the AT6000 Series Configuration data sheet.Pinout tables for the AT6000 series of devices follow.

Power Pins

V CC , V DD , GND, V SS

V CC and GND are the I/O supply pins, V DD and V SS are the internal logic supply pins. V CC and V DD should be tied to the same trace on the printed circuit board. GND and V SS should be tied to the same trace on the printed circuit board.

Input/Output Pins

All I/O pins can be used in the same way (refer to the I/O section of the architecture description). Some I/O pins are dual-function pins used during configuration of the array.When not being used for configuration, dual-function I/Os are fully functional as normal I/O pins. On initial power-up,all I/Os are configured as TTL inputs with a pull-up.

Dedicated Timing and Control Pins

Configuration-in-process pin. After power-up, CON stay-sLow until power-up initialization is complete, at which time CON is then released. CON is an open collector signal.After power-up initialization, forcing CON low begins the configuration process.CS

Configuration enable pin. All configuration pins are ignored M0, M1, M2

Configuration mode pins are used to determine the config-uration mode. All three are TTL input https://www.wendangku.net/doc/2111307799.html,LK

Configuration clock pin. CCLK is a TTL input or a CMOS output depending on the mode of operation. In modes 1, 2,3, and 6 it is an input. In modes 4 and 5 it is an output with a typical frequency of 1 MHz. In all modes, the rising edge of the CCLK signal is used to sample inputs and change outputs.CLOCK

External logic source used to drive the internal global clock line. Registers toggle on the rising edge of CLOCK. The CLOCK signal is neither used nor affected by the configu-ration modes. It is always a TTL input.Array register asynchronous reset. RESET drives the inter-nal global reset. The RESET signal is neither used nor affected by the configuration modes. It is always a TTL input.

Dual-function Pins

figuration control or data signals as determined by the configuration modes. Care must be taken when using these pins to ensure that configuration activity does not interfere with other circuitry connected to these pins in the application.D0 or I/O

Serial configuration modes use D0 as the serial data input pin. Parallel configuration modes use D0 as the least-sig-nificant bit. Input data must meet setup and hold requirements with respect to the rising edge of CCLK. D0 is a TTL input during configuration.D1 to D7 or I/O

Parallel configuration modes use these pins as inputs.Serial configuration modes do not use them. Data must meet setup and hold requirements with respect to the rising edge of CCLK. D1 - D7 are TTL inputs during configuration.A0 to A16 or I/O

During configuration in modes 1, 2 and 5, these pins are CMOS outputs and act as the address pins for a parallel EPROM. A0 - A16 eliminates the need for an external address counter when using an external parallel nonvolatile

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AT6000(LV) Series

memory to configure the FPGA. Addresses change after the rising edge of the CCLK signal.CSOUT or I/O

optional and can be disabled during initial programming when cascading is not used. When cascading devices,as a configurable I/O.During configuration, CHECK is a TTL input that can be used to enable the data check function at the beginning of a configuration cycle. No data is written to the device while CHECK is low. Instead, the configuration file being applied to D0 (or D0 - D7, in parallel mode) is compared with the

current contents of the internal configuration RAM. If a mis-match is detected between the data being loaded and the data already in the RAM, the ERR pin goes low. The CHECK function is optional and can be disabled during ini-tial programming.ERR or I/O

function is activated and a mismatch is detected between the current configuration data stream and the data already ouput is a registered signal. Once a mismatch is found, the signal is set and is only reset after the configuration cycle is initial programming.

Device Pinout Selection (Max. Number of User I/O)

AT6002

AT6003AT6005AT6010

84 PLCC 64 I/O 64 I/O 64 I/O -100 VQFP 80 I/O 80 I/O 80 I/O -132 PQFP 96 I/O 108 I/O 108 I/O 108 I/O 144 TQFP 95 I/O 120 I/O 108 I/O 120 I/O 208 PQFP ---172 I/O 240 PQFP

---204 I/O

Bit-stream Sizes

Mode(s)

Type Beginning Sequence AT6002AT6003AT6005AT60101Parallel Preamble 267741538077163932Parallel Preamble

267741538077163933Serial Null Byte/Preamble 267841548078163944Serial Null Byte/Preamble 267841548078163945Parallel Preamble

267741538077163936

Parallel

Preamble/Preamble

2678

4154

8078

16394

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AT6000(LV) Series

Pinout Assignment

Left Side (Top to Bottom)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP ---I/O51(A)----B111I/O24(A) or A7I/O30(A) or A7I/O27(A) or A7I/O50(A) or A7121181C122-I/O29(B)-I/O49(A)---2D133---I/O48(B)------4---VCC ----PWR (1)45---I/O47(A)----E156---GND ----GND (2)67-I/O28(A)I/O26(A)I/O46(A)--193G178I/O23(A) or A6I/O27(A) or A6I/O25(A) or A6I/O45(A) or A6132204H189---I/O44(B)------10---I/O43(A)----C2911I/O22(B)I/O26(A)I/O24(A)I/O42(A)--215D21012I/O21(A) or A5I/O25(A) or A5I/O23(A) or A5I/O41(A) or A5143226E21113---I/O40(B)------14---I/O39(A)----F21215I/O20(B)I/O24(B)I/O22(A)I/O38(A)-4237G21316I/O19(A) or A4I/O23(A) or A4I/O21(A) or A4I/O37(A) or A4155248H21417---I/O36(B)------18I/O18(B)I/O22(B)I/O20(A)I/O35(A)--259D31519I/O17(A) or A3I/O21(A) or A3I/O19(A) or A3I/O34(A) or A31662610E31620I/O16(B)I/O20(B)I/O18(A)I/O33(A)-72711F31721---I/O32(B)-----1822I/O15(A) or A2I/O19(A) or A2I/O17(A) or A2I/O31(A) or A21782812G31923-I/O18(B)I/O16(A)I/O30(A)--2913H32024GND GND GND GND 1893014GND (2)2125VSS

VSS

19103115GND (2)2226I/O14(A) or A1I/O17(A) or A1I/O15(A) or A1I/O29(A) or A120113216F42327---I/O28(B)-----2428-I/O16(B)-I/O27(A)---17G42529I/O13(A) or A0I/O15(A) or A0I/O14(A) or A0I/O26(A) or A021123318H42630I/O12(B) or D7I/O14(A) or D7I/O13(A) or D7I/O25(B) or D722133419H52731---I/O24(B)-----2832I/O11(A) or D6I/O13(A) or D6I/O12(A) or D6I/O23(A) or D623143520J42933I/O10(A) or D5I/O12(A) or D5I/O11(A) or D5I/O22(A) or D524153621K43034VDD VDD VDD VDD 25163722PWR (1)3135VCC

VCC

PWR (1)

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AT6000(LV) Series

2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

I/O9(B)I/O11(B)I/O10(A)I/O21(A)--3924J33337---I/O20(B)-----3438I/O8(A) or D4I/O10(A) or D4I/O9(A) or D4I/O19(A) or D427184025K33539I/O7(B)I/O9(B)I/O8(A)I/O18(A)-194126L33640---I/O17(A)----M33741---I/O16(B)------42I/O6(A) or D3I/O8(A) or D3I/O7(A) or D3I/O15(A) or D328204227N33843-I/O7(B)I/O6(A)I/O14(A)--4328J23944---I/O13(A)----K24045GND GND GND GND --4429GND (2)4146---VSS ----GND (2)

4247---I/O12(B)------48I/O5(A) or D2I/O6(A) or D2I/O5(A) or D2I/O11(A) or D229214530M24349I/O4(B)I/O5(B)I/O4(A)I/O10(A)-224631N24450---I/O9(A)----P24551---I/O8(B)------52I/O3(A) or D1I/O4(A) or D1I/O3(A) or D1I/O7(A) or D130234732J14653I/O2(B)I/O3(A)I/O2(A)I/O6(A)--4833K14754---I/O5(A)----L14855---I/O4(B)------56-I/O2(B)-I/O3(A)---34M14957I/O1(A) or D0I/O1(A) or D0I/O1(A) or D0I/O2(A) or D031244935N15058---I/O1(A)----P15159CCLK

CCLK

Pinout Assignment (Continued)

Left Side (Top to Bottom)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP 元器件交易网https://www.wendangku.net/doc/2111307799.html,

AT6000(LV) Series

Pinout Assignment

Bottom Side (Left to Right)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP CON CON CON CON 33265137M55361---I/O204(A)----M65462I/O96(A)I/O120(A)I/O108(A)I/O203(A)34275238M75563-I/O119(B)-I/O202(A)---39R25664---I/O201(B)------65---VCC ----PWR (1)5766---I/O200(A)----R35867---GND ----GND (2)5968-I/O118(A)I/O107(A)I/O199(A)--5340R56069I/O95(A) or CSOUT I/O117(A) or CSOUT I/O106(A) or CSOUT I/O198(A) or CSOUT 35285441R66170---I/O197(B)------71---I/O196(A)----R76272I/O94(B)I/O116(A)I/O105(A)I/O195(A)--5542P36373I/O93(A)I/O115(A)I/O104(A)I/O194(A)36295643P46474---I/O193(B)------75---I/O192(A)----P56576I/O92(B)I/O114(B)I/O103(A)I/O191(A)-305744P66677I/O91(A) or CHECK I/O113(A) or CHECK I/O102(A) or CHECK I/O190(A) or CHECK 37315845P76778---I/O189(B)------79I/O90(B)I/O112(B)I/O101(A)I/O188(A)--5946N46880I/O89(A) or ERR I/O111(A) or ERR I/O100(A) or ERR I/O187(A) or ERR 38326047N56981I/O88(B)I/O110(B)I/O99(A)I/O186(A)-336148N67082---I/O185(B)-----7183I/O87(A)I/O109(A)I/O98(A)I/O184(A)39346249N77284-I/O108(B)I/O97(A)I/O183(A)--6350M87385GND GND GND GND 40356451GND (2)7486I/O86(A)I/O107(A)I/O96(A)I/O182(A)41366552M97587---I/O181(B)-----7688-I/O106(B)-I/O180(A)---53M107789I/O85(A)I/O105(A)I/O95(A)I/O179(A)42376654M117890CS CS CS CS 43386755L87991I/O84(B)I/O104(A)I/O94(A)I/O178(A)44396856M128092---I/O177(B)-----8193I/O83(A)

I/O103(A)

I/O93(A)

I/O176(A)

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AT6000(LV) Series

Notes:

1.PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A1

2.2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

---VDD ----PWR (1)8395VCC VCC VCC VCC 46417058PWR (1)8496I/O82(A)I/O102(A)I/O92(A)I/O175(A)47427159N118597I/O81(B)I/O101(B)I/O91(A)I/O174(A)--7260N128698---I/O173(B)-----8799I/O80(A)I/O100(A)I/O90(A)I/O172(A)48437361N1388100I/O79(B)I/O99(B)I/O89(A)I/O171(A)-447462P889101---I/O170(A)----P990102---I/O169(B)------103I/O78(A)I/O98(A)I/O88(A)I/O168(A)49457563P1091104-I/O97(B)I/O87(A)I/O167(A)--7664P1192105---I/O166(A)----P1293106GND GND GND GND --7765GND (2)

94107---I/O165(B)------108I/O77(A)I/O96(A)I/O86(A)I/O164(A)50467866P1395109I/O76(B)I/O95(B)I/O85(A)I/O163(A)-477967P1496110---I/O162(A)----P897111---I/O161(B)------112I/O75(A)I/O94(A)I/O84(A)I/O160(A)51488068R998113I/O74(B)I/O93(A)I/O83(A)I/O159(A)--8169R1099114---I/O158(A)----R11100115---I/O157(B)------116-I/O92(B)-I/O156(A)---70R12101117I/O73(A)I/O91(A)I/O82(A)I/O155(A)52498271R13102118---I/O154(A)----R14103119RESET

RESET

R15

104

120

Pinout Assignment (Continued)

Bottom Side (Left to Right)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP 元器件交易网https://www.wendangku.net/doc/2111307799.html,

AT6000(LV) Series

Pinout Assignment

Right Side (Bottom to Top)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP ---I/O153(A)----P1*******I/O72(A)I/O90(A)I/O81(A)I/O152(A)54518473N15106122-I/O89(B)I/O80(A)I/O151(A)--85(3)74M15107123---I/O150(B)------124---VCC ----PWR (1)108125---I/O149(A)----L15109126---GND ----GND (2)110127-I/O88(A)-I/O148(A)--85(4)75J15111128I/O71(A)I/O87(A)I/O79(A)I/O147(A)55528676H15112129---I/O146(B)------130---I/O145(A)----N14113131I/O70(B)I/O86(A)I/O78(A)I/O144(A)--8777M14114132I/O69(A)I/O85(A)I/O77(A)I/O143(A)56538878L14115133---I/O142(B)------134---I/O141(A)----K14116135I/O68(B)I/O84(B)I/O76(A)I/O140(A)-548979J14117136I/O67(A)I/O83(A)I/O75(A)I/O139(A)57559080H14118137---I/O138B ------138I/O66(B)I/O82(B)I/O74(A)I/O137(A)--9181M13119139I/O65(A)I/O81(A)I/O73(A)I/O136(A)58569282L13120140I/O64(B)I/O80(B)I/O72(A)I/O135(A)-579383K13121141---I/O134(B)-----122142I/O63(A)I/O79(A)I/O71(A I/O133(A)59589484J13123143-I/O78(B)I/O70(A)I/O132(A)--9585H13124144GND GND GND GND 60599686GND (2)125145VSS VSS VSS VSS 61609787GND (2)126146I/O62(A)I/O77(A)I/O69(A)I/O131(A)62619888K12127147---I/O130(B)-----128148-I/O76(B)-I/O129(A)---89J12129149I/O61(A)I/O75(A)I/O68(A)I/O128(A)63629990H12130150I/O60(B)I/O74(A)I/O67(A)I/O127(A)646310091H11131151---I/O126(B)-----132152I/O59(A)I/O73(A)I/O66(A)I/O125(A)656410192G12133153I/O58(A)I/O72(A)I/O65(A)I/O124(A)666510293F12134154VDD VDD VDD VDD 676610394PWR (1)135155VCC

VCC

104

PWR (1)

136

156

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AT6000(LV) Series

2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

3.85 = Pin 85 on A T6005.

4.85 = Pin 85 on A T6003 and A T6010.

I/O57(B)I/O71(B)I/O64(A)I/O123(A)--10596G13137157---I/O122(B)-----138158I/O56(A)I/O70(A)I/O63(A)I/O121(A)696810697F13139159I/O55(B)I/O69(B)I/O62(A)I/O120(A)-6910798E13140160---I/O119(A)----D1*******---I/O118(B)------162I/O54(A)I/O68(A)I/O61(A)I/O117(A)707010899C13142163-I/O67(B)I/O60(A)I/O116(A)--109100G14143164---I/O115(A)----F14144165GND GND GND GND --110101GND (2)145166---VSS ----GND (2)

146167---I/O114(B)------168I/O53(A)I/O66(A)I/O59(A)I/O113(A)7171111102D14147169I/O52(B)I/O65(B)I/O58(A)I/O112(A)-72112103C14148170---I/O111(A)----B14149171---I/O110(B)------172I/O51(A)I/O64(A)I/O57(A)I/O109(A)7273113104G15150173I/O50(B)I/O63(A)I/O56(A)I/O108(A)--114105F15151174---I/O107(A)----E15152175---I/O106(B)------176-I/O62(B)-I/O105(A)---106D15153177I/O49(A)I/O61(A)I/O55(A)I/O104(A)7374115107C15154178‘---I/O103(A)----B15155179M2

116

108

A15

156

180

Pinout Assignment (Continued)

Right Side (Bottom to Top)

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AT6000(LV) Series

Pinout Assignment

Top Side (Right to Left)

AT6002AT6003AT6005AT601084 PLCC 100 VQFP 132 PQFP 144 TQFP 180 CPGA 208 PQFP 240 PQFP M1M1M1M175********D1*******---I/O102(A)----D1*******I/O48(A)I/O60(A)I/O54(A)I/O101(A)7677118110D9159183-I/O59(B)-I/O100(A)---111A14160184---I/O99(B)------185---VCC ----PWR (1)161186---I/O98(A)----A13162187---GND ----GND (2)163188-I/O58(A)I/O53(A)I/O97(A)--119112A11164189I/O47(A)I/O57(A)I/O52(A)I/O96(A)7778120113A10165190---I/O95(B)------191---I/O94(A)----A9166192I/O46(B)I/O56(A)I/O51(A)I/O93(A)--121114B13167193I/O45(A)I/O55(A)I/O50(A)I/O92(A)7879122115B12168194---I/O91(B)------195---I/O90(A)----B11169196I/O44(B)I/O54(B)I/O49(A)I/O89(A)-80123116B10170197I/O43(A)I/O53(A)I/O48(A)I/O88(A)7981124117B9171198---I/O87(B)------199I/O42(B)I/O52(B)I/O47(A)I/O86(A)--125118C12172200I/O41(A)I/O51(A)I/O46(A)I/O85(A)8082126119C11173201I/O40(B)I/O50(B)I/O45(A)I/O84(A)-83127120C10174202---I/O83(B)-----175203I/O39(A)I/O49(A)I/O44(A)I/O82(A)8184128121C9176204-I/O48(B)I/O43(A)I/O81(A)--129122D8177205GND GND GND GND 8285130123GND (2)178206I/O38(A)I/O47(A)I/O42(A)I/O80(A)8386131124D7179207---I/O79(B)-----180208-I/O46(B)-I/O78(A)---125D6181209I/O37(A) or A16I/O45(A) or A16I/O41(A) or A16I/O77(A) or A168487132126D5182210CLOCK CLOCK CLOCK CLOCK 1881127E8183211I/O36(B) or A15I/O44(B) or A15I/O40(A) or A15I/O76(A) or A152892128D4184212---I/O75(B)-----185213I/O35(A) or A14I/O43(A) or A14I/O39(A) or A14I/O74(A) or A143903129C8186214---VDD ----PWR (1)187215VCC

VCC

130

PWR (1)

188

216

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AT6000(LV) Series

2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

I/O34(A) or A13I/O42(A) or A13I/O38(A) or A13I/O73(A) or A135925131C5189217I/O33(B)I/O41(B)I/O37(A)I/O72(A)--6132C4190218---I/O71(B)-----191219I/O32(A) or A12I/O40(A) or A12I/O36(A) or A12I/O70(A) or A126937133C3192220I/O31(B)I/O39(B)I/O35(A)I/O69(A)-948134B8193221---I/O68(A)----B7194222---I/O67(B)------223I/O30(A) or A11I/O38(A) or A11I/O34(A) or A11I/O66(A) or A117959135B6195224-I/O37(B)I/O33(A)I/O65(A)--10136B5196225---I/O64(A)----B4197226GND GND GND GND --11137GND (2)

198227---I/O63(B)------228I/O29(A) or A10I/O36(A) or A10I/O32(A) or A10I/O62(A) or A1089612138B3199229I/O28(B)I/O35(B)I/O31(A)I/O61(A)-9713139B2200230---I/O60(A)----A8201231---I/O59(B)------232I/O27(A) or A9I/O34(A) or A9I/O30(A) or A9I/O58(A) or A999814140A7202233I/O26(B)I/O33(A)I/O29(A)I/O57(A)--15141A6203234---I/O56(A)----A5204235---I/O55(B)------236-I/O32(B)-I/O54(A)---142A4205237I/O25(A) or A8I/O31(A) or A8I/O28(A) or A8I/O53(A) or A8109916143A3206238---I/O52(A)----A2-207239M0

100

144

208

240

Pinout Assignment (Continued)

Top Side (Right to Left)

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AT6000(LV) Series

AC Timing Characteristics – 5V Operation

Notes:

1.TTL buffer delays are measured from a V IH of 1.5V at the pad to the internal V IH at A. The input buffer load is constant.

2.CMOS buffer delays are measured from a V IH of 1/2 V CC at the apd to the internal V IH at A. The input buffer load is constant.

3.Buffer delay is to a pad voltage of 1.5V with one output switching.

4.Max specifications are the average of mas t PDLH and t PDHL .

5.Parameter based on characterization and simulation; not tested in production

6.Exact power calculation is available in an Atmel application note.

Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF .

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.Worst case: V CC = 4.75V to 5.25V. Temperature = 0°C to 70°C.

Cell Function Parameter From To Load Definition (7)

-1-2-4Units Wire (4)t PD (max)(4)A, B, L A, B 10.8 1.2 1.8ns NAND t PD (max)A, B, L B 1 1.6 2.2 3.2ns XOR t PD (max)A, B, L A 1 1.8 2.4 4.0ns AND t PD (max)A, B, L B 1 1.7 2.2 3.2ns MUX t PD (max)A, B A 1 1.7 2.3 4.0ns L A 1 2.1 3.0 4.9ns D-Flip-flop (5)t setup (min)A, B, L CLK - 1.5 2.0 3.0ns D-Flip-flop (5)t hold (min)CLK A, B, L -000ns D-Flip-flop t PD (max)CLK A 1 1.5 2.0 3.0ns Bus Driver t PD (max)A L 2 2.0 2.6 4.0ns Repeater t PD (max)L, E E 3 1.3 1.6 2.3ns L, E L 2 1.7 2.1 3.0ns Column Clock t PD (max)GCLK, A, ES CLK 3 1.8 2.4 3.0ns Column Reset t PD (max)GRES, A, EN RES 3 1.8 2.4 3.0ns Clock Buffer (5)t PD (max)CLOCK PIN GCLK - 1.6 2.0 2.9ns Reset Buffer (5)t PD (max)RESET PIN

GRES - 1.5 1.9 2.8ns TTL Input (1)t PD (max)I/O A 3 1.0 1.2 1.5ns CMOS Input (2)t PD (max)I/O A 3 1.3 1.4 2.3ns Fast Output (3)t PD (max)A I/O PIN 4 3.3 3.5 6.0ns Slow Output (3)t PD (max)A I/O PIN 47.58.012.0ns Output Disable (5)t PXZ (max)L I/O PIN 4 3.1 3.3 5.5ns Fast Enable (3)(5)t PXZ (max)L I/O PIN 4 3.8 4.0 6.5ns Slow Enable (3)(5)t PXZ (max)

I/O PIN

8.28.5

12.5ns

Device Cell Types

Outputs I CC (max)Cell (6)Wire, XWire, Half-adder, Flip-flop

A, B 4.5 μA/MHz Bus (6)

Wire, XWire, Half-adder, Flip-flop, Repeater L 2.5 μA/MHz Column Clock (6)Column Clock Driver

CLK

40 μA/MHz

= Preliminary Information

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AT6000(LV) Series

AC Timing Characteristics – 3.3V Operation

Notes:

1.TTL buffer delays are measured from a V IH of 1.5V at the pad to the internal V IH at A. The input buffer load is constant.

2.CMOS buffer delays are measured from a V IH of 1/2 V CC at the apd to the internal V IH at A. The input buffer load is constant.

3.Buffer delay is to a pad voltage of 1.5V with one output switching.

4.Max specifications are the average of mas t PDLH and t PDHL .

5.Parameter based on characterization and simulation; not tested in production

6.Exact power calculation is available in an Atmel application note.

Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Load of 28 Clock Columns; 5 = Load of 28 Reset Columns; 6 = Tester Load of 50 pF .

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.Worst case: V CC = 3.0V to 3.6V. Temperature = 0°C to 70°C.

Cell Function Parameter From To Load Definition (7)

-4Units Wire (4)t PD (max)(4)A, B, L A, B 1 1.8ns NAND t PD (max)A, B, L B 1 3.2ns XOR t PD (max)A, B, L A 1 4.0ns AND t PD (max)A, B, L B 1 3.2ns MUX t PD (max)A, B A 1 4.0ns L A 1 4.9ns D-Flip-flop (5)t setup (min)A, B, L CLK - 3.0ns D-Flip-flop (5)t hold (min)CLK A, B, L -0ns D-Flip-flop t PD (max)CLK A 1 3.0ns Bus Driver t PD (max)A L 2 4.0ns Repeater t PD (max)L, E E 3 2.3ns L, E L 2 3.0ns Column Clock t PD (max)GCLK, A, ES CLK 3 3.0ns Column Reset t PD (max)GRES, A, EN RES 3 3.0ns Clock Buffer (5)t PD (max)CLOCK PIN GCLK 4 2.9ns Reset Buffer (5)t PD (max)RESET PIN

GRES 5 2.8ns TTL Input (1)t PD (max)I/O A 3 1.5ns CMOS Input (2)t PD (max)I/O A 3 2.3ns Fast Output (3)t PD (max)A I/O PIN 6 6.0ns Slow Output (3)t PD (max)A I/O PIN 612.0ns Output Disable (5)t PXZ (max)L I/O PIN 6 5.5ns Fast Enable (3)(5)t PXZ (max)L I/O PIN 6 6.5ns Slow Enable (3)(5)t PXZ (max)

I/O PIN

12.5

Device Cell Types

Outputs I CC (max)Cell (6)Wire, XWire, Half-adder, Flip-flop

A, B 2.3 μA/MHz Bus (6)

Wire, XWire, Half-adder, Flip-flop, Repeater L 1.3 μA/MHz Column Clock (6)Column Clock Driver

CLK

20 μA/MHz

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