Simulation and Synthesis Techniques for Asynchronous FIFO Design

Expert Verilog, SystemVerilog & Synthesis Training

Simulation and Synthesis Techniques for Asynchronous

FIFO Design

Clifford E. Cummings, Sunburst Design, Inc.

cliffc@https://www.wendangku.net/doc/2d13512796.html,

ABSTRACT

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design.

This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

Post-SNUG Editorial Comment

A second FIFO paper by the same author was voted “Best Paper - 1st Place” by SNUG attendees, is listed as reference [3] and is also available for download.

1.0 Introduction

An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other.

Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain.

There are many ways to do asynchronous FIFO design, including many wrong ways. Most incorrectly implemented FIFO designs still function properly 90% of the time. Most almost-correct FIFO designs function properly 99%+ of the time. Unfortunately, FIFOs that work properly 99%+ of the time have design flaws that are usually the most difficult to detect and debug (if you are lucky enough to notice the bug before shipping the product), or the most costly to diagnose and recall (if the bug is not discovered until the product is in the hands of a dissatisfied customer).

This paper discusses one FIFO design style and important details that must be considered when doing asynchronous FIFO design.

The rest of the paper simply refers to an “asynchronous FIFO” as just “FIFO.”

2.0Passing multiple asynchronous signals

Attempting to synchronize multiple changing signals from one clock domain into a new clock domain and insuring that all changing signals are synchronized to the same clock cycle in the new clock domain has been shown to be problematic[1]. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another. Data words are placed into a FIFO buffer memory array by control signals in one clock domain, and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain. Conceptually, the task of designing a FIFO with these assumptions seems to be easy.

The difficulty associated with doing FIFO design is related to generating the FIFO pointers and finding a reliable way to determine full and empty status on the FIFO.

2.1Synchronous FIFO pointers

For synchronous FIFO design (a FIFO where writes to, and reads from the FIFO buffer are conducted in the same clock domain), one implementation counts the number of writes to, and reads from the FIFO buffer to increment (on FIFO write but no read), decrement (on FIFO read but no write) or hold (no writes and reads, or simultaneous write and read operation) the current fill value of the FIFO buffer. The FIFO is full when the FIFO counter reaches a predetermined full value and the FIFO is empty when the FIFO counter is zero.

Unfortunately, for asynchronous FIFO design, the increment-decrement FIFO fill counter cannot be used, because two different and asynchronous clocks would be required to control the counter. To determine full and empty status for an asynchronous FIFO design, the write and read pointers will have to be compared.

2.2Asynchronous FIFO pointers

In order to understand FIFO design, one needs to understand how the FIFO pointers work. The write pointer always points to the next word to be written; therefore, on reset, both pointers are set to zero, which also happens to be the next FIFO word location to be written. On a FIFO-write operation, the memory location that is pointed to by the write pointer is written, and then the write pointer is incremented to point to the next location to be written. Similarly, the read pointer always points to the current FIFO word to be read. Again on reset, both pointers are reset to zero, the FIFO is empty and the read pointer is pointing to invalid data (because the FIFO is empty and the empty flag is asserted). As soon as the first data word is written to the FIFO, the write pointer increments, the empty flag is cleared, and the read pointer that is still addressing the contents of the first FIFO memory word, immediately drives that first valid word onto the FIFO data output port, to be read by the receiver logic. The fact that the read pointer is always pointing to the next FIFO word to be read means that the receiver logic does not have to use two clock periods to read the data word. If the receiver first had to increment the read pointer before reading a FIFO data

word, the receiver would clock once to output the data word from the FIFO, and clock a second time to capture the data word into the receiver. That would be needlessly inefficient.

The FIFO is empty when the read and write pointers are both equal. This condition happens when both pointers are reset to zero during a reset operation, or when the read pointer catches up to the write pointer, having read the last word from the FIFO.

A FIFO is full when the pointers are again equal, that is, when the write pointer has wrapped around and caught up to the read pointer. This is a problem. The FIFO is either empty or full when the pointers are equal, but which? One design technique used to distinguish between full and empty is to add an extra bit to each pointer. When the write pointer increments past the final FIFO address, the write pointer will increment the unused MS

B while setting the rest of the bits back to zero as shown in Figure 1 (the FIFO has wrapped and toggled the pointer MSB). The same is done with the read pointer. If the MSBs of the two pointers are different, it means that the write pointer has wrapped one more time that the read pointer. If the MSBs of the two pointers are the same, it means that both pointers have wrapped the same number of times.

Figure 1 - FIFO full and empty conditions

Using n-bit pointers where (n-1) is the number of address bits required to access the entire FIFO memory buffer, the FIFO is empty when both pointers, including the MSBs are equal. And the FIFO is full when both pointers, except the MSBs are equal.

The FIFO design in this paper uses n-bit pointers for a FIFO with 2(n-1) write-able locations to help handle full and empty conditions. More design details related to the full and empty logic are included in section 5.0.

2.3Binary FIFO pointer considerations

Trying to synchronize a binary count value from one clock domain to another is problematic because every bit of an n-bit counter can change simultaneously (example 7->8 in binary numbers is 0111->1000, all bits changed). One approach to the problem is sample and hold periodic binary count values in a holding register and pass a synchronized ready signal to the new clock domain. When the ready signal is recognized, the receiving clock domain sends back a synchronized acknowledge signal to the sending clock domain. A sampled pointer must not change until an acknowledge signal is received from the receiving clock domain. A count-value with multiple changing bits can be safely transferred to a new clock domain using this technique. Upon receipt of an acknowledge signal, the sending clock domain has permission to clear the ready signal and re-sample the binary count value. Using this technique, the binary counter values are sampled periodically and not all of the binary counter values can be passed to a new clock domain The question is, do we need to be concerned about the case where a binary counter might continue to increment and overflow or underflow the FIFO between sampled counter values? The answer is no[8].

FIFO full occurs when the write pointer catches up to the synchronized and sampled read pointer. The synchronized and sampled read pointer might not reflect the current value of the actual read pointer but the write pointer will not try to count beyond the synchronized read pointer value. Overflow will not occur[8].

FIFO empty occurs when the read pointer catches up to the synchronized and sampled write pointer. The synchronized and sampled write pointer might not reflect the current value of the actual write pointer but the read pointer will not try to count beyond the synchronized write pointer value. Underflow will not occur[8].More observations about this technique of sampling binary pointers with a synchronized ready-acknowledge pair of handshaking signals are detailed in section 7.0, after the discussion of synchronized Gray[6] code pointers.

A common approach to FIFO counter-pointers, is to use Gray code counters. Gray codes only allow one bit to change for each clock transition, eliminating the problem associated with trying to synchronize multiple changing signals on the same clock edge.

2.4FIFO testing troubles

Testing a FIFO design for subtle design problems is nearly impossible to do. The problem is rooted in the fact that FIFO pointers in an RTL simulation behave ideally, even though, if incorrectly implemented, they can cause catastrophic failures if used in a real design.

In an RTL simulation, if binary-count FIFO pointers are included in the design all of the FIFO pointer bits will change simultaneously; there is no chance to observe synchronization and comparison problems. In a gate-level simulation with no backannotated delays, there is only a slight chance of observing a problem if the gate transitions are different for rising and falling edge signals, and even then, one would have to get lucky and have the correct sequence of bits changing just prior to and just after a rising clock edge. For higher speed designs, the delay differences between rising and falling edge signals diminishes and the probability of detecting problems also diminishes. Finding actual FIFO design problems is greatest for gate-level designs with backannotated delays, but even doing this type of simulation, finding problems will be difficult to do and again the odds of observing the design problems decreases as signal propagation delays diminish.

Clearly the answer is to recognize that there are potential FIFO design problems and to do the design correctly from the start.

The behavioral model that I sometimes use for testing a FIFO design is a FIFO model that is simple to code, is accurate for behavioral testing purposes and would be difficult to debug if it were used as an RTL synthesis model. This FIFO model is only recommended for use in a FIFO testbench. The model accurately determines when FIFO full and empty status bits should be set and can be used to determine the data values that should have been stored into a working FIFO. THIS FIFO MODEL IS NOT SAFE FOR SYNTHESIS!

module beh_fifo (rdata, wfull, rempty, wdata,

winc, wclk, wrst_n, rinc, rclk, rrst_n);

parameter DSIZE = 8;

parameter ASIZE = 4;

output [DSIZE-1:0] rdata;

output wfull;

output rempty;

input [DSIZE-1:0] wdata;

input winc, wclk, wrst_n;

input rinc, rclk, rrst_n;

reg [ASIZE:0] wptr, wrptr1, wrptr2, wrptr3;

reg [ASIZE:0] rptr, rwptr1, rwptr2, rwptr3;

parameter MEMDEPTH = 1<

reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1];

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) wptr <= 0;

else if (winc && !wfull) begin

ex_mem[wptr[ASIZE-1:0]] <= wdata;

wptr <= wptr+1;

end

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) {wrptr3,wrptr2,wrptr1} <= 0;

else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr};

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) rptr <= 0;

else if (rinc && !rempty) rptr <= rptr+1;

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) {rwptr3,rwptr2,rwptr1} <= 0;

else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr};

assign rdata = ex_mem[rptr[ASIZE-1:0]];

assign rempty = (rptr == rwptr3);

assign wfull = ((wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) &&

(wptr[ASIZE] != wrptr3[ASIZE] ));

endmodule

Example 1 - Behavioral FIFO model for testbench use only - SHOULD NOT BE USED FOR SYNTHESIS!

In the behavioral model of Example 1, it is okay to use binary-count pointers, a Verilog array to represent the FIFO memory buffer, multi-asynchronous clocks in the same module and non-registered outputs. THIS MODEL IS NOT INTENDED FOR SYNTHESIS! (Hopefully enough capital letters have been used in this section to discourage anyone from trying to synthesize this model!)

Two of the always blocks in the module (the always blocks with concatenations) are included to behaviorally represent the synchronization that will be required in the actual RTL FIFO design. They are not important to the testing of the data transfer through the FIFO, but they are important to the testing of the correctly timed full and empty flags in the FIFO model. The exact number of synchronization stages required in the behavioral model is FIFO-design dependent. This model can be used to help test the FIFO design described in this paper.

3.0Gray code counter - Style #1

Gray codes are named for the person who originally patented the code back in 1953, Frank Gray[6]. There are multiple ways to design a Gray code counter. This section details a simple and straight forward method to do the design. The technique described in this paper uses just one set of flip-flops for the Gray code counter. A second method that uses two sets of flip-flops to achieve higher speeds is detailed in shown in section 4.0.

3.1Gray code patterns

For reasons that will be described later, it is desirable to create both an n-bit Gray code counter and an (n-1)-bit Gray code counter. It would certainly be easy to create the two counters separately, but it is also easy and efficient to create a common n-bit Gray code counter and then modify the 2nd MSB to form an (n-1)-bit Gray code counter with shared LSBs. In this paper, this will be called a “dual n-bit Gray code counter.”

Figure 2 - n-bit Gray code converted to an (n-1)-bit Gray code

To better understand the problem of converting an n-bit Gray code to an (n-1)-bit Gray code, consider the example of creating a dual 4-bit and 3-bit Gray code counter as shown in Figure 2.

The most common Gray code, as shown in Figure 2, is a reflected code where the bits in any column except the MSB are symmetrical about the sequence mid-point[6]. This means that the second half of the 4-bit Gray code is a mirror image of the first half with the MSB inverted.

To convert a 4-bit to a 3-bit Gray code, we do not want the LSBs of the second half of the 4-bit sequence to be a mirror image of the LSBs of the first half, instead we want the LSBs of the second half to repeat the 4-bit LSB-sequence of the first half.

Upon closer examination, it is obvious that inverting the second MSB of the second half of the 4-bit Gray code will produce the desired 3-bit Gray code sequence in the three LSBs of the 4-bit sequence. The only other problem is that the 3-bit Gray code with extra MSB is no longer a true Gray code because when the sequence changes from 7 (Gray 0100) to 8 (~Gray 1000) and again from 15 (~Gray 1100) to 0 (Gray 0000), two bits are changing instead of just one bit. A true Gray code only changes one bit between counts.

3.2Gray code counter basics

The first fact to remember about a Gray code is that the code distance between any two adjacent words is just 1 (only one bit can change from one Gray count to the next). The second fact to remember about a Gray code counter is that most useful Gray code counters must have power-of-2 counts in the sequence. It is possible to make a Gray code counter that counts an even number of sequences but conversions to and from these sequences are generally not as simple to do as the standard Gray code. Also note that there are no odd-count-length Gray code sequences so one cannot make a 23-deep Gray code. This means that the technique described in this paper is used to make a FIFO that is 2n deep.

Figure 3 is a block diagram for a style #1 dual n-bit Gray code counter. The style #1 Gray code counter assumes that the outputs of the register bits are the Gray code value itself (ptr, either wptr or rptr). The Gray code outputs are then passed to a Gray-to-binary converter (bin), which is passed to a conditional binary-value incrementer to generate the next-binary-count-value (bnext), which is passed to a binary-to-Gray converter that generates the next-Gray-count-value (gnext), which is passed to the register inputs. The top half of the Figure 3 block diagram shows the described logic flow while the bottom half shows logic related to the second Gray code counter as described in the next section.

Figure 3 - Dual n-bit Gray code counter block diagram - style #1

3.3Dual n-bit Gray code counter

A dual n-bit Gray code counter is a Gray code counter that generates both an n-bit Gray code sequence (described in section 3.2) and an (n-1)-bit Gray code sequence.

The (n-1)-bit Gray code is simply generated by doing an exclusive-or operation on the two MSBs of the n-bit Gray code to generate the MSB for the (n-1)-bit Gray code. This is combined with the (n-2) LSBs of the n-bit Gray code counter to form the (n-1)-bit Gray code counter[5].

3.4Additional Gray code counter considerations

The binary-value incrementer is conditioned with either an “if not full” or “if not empty” test as shown in Figure 3, to insure that the appropriate FIFO pointer will not increment during FIFO-full or FIFO-empty conditions that could lead to overflow or underflow of the FIFO buffer.

If the logic block that sends data to the FIFO reliably stops sending data when a FIFO full condition is asserted, the FIFO design might be streamlined by removing the full-testing logic from the FIFO write pointer.

The FIFO pointer itself does not protect the FIFO buffer from being overwritten, but additional conditioning logic could be added to the FIFO memory buffer to insure that a write_enable signal could not be activated during a FIFO full condition.

An additional “sticky” status bit, either ovf (overflow) or unf (underflow), could be added to the pointer design to indicate that an additional FIFO write operation occurred during full or an additional FIFO read operation occurred during empty to indicate error conditions that could only be cleared during reset.

A safe, general purpose FIFO design will include the above safeguards at the expense of a slightly larger and perhaps slower implementation. This is a good idea since a future co-worker might try to copy and reuse the code in another design without understanding all of the important details that were considered for the current design.

4.0Gray code counter - Style #2

Starting with version 1.2 of this paper, the FIFO implementation uses the Gray code counter style #2, which actually employs two sets of registers to eliminate the need to translate Gray pointer values to binary values. The second set of registers (the binary registers) can also be used to address the FIFO memory directly without the need to translate memory addresses into Gray codes. The n-bit Gray-code pointer is still required to synchronize the pointers into the opposite clock domains, but the n-1-bit binary pointers can be used to address memory directly. The binary pointers also make it easier to run calculations to generate "almost-full" and "almost-empty" bits if desired (not shown in this paper).

Figure 4 - Dual n-bit Gray code counter block diagram - style #2

FIFO style #1

The block diagram for FIFO style #1 is shown in Figure 5.

Figure 5 - FIFO1 partitioning with synchronized pointer comparison

To facilitate static timing analysis of the style #1 FIFO design, the design has been partitioned into the following six Verilog modules with the following functionality and clock domains:

?fifo1.v - (see Example 2 in section 6.1) - this is the top-level wrapper-module that includes all clock domains. The top module is only used as a wrapper to instantiate all of the other FIFO modules used in the design. If this FIFO is used as part of a larger ASIC or FPGA design, this top-level wrapper would probably be discarded to permit grouping of the other FIFO modules into their respective clock domains for improved synthesis and static timing analysis.

?fifomem.v - (see Example 3 in section 6.2) - this is the FIFO memory buffer that is accessed by both the write and read clock domains. This buffer is most likely an instantiated, synchronous dual-port RAM. Other memory styles can be adapted to function as the FIFO buffer.

?sync_r2w.v - (see Example 4 in section 6.3) - this is a synchronizer module that is used to synchronize the read pointer into the write-clock domain. The synchronized read pointer will be used by the wptr_full module to generate the FIFO full condition. This module only contains flip-flops that are synchronized to the write clock. No other logic is included in this module.

?sync_w2r.v - (see Example 5 in section 6.4) - this is a synchronizer module that is used to synchronize the write pointer into the read-clock domain. The synchronized write pointer will be used by the rptr_empty module to generate the FIFO empty condition. This module only contains flip-flops that are synchronized to the read clock. No other logic is included in this module.

?rptr_empty.v - (see Example 6 in section 6.5) - this module is completely synchronous to the read-clock domain and contains the FIFO read pointer and empty-flag logic.

?wptr_full.v - (see Example 7 in section 6.6) - this module is completely synchronous to the write-clock domain and contains the FIFO write pointer and full-flag logic.

In order to perform FIFO full and FIFO empty tests using this FIFO style, the read and write pointers must be passed to the opposite clock domain for pointer comparison.

As with other FIFO designs, since the two pointers are generated from two different clock domains, the pointers need to be “safely” passed to the opposite clock domain. The technique shown in this paper is to synchronize Gray code pointers to insure that only one pointer bit can change at a time.

5.0Handling full & empty conditions

Exactly how FIFO full and FIFO empty are implemented is design-dependent.

The FIFO design in this paper assumes that the empty flag will be generated in the read-clock domain to insure that the empty flag is detected immediately when the FIFO buffer is empty, that is, the instant that the read pointer catches up to the write pointer (including the pointer MSBs).

The FIFO design in this paper assumes that the full flag will be generated in the write-clock domain to insure that the full flag is detected immediately when the FIFO buffer is full, that is, the instant that the write pointer catches up to the read pointer (except for different pointer MSBs).

5.1Generating empty

As shown in Figure 1, the FIFO is empty when the read pointer and the synchronized write pointer are equal.

The empty comparison is simple to do. Pointers that are one bit larger than needed to address the FIFO memory buffer are used. If the extra bits of both pointers (the MSBs of the pointers) are equal, the pointers have wrapped the same number of times and if the rest of the read pointer equals the synchronized write pointer, the FIFO is empty. The Gray code write pointer must be synchronized into the read-clock domain through a pair of synchronizer registers found in the sync_w2r module. Since only one bit changes at a time using a Gray code pointer, there is no problem synchronizing multi-bit transitions between clock domains.

In order to efficiently register the rempty output, the synchronized write pointer is actually compared against the rgraynext (the next Gray code that will be registered into the rptr). The empty value testing and the accompanying sequential always block has been extracted from the rptr_empty.v code of Example 6 and is shown below:

assign rempty_val = (rgraynext == rq2_wptr);

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) rempty <= 1'b1;

else rempty <= rempty_val;

5.2Generating full

Since the full flag is generated in the write-clock domain by running a comparison between the write and read pointers, one safe technique for doing FIFO design requires that the read pointer be synchronized into the write clock domain before doing pointer comparison.

The full comparison is not as simple to do as the empty comparison. Pointers that are one bit larger than needed to address the FIFO memory buffer are still used for the comparison, but simply using Gray code counters with an extra bit to do the comparison is not valid to determine the full condition. The problem is that a Gray code is a symmetric code except for the MSBs.

Figure 6 - Problems associated with extracting a 3-bit Gray code from a 4-bit Gray code

Consider the example shown in Figure 6 of an 8-deep FIFO. In this example, a 3-bit Gray code pointer is used to address memory and an extra bit (the MSB of a 4-bit Gray code) is added to test for full and empty conditions. If the FIFO is allowed to fill the first seven locations (words 0-6) and then if the FIFO is emptied by reading back the same seven words, both pointers will be equal and will point to address Gray-7 (the FIFO is empty). On the next write operation, the write pointer will increment the 4-bit Gray code pointer (remember, only the 3 LSBs are being used to address memory), making the MSBs different on the 4-bit pointers but the rest of the write pointer bits will match the read pointer bits, so the FIFO full flag would be asserted. This is wrong! Not only is the FIFO not full, but the 3 LSBs did not change, which means that the addressed memory location will over-write the last FIFO memory location that was written. This too is wrong!

This is one reason why the dual n-bit Gray code counter of Figure 4 and Section 4.0 is used.

The correct method to perform the full comparison is accomplished by synchronizing the rptr into the wclk domain and then there are three conditions that are all necessary for the FIFO to be full:

(1) The wptr and the synchronized rptr MSB's are not equal (because the wptr must have wrapped

one more time than the rptr).

(2) The wptr and the synchronized rptr 2nd MSB's are not equal (because an inverted 2nd MSB from

one pointer must be tested against the un-inverted 2nd MSB from the other pointer, which is required if the MSB's are also inverses of each other - see Figure 6 above).

(3) All other wptr and synchronized rptr bits must be equal.

In order to efficiently register the wfull output, the synchronized read pointer is actually compared against the wgnext (the next Gray code that will be registered in the wptr). This is shown below in the sequential always

block that has been extracted from the wptr_full.v code of Example 7:

assign wfull_val = ((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&

(wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&

(wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) wfull <= 1'b0;

else wfull <= wfull_val;

In the above code, the three necessary conditions to check for FIFO-full are tested and the result is assigned to the wfull_val signal, which is then registered in the subsequent sequential always block.

The continuous assignment to wfull_val can be further simplified using concatenations as shown below: assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1],

wq2_rptr[ADDRSIZE-2:0]});

5.3Different clock speeds

Since asynchronous FIFOs are clocked from two different clock domains, obviously the clocks are running at different speeds. When synchronizing a faster clock into a slower clock domain, there will be some count values that are skipped due to the fact that the faster clock will semi-periodically increment twice between slower clock edges. This raises discussion of the two following questions:

First question. Noting that a synchronized Gray code that increments twice but is only sampled once will show multi-bit changes in the synchronized value, will this cause multi-bit synchronization problems?

The answer is no. Synchronizing multi-bit changes is only a problem when multiple bits are changing near the rising edge of the synchronizing clock. The fact that a Gray code counter could increment twice (or more) between slower synchronization clock edges means that the first Gray code change will occur well before the rising edge of the slower clock and only the second Gray code transition could change near the rising clock edge. There is no multi-bit synchronization problem with Gray code counters.

Second question. Again noting that a faster Gray code counter could increment more than once between the rising edge of a slower clock signal, is it possible that the Gray code counter from the faster clock domain could increment to a full-state and to a full+1-state before full is detected, causing the FIFO to overflow without recognizing that the FIFO was ever full? (This question similarly applies to FIFO empty).

Again, the answer is no using the implementation described in this paper. Consider first the generation of FIFO full. The FIFO goes full when the write pointer catches up to the synchronized read pointer and the FIFO-full state is detected in the write clock domain. If the wclk-domain is faster than the rclk-domain, the write pointer will eventually catch up to the synchronized read pointer, the FIFO will be full, the wfull bit will be set and the FIFO will quit writing until the synchronized read pointer advances again. The write pointer cannot advance past the synchronized read pointer in the wclk-domain.

A similar examination of the empty flag shows that the FIFO goes empty when the read pointer catches up to the synchronized write pointer and the FIFO-empty state is detected in the read clock domain. If the rclk-domain is faster than the wclk-domain, the read pointer will eventually catch up to the synchronized write pointer, the FIFO will be empty, the rempty bit will be set and the FIFO will quit reading until the synchronized write pointer advances again. The read pointer cannot advance past the synchronized write pointer in the rclk-domain.

Using this implementation, assertion of “full” or “empty” happens exactly when the FIFO goes full or empty. Removal of “full” and “empty” status is pessimistic.

5.4Pessimistic full & empty

The FIFO described in this paper has implemented full-removal and empty-removal using a “pessimistic” method. That is, “full” and “empty” are both asserted exactly on time but removed late.

Since the write clock is used to generate the FIFO-full status and since FIFO-full occurs when the write pointer catches up to the synchronized read pointer, full-detection is “accurate” and immediate. Removal of “full” status is pessimistic because “full” comparison is being done with a synchronized read pointer. When the read pointer does increment, the FIFO is no longer full, but the full-generation logic will not detect the change until two rising wclk edges synchronize the updated rptr into the wclk domain. This is generally not a problem, since it means that the data-sending hardware is being “held-off” or informed that the FIFO is still full for a couple of extra wclk edges. The important detail is to insure that the FIFO does not overflow. Signaling the data-sender to not send more data for a couple of extra wclk edges merely gives time for the FIFO to make room to receive more data.

Similarly, since the read clock is used to generate the FIFO-empty status and since FIFO-empty occurs when the read pointer catches up to the synchronized write pointer, empty-detection is “accurate” and immediate. Removal of “empty” status is pessimistic because “empty” comparison is being done with a synchronized write pointer. When the write pointer does increment, the FIFO is no longer empty, but the empty-generation logic will not detect the change until two rising rclk edges synchronize the updated wptr into the rclk domain. This is generally not a problem, since it means that the data-receiving logic is being “held-off” or informed that the FIFO is still empty for a couple of extra rclk edges. The important detail is to insure that the FIFO does not underflow. Signaling the data-receiver to stop removing data from the FIFO for a couple of extra rclk edges merely gives time for the FIFO to be filled with more data.

5.4.1“Accurate” setting of full & empty

Note that setting either the full flag or empty flag might not be quite accurate if both pointers are incrementing simultaneously. For example, if the write pointer catches up to the synchronized read pointer, the full flag will be set, but if the read pointer had incremented at the same time as the write pointer, the full flag will have been set early since the FIFO is not really full due to a read operation occurring simultaneous to the “write-to-full” operation, but the read pointer had not yet been synchronized into the write-clock domain. The setting of the full flag was slightly too early and slightly pessimistic. This is not a design problem.

5.5Multi-bit asynchronous reset

Much attention has been paid to insuring that the FIFO pointers only change one bit at a time. The question is, will there be a problem associated with an asynchronous reset, which generally causes multiple pointer bits to changes simultaneously?

The answer is no. A reset indicates that the FIFO has also been reset and there is no valid data in the FIFO. On assertion of the reset, all of the synchronizing registers, wclk-domain logic (including the registered full flag), and rclk-domain logic are simultaneously and asynchronously reset. The registered empty flag is also set at the same time. The more important question concerns orderly removal of the reset signals.

Note that the design included in this paper uses different reset signals for the wclk and rclk domains. The resets used in this design are intended to be asynchronously set and synchronously removed using the techniques describe in Mills and Cummings[2].

Asynchronous reset of the FIFO pointers is not a problem.

5.6Almost full and almost empty

Many designs require notification of a pending full or empty status with the generation of “almost full” and “almost empty” status bits. There are many ways to implement these two status bits and each implementation is dependent upon the specified design requirements.

Some FIFO designs require programmable FIFO-full and FIFO-empty difference values, such that when the difference between the two pointers is smaller than the programmed difference, the corresponding almost full or almost empty bit is asserted. Other FIFOs may be implemented with a fixed difference to generate almost full or empty. Other FIFOs may be satisfied with almost full and empty being loosely generated when the MSBs of the FIFO pointers are close. And yet other designs might only require knowing when the FIFO is more, or less than half full.

Remembering that the FIFO is full when the wptr catches up to the synchronized rptr, the almost full condition could be described as the condition when (wptr+4) catches up to the synchronized rptr. The (wptr+4) value could be generated in the Gray code pointer logic shown in

Figure 3 by placing a second adder after the Gray-to-binary combinational logic to add four to the binary value and register the result. This registered value would then be used to do subtraction against the synchronized rptr after it has been converted to a binary value in the wclk domain, and if the difference is less than four, an almost_full bit could be set. A less-than operation insures that the almost_full bit is set for the full range when the wptr is within 0-4 counts of catching up to the synchronized rptr. Similar logic could be used in the rclk-domain to generate the almost_empty flag.

Almost full and almost empty have not been included in the Verilog RTL code shown in this paper.

6.0RTL code for FIFO Style #1

The Verilog RTL code for the FIFO style #1 model is listed in this section.

6.1fifo1.v - FIFO top-level module

The top -level FIFO module is a parameterized FIFO design with all sub-blocks instantiated using the recommended practice of doing named port connections. Another common coding practice is to give the top-level module instantiations the same name as the module name. This is done to facilitate debug, since referencing module names in a hierarchical path will be straight forward if the instance names match the module names.

module fifo1 #(parameter DSIZE = 8,

parameter ASIZE = 4)

(output [DSIZE-1:0] rdata,

output wfull,

output rempty,

input [DSIZE-1:0] wdata,

input winc, wclk, wrst_n,

input rinc, rclk, rrst_n);

wire [ASIZE-1:0] waddr, raddr;

wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;

sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),

.wclk(wclk), .wrst_n(wrst_n));

sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),

.rclk(rclk), .rrst_n(rrst_n));

fifomem #(DSIZE, ASIZE) fifomem

(.rdata(rdata), .wdata(wdata),

.waddr(waddr), .raddr(raddr),

.wclken(winc), .wfull(wfull),

.wclk(wclk));

rptr_empty #(ASIZE) rptr_empty

(.rempty(rempty),

.raddr(raddr),

.rptr(rptr),.rq2_wptr(rq2_wptr),

.rinc(rinc), .rclk(rclk),

.rrst_n(rrst_n));

wptr_full #(ASIZE) wptr_full

(.wfull(wfull), .waddr(waddr),

.wptr(wptr), .wq2_rptr(wq2_rptr),

.winc(winc), .wclk(wclk),

.wrst_n(wrst_n));

endmodule

Example 2 - Top-level Verilog code for the FIFO style #1 design

6.2fifomem.v - FIFO memory buffer

The FIFO memory buffer is typically an instantiated ASIC or FPGA dual-port, synchronous memory device. The memory buffer could also be synthesized to ASIC or FPGA registers using the RTL code in this module.

About an instantiated vendor RAM versus a Verilog-declared RAM, the Synopsys DesignWare team did internal analysis and found that for sizes up to 256 bits, there is no lost area or performance using the Verilog-declared RAM compared to an instantiated vendor RAM[4].

If a vendor RAM is instantiated, it is highly recommended that the instantiation be done using named port connections.

module fifomem #(parameter DATASIZE = 8, // Memory data word width

parameter ADDRSIZE = 4) // Number of mem address bits (output [DATASIZE-1:0] rdata,

input [DATASIZE-1:0] wdata,

input [ADDRSIZE-1:0] waddr, raddr,

input wclken, wfull, wclk);

`ifdef VENDORRAM

// instantiation of a vendor's dual-port RAM

vendor_ram mem (.dout(rdata), .din(wdata),

.waddr(waddr), .raddr(raddr),

.wclken(wclken),

.wclken_n(wfull), .clk(wclk));

`else

// RTL Verilog memory model

localparam DEPTH = 1<

reg [DATASIZE-1:0] mem [0:DEPTH-1];

assign rdata = mem[raddr];

always @(posedge wclk)

if (wclken && !wfull) mem[waddr] <= wdata;

`endif

endmodule

Example 3 - Verilog RTL code for the FIFO buffer memory array

6.3sync_r2w.v - Read-domain to write-domain synchronizer

This is a simple synchronizer module, used to pass an n-bit pointer from the read clock domain to the write clock domain, through a pair of registers that are clocked by the FIFO write clock. Notice the simplicity of the always block that concatenates the two registers together for reset and shifting. The synchronizer always block is only three lines of code.

All module outputs are registered for simplified synthesis using time budgeting. All outputs of this module are entirely synchronous to the wclk and all asynchronous inputs to this module are from the rclk domain with all signals named using an “r” prefix, making it easy to set a false path on all “r*” signals for simplified static timing analysis.

module sync_r2w #(parameter ADDRSIZE = 4)

(output reg [ADDRSIZE:0] wq2_rptr,

input [ADDRSIZE:0] rptr,

input wclk, wrst_n);

reg [ADDRSIZE:0] wq1_rptr;

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;

else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};

endmodule

Example 4 - Verilog RTL code for the read-clock domain to write-clock domain synchronizer module

6.4sync_w2r.v - Write-domain to read-domain synchronizer

This is a simple synchronizer module, used to pass an n-bit pointer from the write clock domain to the read clock domain, through a pair of registers that are clocked by the FIFO read clock. Notice the simplicity of the always block that concatenates the two registers together for reset and shifting. The synchronizer always block is only three lines of code.

All module outputs are registered for simplified synthesis using time budgeting. All outputs of this module are entirely synchronous to the rclk and all asynchronous inputs to this module are from the wclk domain with all signals named using an “w” prefix, making it easy to set a false path on all “w*” signals for simplified static timing analysis.

module sync_w2r #(parameter ADDRSIZE = 4)

(output reg [ADDRSIZE:0] rq2_wptr,

input [ADDRSIZE:0] wptr,

input rclk, rrst_n);

reg [ADDRSIZE:0] rq1_wptr;

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;

else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};

endmodule

Example 5 - Verilog RTL code for the write-clock domain to read-clock domain synchronizer module

6.5rptr_empty.v - Read pointer & empty generation logic

This module encloses all of the FIFO logic that is generated within the read clock domain (except synchronizers). The read pointer is a dual n-bit Gray code counter. The n-bit pointer ( rptr ) is passed to the write clock domain through the sync_r2w module. The (n-1)-bit pointer ( raddr ) is used to address the FIFO buffer.

The FIFO empty output is registered and is asserted on the next rising rclk edge when the next rptr value equals the synchronized wptr value. All module outputs are registered for simplified synthesis using time budgeting. This module is entirely synchronous to the rclk for simplified static timing analysis.

module rptr_empty #(parameter ADDRSIZE = 4)

(output reg rempty,

output [ADDRSIZE-1:0] raddr,

output reg [ADDRSIZE :0] rptr,

input [ADDRSIZE :0] rq2_wptr,

input rinc, rclk, rrst_n);

reg [ADDRSIZE:0] rbin;

wire [ADDRSIZE:0] rgraynext, rbinnext;

//-------------------

// GRAYSTYLE2 pointer

//-------------------

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) {rbin, rptr} <= 0;

else {rbin, rptr} <= {rbinnext, rgraynext};

// Memory read-address pointer (okay to use binary to address memory) assign raddr = rbin[ADDRSIZE-1:0];

assign rbinnext = rbin + (rinc & ~rempty);

assign rgraynext = (rbinnext>>1) ^ rbinnext;

//---------------------------------------------------------------

// FIFO empty when the next rptr == synchronized wptr or on reset

//---------------------------------------------------------------

assign rempty_val = (rgraynext == rq2_wptr);

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) rempty <= 1'b1;

else rempty <= rempty_val;

endmodule

Example 6 - Verilog RTL code for the read pointer and empty flag logic

6.6wptr_full.v - Write pointer & full generation logic

This module encloses all of the FIFO logic that is generated within the write clock domain (except synchronizers). The write pointer is a dual n-bit Gray code counter. The n-bit pointer ( wptr ) is passed to the read clock domain through the sync_w2r module. The (n-1)-bit pointer ( waddr ) is used to address the FIFO buffer.

The FIFO full output is registered and is asserted on the next rising wclk edge when the next modified wgnext value equals the synchronized and modified wrptr2 value (except MSBs). All module outputs are registered for simplified synthesis using time budgeting. This module is entirely synchronous to the wclk for simplified static timing analysis.

module wptr_full #(parameter ADDRSIZE = 4)

(output reg wfull,

output [ADDRSIZE-1:0] waddr,

output reg [ADDRSIZE :0] wptr,

input [ADDRSIZE :0] wq2_rptr,

input winc, wclk, wrst_n);

reg [ADDRSIZE:0] wbin;

wire [ADDRSIZE:0] wgraynext, wbinnext;

// GRAYSTYLE2 pointer

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) {wbin, wptr} <= 0;

else {wbin, wptr} <= {wbinnext, wgraynext};

// Memory write-address pointer (okay to use binary to address memory) assign waddr = wbin[ADDRSIZE-1:0];

assign wbinnext = wbin + (winc & ~wfull);

assign wgraynext = (wbinnext>>1) ^ wbinnext;

//------------------------------------------------------------------

// Simplified version of the three necessary full-tests:

// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&

// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&

// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));

//------------------------------------------------------------------

assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1],

wq2_rptr[ADDRSIZE-2:0]});

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) wfull <= 1'b0;

else wfull <= wfull_val;

endmodule

Example 7 - Verilog RTL code for the write pointer and full flag logic

7.0Comparing Gray code pointers to binary pointers

As mentioned in section 2.3, binary pointers can be used to do FIFO design if the pointers are sampled and handshaking control signals are used between the two clock domains to safely pass the sampled binary count values. Some advantages of using binary pointers over Gray code pointers:

?The technique of sampling a multi-bit value into a holding register and using synchronized handshaking control signals to pass the multi-bit value into a new clock domain can be used for passing ANY arbitrary multi-bit value across clock domains. This technique can be used to pass FIFO pointers or any multi-bit value.

?Each synchronized Gray code pointer requires 2n flip-flops (2 per pointer bit). The sampled multi-bit register requires 2n+4 flip-flops (1 per holding register bit in each clock domain, 2 flip-flops to synchronize a ready bit and 2 flip-flops to synchronize an acknowledge bit). There is no appreciable difference in the chance that either pointer style would experience metastability.

?The sampled multi-bit binary register allows arbitrary pointer changes. Gray code pointers can only increment and decrement.

?The sampled multi-bit register technique permits arbitrary FIFO depths; whereas, a Gray code pointer requires power-of-2 FIFO depths. If a design required a FIFO depth of at least 132 words, using a standard Gray code pointer would employ a FIFO depth of 256 words. Since most instantiated dual-port RAM blocks are power-of-

2 words deep, this may not be an issue.

?Using binary pointers makes it easy to calculate “almost-empty” and “almost-full” status bits using simple binary arithmetic between the pointer values.

One small disadvantage to using binary pointers over Gray code pointers is:

?Sampling and holding a binary FIFO pointer and then handshaking it across a clock boundary can delay the capture of new samples by at least two clock edges from the receiving clock domain and another two clock edges from the sending clock domain. This latency is generally not a problem but it will typically add more pessimism to the assertion of full and empty and might require additional FIFO depth to compensate for the added pessimism. Since most FIFOs are typically specified with excess depth, it is not likely that extra registers or a larger dual-port FIFO buffer size would be required.

The above comparison is worthy of consideration when selecting a method to implement a FIFO design.

8.0Conclusions

Asynchronous FIFO design requires careful attention to details from pointer generation techniques to full and empty generation. Ignorance of important details will generally result in a design that is easily verified but is also wrong. Finding FIFO design errors typically requires simulation of a gate-level FIFO design with backannotation of actual delays and a whole lot of luck!

Synchronization of FIFO pointers into the opposite clock domain is safely accomplished using Gray code pointers. Generating the FIFO-full status is perhaps the hardest part of a FIFO design. Dual n-bit Gray code counters are valuable to synchronize and n-bit pointer into the opposite clock domain and to use an (n-1)-bit pointer to do “full”comparison. Synchronizing binary FIFO pointers using techniques described in section 7.0 is another worthy technique to use when doing FIFO design.

Generating the FIFO-empty status is easily accomplished by comparing-equal the n-bit read pointer to the synchronized n-bit write pointer.

The techniques described in this paper should work with asynchronous clocks spanning small to large differences in speed.

Careful partitioning of the FIFO modules along clock boundaries with all outputs registered can facilitate synthesis and static timing analysis within the two asynchronous clock domains.

高考文科数学模拟试卷及答案

高考文科数学模拟试卷 一、选择题：本大题共10小题，每小题5分，共50分．在每小题给出的四个选项中，只有一项是符合题目要求的． 1．已知复数z满足（2﹣i）2?z=1，则z的虚部为（） A．B．C．D． 2．已知集合A={x|x2=a}，B={﹣1，0，1}，则a=1是A?B的（） A．充分不必要条件B．必要不充分条 C．充要条件D．既不充分也不必要条件 3．设单位向量的夹角为120°，，则|=（） A．3 B． C．7 D． 4．已知等差数列{a n}满足a6+a10=20，则下列选项错误的是（） A．S15=150 B．a8=10 C．a16=20 D．a4+a12=20 5．一几何体的三视图如图所示，则该几何体的体积为（） A．B．C．4﹣πD． 6．双曲线=1的顶点到其渐近线的距离为（） A． B．C． D． 7．周期为4的奇函数f（x）在[0，2]上的解析式为f（x）=，则 f（2014）+f（2015）=（） A．0 B．1 C．2 D．3

8．已知x，y满足约束条件，则z=2x+y的最大值为（） A．2 B． C．4 D． 9．在△ABC中，内角A、B、C的对边分别是a、b、c，若c2=（a﹣b）2+6，△ABC的面积为，则C=（） A．B．C．D． 10．设f′（x）为函数f（x）的导函数，已知x2f′（x）+xf（x）=lnx，f（1）=，则 下列结论正确的是（） A．xf（x）在（0，+∞）单调递增B．xf（x）在（1，+∞）单调递减 C．xf（x）在（0，+∞）上有极大值 D．xf（x）在（0，+∞）上有极小值 二、填空题：本大题共5小题，每小题5分，共25分. 11．右面的程序框图输出的S的值为． 12．在区间[﹣2，4]上随机取一个点x，若x满足x2≤m的概率为，则m= ．13．若点（a，9）在函数的图象上，则a= ． 14．已知x＞0，y＞0且2x+y=2，则的最小值为．

圆梦2015·高三年级理科数学仿真模拟试题(3)精美word版

第 1 页 共 10 页 图 1 图2 圆梦2015·高三数学（理）仿真模拟三 一、选择题：本大题共8小题，每小题5分，满分40分．在每小题给出的四个选项中，只有一项是符合题目要求的． 1．已知函数lg y x =的定义域为A ,{} 01B x x =≤≤,则A B =（ ） A ．()0,+∞ B ．[]0,1 C ．(]0,1 D ．[)0,1 2．设i 为虚数单位,若复数() ()2231i z m m m =+-+-是纯虚数,则实数m =（ ） A ．3- B ．3-或1 C ．3或1- D ．1 3 ．设函数sin 2y x x =的最小正周期为T ,最大值为A ，则（ ） A ．T π= ,A = B . T π=,2A = C ．2T π= ,A = D ．2T π=,2A = 4．某由圆柱切割获得的几何体的三视图如图1所示,其中俯视图是 中心角为60?的扇形,则该几何体的体积为（ ） A ． 3 π B ．23π C ．π D ．2π 5．给定命题p ：若20x ≥，则0x ≥； 命题q :：已知非零向量,,a b 则 “⊥a b ”是“-+=a b a b ”的充要条件. 则下列各命题中,假命题的是（ ） A ．p q ∨ B ． ()p q ?∨ C ．()p q ?∧ D ．()()p q ?∧? 6．已知函数()222,02,0 x x x f x x x x ?+≥=?-）的比值a b ,称这些比值中的最小值为这个 数表的“特征值”.当2n =时, 数表的所有可能的“特征值”最 大值为（ ） A ．3 B ． 43 C ．2 D ．32

2020年宁夏银川一中高三生物一模试题【附答案】

绝密★启 用前2020 年普通高等学校招生全国统一考试 理科综合能力测试试题卷 ( 银川一中第一次模拟考试) 注意事项： 1.答卷前，考生务必将自己的姓名、准考证号填写在答题卡上。 2.作答时，务必将答案写在答题卡上。写在本试卷及草稿纸上无效。 3.考试结束后，将本试卷和答题卡一并交回。 可能用到的相对原子质量：H-1 C-12 N-14 O-16 P-31 S-32 Cl-35.5 Ca-40 V-51 Fe-56 Cu-64 Zn-65 一、选择题：本题共13 小题，每小题6 分，在每小题给出的四个选项中，只有一项是符合题目要求的。 1.下列关于生物大分子的叙述中，正确的是 A．肺炎双球菌、烟草花叶病毒都含有核糖体和核 酸B．生物体内参与信息传递的信息分子都是蛋白 质 C.细胞质中的核酸只含核糖，细胞核中的核酸只含脱氧核糖 D.人的吞噬细胞和浆细胞结构和功能不同，根本原因是遗传信息执行情况不同 2.某农作物细胞间隙的浓度为a，细胞液的浓度为b，细胞质基质的浓度为c，在对农 作物施肥过多造成“烧苗”过程中，三者之间的关系是 A．a>b>c B．b>c>a C．a>c>b D．b>a>c 3．下列关于变异和进化的说法，正确的是 A.用秋水仙素处理单倍体植株后得到的一定是纯合子 B.在三倍体无子西瓜的培育过程中，用四倍体西瓜作母本，用二倍体西瓜作父本，得到 的种子胚细胞中含有三个染色体组 C.两个种群间的隔离一旦形成，这两个不同种群的个体之间就不能进行交配，或者即使 能交配，也不能产生可育后代 D.突变能为生物进化提供原材料，但不包括染色体数目的变异，因为该过程并没有新的 基因产生

2018年高三数学模拟试题理科

黑池中学2018级高三数学期末模拟试题理科（四） 一、选择题：本大题共12小题，每小题5分，共60分. 1.已知集合{}2,101，， -=A ，{} 2≥=x x B ，则A B =I A ．{}2,1,1- B.{ }2,1 C.{}2,1- D. {}2 2.复数1z i =-,则z 对应的点所在的象限为 A ．第一象限 B.第二象限 C.第三象限 D.第四象限 3 .下列函数中,是偶函数且在区间(0,+∞)上单调递减的函数是 A ．2x y = B ．y x = C ．y x = D ．2 1y x =-+ 4.函数 y=cos 2(x + π4 )－sin 2(x + π4 )的最小正周期为 A. 2π B. π C. π2 D. π 4 5. 以下说法错误的是 （ ） A ．命题“若x 2 -3x+2=0,则x=1”的逆否命题为“若x≠1,则x 2 -3x+2≠0” B ．“x=2”是“x 2 -3x+2=0”的充分不必要条件 C ．若命题p:存在x 0∈R,使得2 0x -x 0+1<0,则﹁p:对任意x∈R,都有x 2 -x+1≥0 D ．若p 且q 为假命题,则p,q 均为假命题 6.在等差数列{}n a 中, 1516a a +=,则5S = A ．80 B ．40 C ．31 D ．-31 7.如图为某几何体的三视图，则该几何体的体积为 A ．π16+ B ．π416+ C ．π8+ D ．π48+ 8.二项式6 21()x x +的展开式中，常数项为 A ．64 B ．30 C ． 15 D ．1 9.函数3 ()ln f x x x =-的零点所在的区间是 A ．(1,2) B ．(2,)e C ． (,3)e D ．(3,)+∞ 10.执行右边的程序框图，若0.9p =，则输出的n 为 A. 6 B. 5 C. 4 D. 3 开始 10n S ==， S p

高考文科数学模拟试题

高考文科数学模拟题 一、选择题: 1．已知集合{}{} 12,03A x x B x x =-<=<<，则A B =（） A ．{} 13x x -<”是“0<

高考数学模拟试题

高考数学模拟试题 （第一卷） 一、选择题：（每小题5分，满分60分） 1、已知集合A={x|x 2+2ax+1=0}的真子集只有一个，则a 值的集合是 A ．（﹣1，1）； B ．(﹣∞,﹣1)∪[1，+∞]； C ．{﹣1，1}； D ．{0} 2、若函数y=f(x)的反函数y=f －1(x)满足f －1(3)=0，则函数y=f(x+1)的图象必过点： A ．（0，3）； B ．（－1，3）； C ．（3，－1）； D ．（1，3） 3、已知复数z 1,z 2分别满足| z 1+i|=2，|z 2－3－3i|=3则| z 1－z 2|的最大值为： A ．5； B ．10； C ．5+13； D ．13 4、数列 ,4 3211,3211,211++++++ ……的前n 项和为： A ．12+n n ； B ．1+n n ； C ．222++n n ； D ．2+n n ； 5、极坐标方程ρsin θ=sin2θ表示的曲线是： A ．圆； B ．直线； C ．两线直线 D ．一条直线和一个圆。 6、已知一个复数的立方恰好等于它的共轭复数，则这样的复数共有： A ．3个； B ．4个； C ．5个； D ．6个。 7、如图，在正方体ABCD —A 1B 1C 1D 1中，E 、F 是异面直 线AC ，A 1D 的公垂线，则EF 和ED 1的关系是： A ． 异面； B ．平行； C ．垂直； D ．相交。 8、设(2－X)5=a 0+a 1x+a 2x+…+a 5x 5, 则a 1+a 3+a 5的值为： A ．－120； B ．－121； C ．－122； D ．－243。 9、要从一块斜边长为定值a 的直角三角形纸片剪出一块圆形纸片，圆形纸片的最大面积为： A ．2 πa 2； B ．24223a π-； C ．2πa 2； D ．2)223(a π- 10、过点（1，4）的直线在x,y 轴上的截距分别为a 和b(a,b ∈R +)，则a+b 的最小值是： A ．9； B ．8； C ．7； D ．6； 11、三人互相传球，由甲开始发球并作为第一次传球。经过5次传球后，球仍回到甲手中，则不同的传球方式共有： A ．6种； B ．8种； C ．10种； D ．16种。 12、定义在R 上的偶函数f(x)满足f(x+2)=f(x －2)，若f(x)在[﹣2，0]上递增，则 A ．f(1)>f(5.5) ; B ．f(1)

宁夏银川一中2019届高三生物上学期第一次月考试题

银川一中2019届高三年级第一次月考 理科综合试卷 命题人：本试卷分第I卷（选择题）和第II卷（非选择题）两部分。其中第II卷第33?38题为选考题, 其它题为必考题。考生作答时，将答案写在答题卡上，在本试卷上答题无效。 第I卷（共126分） 可能用到的相对原子质量（原子量）：H—1 0—16 Na—23 K—39 Mn—55 Cu—64 Ni—59 一、选择题：本题包括13小题。每小题6分，共78分，每小题只有一个选项符合题意。 1.下列有关病毒、原核生物和真核生物的描述，正确的是 A.病毒、原核生物和真核生物的共同点是遗传物质都是DM B.原核牛物和真核生物都具有完整的生物膜系统 C.病毒进入原核细胞后，细胞内的溶酶体会将其“消化” D.病毒能够借助原核生物或真核生物的核糖体来合成自身的蛋白质 2.玉米种子的萌发是种子的胚从相对静止状态变为生理活跃状态，并长成营自养生活的幼苗的过 程。下列关于该过程的叙述，正确的是 A.在萌发过程中，主要以被动运输的方式从外界吸收水和无机盐 B.在萌发过程中，细胞呼吸加强，导致细胞内有机物的总量一直减少 C.萌发过程中，各细胞的形态、结构和功能发生稳定性差异，但遗传物质没有发生变化 D.种子萌发初期增加的主要元素为C元素 3.结构与功能相统一是生物学的基本观点之一。下列叙述不能说明这一观点的是 A.叶绿体内类囊体膜堆叠使膜面积增大，利于光能充分利用 B.神经细胞轴突末梢有大量突起，有利于附着更多的神经递质受体蛋白 C.细胞骨架能维持真核细胞的形态，它与细胞的物质运输等活动有关 D.线粒体内膜向内突起形成悄，有利于附着更多的有氧呼吸有关的酶 4.自噬作用是普遍存在于大部分真核细胞屮的一种现象，是溶酶体对自身结构的吞噬降解，它是 细胞内的再循环系统。下列哪一项不属于自噬作用 A.为细胞内新细胞器的构建提供原料，即细胞结构的再循环 B.吞噬细胞吞噬受病每感染的细胞 C.衰老的细胞进入编程死亡过程屮的细胞内的吞噬 D.清除降解细胞内受损伤的细胞结构、衰老的细胞器 5.与物质跨膜运输相关的叙述正确的是

2020高考理科数学模拟试题精编

2020高考理科数学模拟试题精编 (考试用时：120分钟 试卷满分：150分) 注意事项： 1．作答选择题时，选出每小题答案后，用2B 铅笔在答题卡上对应题目选项的答案信息点涂黑；如需要改动，用橡皮擦干净后，再选涂其他答案。答案不能答在试卷上。 2．非选择题必须用黑色字迹的钢笔或签字笔作答，答案必须写在答题卡各题目指定区域内相应位置上；如需改动，先划掉原来的答案，然后再写上新答案；不准使用铅笔和涂改液。不按以上要求作答无效。 3．考生必须保证答题卡的整洁。考试结束后，将试卷和答题卡一并交回。 第Ⅰ卷 一、选择题(本大题共12小题，每小题5分，共60分．在每小题给出的四个选项中，只有一项是符合题目要求的．) 1．设全集Q ＝{x |2x 2－5x ≤0，x ∈N}，且P ?Q ，则满足条件的集合P 的个数是( ) A ．3 B ．4 C ．7 D ．8 2．若复数z ＝m (m －1)＋(m －1)i 是纯虚数，其中m 是实数，则1z ＝( ) A ．i B ．－i C ．2i D ．－2i 3．已知等差数列{a n }的公差为5，前n 项和为S n ，且a 1，a 2，a 5成等比数列，则S 6＝( ) A ．80 B ．85 C ．90 D ．95 4．小明每天上学都需要经过一个有交通信号灯的十字路口．已知十字路口的交通信号灯绿灯亮的时间为40秒，黄灯5秒，红灯45秒．如果小明每天到路口的时间是随机的，则小明上学时到十字路口需要等待的时间不少于20秒的概率是( ) A.34 B.23 C.12 D.13 5．已知以下三视图中有三个同时表示某一个三棱锥，则不是．． 该三棱锥的三视图的是( ) 6．已知p ：a ＝±1，q ：函数f (x )＝ln(x ＋a 2＋x 2)为奇函数，则p 是q 成立的( )

2020年高考文科数学模拟试卷及答案(共三套)

2020年高考文科数学模拟试卷及答案（共三套） 2020年高考文科数学模拟试卷及答案（一） 一、选择题：(本大题共12小题，每小题5分，在每小题给出的四个选项中，只有一项符合题目的要求) 1、设集合{}1 2 3 4U =，，，，集合{}2540A x x x =∈-+

高考理科数学模拟试题

高三上期第二次周练 数学（理科） 第Ⅰ卷（选择题， 共60分） 一、选择题：本大题共12个小题,每小题5分,共60分.在每小题给出的四个选项中， 只有一项是符合题目要求的. 1．设集合{}=0123A ，，，， {}=21B x x a a A =-∈，， 则=( )A B ? A. {}12， B. {}13， C. {}01 ， D. {}13-， 2．已知i 是虚数单位， 复数z 满足()12i z i +=， 则z 的虚部是（ ） A. i - B. i C. 1- D. 1 3．在等比数列{}n a 中， 13521a a a ++=， 24642a a a ++=， 则数列{}n a 的前9项的和9S =（ ） A. 255 B. 256 C. 511 D. 512 4．如图所示的阴影部分是由x 轴， 直线1x =以及曲线1x y e =-围成， 现向矩形区域OABC 内随机投掷一点， 则该点落在阴影区域的概率是（ ） A. 1e B. 21 e e -- C. 11e - D. 11e - 5．在 52)(y x x ++ 的展开式中， 含 2 5y x 的项的系数是（ ） A. 10 B. 20 C. 30 D. 60 6．已知一个简单几何体的三视图如右图所示， 则该几何体的 体积为 ( ) A. 36π+ B. 66π+ C. 312π+ D. 12 7．已知函数 ())2log(x a x f -= 在 )1,(-∞上单调递减， 则a 的取值范围是( ) A. 11<<

2018高考文科数学模拟试题

2018高考文科数学模拟试题 一、选择题： 1．已知命题，，则是成立的（ ）条件． A ．充分不必要 B ．必要不充分 C ．既不充分有不必要 D ．充要 2．已知复数，，，是虚数单位，若是实数，则（ ） A ． B ． C ． D ． 3．下列函数中既是偶函数又在上单调递增的函数是（ ） A ． B ． C ． D ． 4．已知变量，之间满足线性相关关系 ，且，之间的相关数据如下表所示：则（ ） A ．0.8 B ．1.8 C ．0.6 D ．1.6 5．若变量，满足约束条件，则的最大值是（ ） A ．0 B ．2 C ．5 D ．6 6．已知等差数列的公差和首项都不为，且成等比数列，则（ ） A ． B ． C ． D ． 7．我国古代数学名著《孙子算经》中有如下问题：“今有三女，长女五日一归，中女四日一归，少女三日一归．问：三女何日相会？”意思是：“一家出嫁的三个女儿中，大女儿每五天回一次娘家，二女儿每四天回一次娘家，小女儿每三天回一次娘家．三个女儿从娘家同一天走后，至少再隔多少天三人再次相会？”假如回娘家当天均回夫家，若当地风俗正月初二都要回娘家，则从正月初三算起的 :12p x -<<2:log 1q x

人教版2020年高考数学仿真模拟试题 文1新人教版

2019年高考数学仿真模拟试题 本试卷共6页。考试结束后，将本试卷和答题卡一并交回。 注意事项： 1．答题前，考生先将自己的姓名、准考证号码填写清楚，将条形码准 确粘贴在考生信息条形码粘贴区。 2．选择题必须使用2B 铅笔填涂；非选择题必须使用0.5毫米黑色字迹的 签字笔书写，字体工整、笔迹清楚。 3．请按照题号顺序在答题卡各题目的答题区域内作答，超出答题区域 书写的答案无效；在草稿纸、试卷上答题无效。 4．作图可先使用铅笔画出，确定后必须用黑色字迹的签字笔描黑。 5．保持卡面清洁，不要折叠，不要弄破、弄皱。不准使用涂改液、修正带、 刮纸刀。 一、选择题：本题共12小题,每小题5分,共60分。在每小题给出的四个选 项中,只有一项是符合题目要求的。 1.已知集合{}3,2,1=A ，{} Z x x x x B ∈<--= ,0322 ,则=B A Y A ．{}2,1 B ．{}3,2,1,0 C ．[]2,1 D ．[]3,0 2.复数 i i 212-+的共轭复数的虚部是 A ．53- B ．53 C ．1- D ．1 3.下列结论正确的是 A ．若直线⊥l 平面α，直线⊥l 平面β，且βα,不共面，则βα// B ．若直线//l 平面α，直线//l 平面β，则βα// C ．若两直线21l l 、与平面α所成的角相等，则21//l l D ．若直线l 上两个不同的点B A 、到平面α的距离相等，则α//l 4.已知34cos sin = -αα，则=?? ? ??-απ4cos 2 A. 91 B. 92 C. 94 D. 9 5 5.设直线l 过双曲线C 的一个焦点，且与C 的一条对称轴垂直，l 与C 交于B A 、两点，

宁夏银川一中2017届高三下学期第一次模拟理综-生物试卷含答案.doc

绝密★启用前 2017年普通高等学校招生全国统一考试 理科综合能力测试-生物部分 （银川一中第一次模拟考试） 本试卷分第I卷（选择题）和第II卷（非选择题）两部分，其中第II卷第33?40题为选考题，其它题为必考题。考生作答时，将答案答在答题卡上，在本试卷上答题无效。考试结束后，将本试卷和答题卡一并交回。 注意事项： 1. 答题前，考生务必先将自己的姓名、准考证号填写在答题卡上，认真核对条形码上的姓名、准考证号，并将条形码粘贴在答题卡的指定位置上。 2. 选择题答案使用2B铅笔填涂，如需改动，用橡皮擦干净后，再选涂其他答案的标号; 非选择题答案使用0. 5毫米的黑色中性（签字）笔或碳素笔书写，字体工整、笔迹清楚。 3. 考生必须按照题号在答题卡各题号相对应的答题区域（黑色线框）内作答，写出草稿纸上、超出答题区域或非题号对应的答题区域的答案一律无效。 4. 保持卡面清洁，不折叠，不破损。 5. 做选考题时，考生按照题目要求作答，并用2B铅笔在答题卡上把所选题目对应的题目涂黑。 可能用到的相对原子质量：H-l C-12 N-14 0-16 S-32 Fe-56 Cu-64 Ba-137 第I卷 一、选择题：本题共13小题，每小题6分，在每小题给出的四个选项中，只有一项是符合题 目要求的。 1. 破伤风杆菌一般在较深伤口内繁殖，可产生外毒素使机体发病，而外毒素的毒性可被胰蛋 白酶解除。下列有关分析错误的是 A. 破伤风杆菌的呼吸方式为无氧呼吸 B. 破伤风杆菌分泌的外毒素是在内质网上的核糖体合成的 C. 破伤风杆菌分泌的外毒素不能直接作为疫苗进行预防接种 D. 破伤风杆菌生命活动所需的能量来源于有机物的氧化分解 2. 科研人员研究小鼠癌变与基因突变的关系。如图为小鼠结肠癌发生过程中细胞形态和部分

高考数学模拟试题(文科)及答案

凹凸教育高考文科数学模拟题 本试卷分第Ⅰ卷（选择题）和第Ⅱ卷（非选择题）两部分，满分150分，考试时间120分钟. 第Ⅰ卷 一、选择题：本大题共12小题，每小题5分，共60分.在每小题给出的四个选项中，只有一项是符合题目要求的. 1．已知全集,U R =且{}{} 2|12,|680, A x x B x x x =->=-+<则()U C A B I 等于 （A ）[1,4)- （B ）(2,3] （C ）(2,3) （D ）(1,4)- 2．已知i z i 32)33(-=?+（i 是虚数单位），那么复数z 对应的点位于复平面内的 （A ）第一象限 （B ）第二象限 （C ）第三象限 （D ）第四象限 3．下列有关命题的说法正确的是 （A ）命题“若21x =，则1=x ”的否命题为：“若21x =，则1x ≠”． （B ）“1x =-”是“2560x x --=”的必要不充分条件． （C ）命题“x R ?∈，使得210x x ++<”的否定是：“x R ?∈， 均有210x x ++<”． （D ）命题“若x y =，则sin sin x y =”的逆否命题为真命题． 4．某人骑自行车沿直线匀速旅行，先前进了a 千米，休息了一段时间，又沿原路返回b 千米（)a b <，再前进c 千米，则此人离起点的距离s 与时间t 的关系示意图是 （A ） （B ） （C ） （D ） 5．已知(31)4,1()log ,1a a x a x f x x x -+

2019年高考数学模拟试题含答案

F D C B A 2019年高考数学模拟试题（理科） 注意事项： 1．本试卷分第Ⅰ卷（选择题）和第Ⅱ卷（非选择题）两部分。答卷前，考生务必将自己的姓名、准考证号填写在答题卡上。 2．回答第Ⅰ卷时，选出每小题答案后，用铅笔把答题卡上对应题目的答案标号涂黑。如需改动，用橡皮擦干净后，再选涂其他答案标号。写在本试卷上无效。 3．回答第Ⅱ卷时，将答案写在答题卡上。写在本试卷上无效。 4．考试结束后，将本试卷和答题卡一并收回。 一．选择题：本大题共12个小题，每小题5分，共60分。在每小题给出的四个选项中只有一项是符合题目要求的 1．已知集合}032{2>--=x x x A ，}4,3,2{=B ，则B A C R ?)(= A ．}3,2{ B ．}4,3,2{ C ．}2{ D ．φ 2．已知i 是虚数单位，i z += 31 ，则z z ?= A ．5 B ．10 C ． 10 1 D ． 5 1 3．执行如图所示的程序框图，若输入的点为(1,1)P ，则输出的n 值为 A ．3 B ．4 C ．5 D ．6 （第3题） （第4题） 4．如图，ABCD 是边长为8的正方形，若1 3 DE EC =，且F 为BC 的中点，则EA EF ?=

A ．10 B ．12 C ．16 D ．20 5．若实数y x ,满足?? ???≥≤-≤+012y x y y x ，则y x z 82?=的最大值是 A ．4 B ．8 C ．16 D ．32 6.一个棱锥的三视图如右图，则该棱锥的表面积为 A ．3228516++ B ．32532+ C ．32216+ D ．32216516++ 7. 5张卡片上分别写有0，1，2，3，4，若从这5张卡片中随机取出2张，则取出的2张卡片上的数字之和大于5的概率是 A ． 101 B ．51 C ．103 D ．5 4 8．设n S 是数列}{n a 的前n 项和，且11-=a ，11++?=n n n S S a ，则5a = A ． 301 B ．031- C ．021 D ．20 1 - 9. 函数()1ln 1x f x x -=+的大致图像为 10. 底面为矩形的四棱锥ABCD P -的体积为8，若⊥PA 平面ABCD ,且3=PA ，则四棱锥 ABCD P -的外接球体积最小值是

宁夏银川一中2021届高三第四次月考理综-生物试题 Word版含答案

银川一中2021届高三年级第四次月考 理科综合能力测试-生物 命题教师：注意事项： 1．答卷前，考生务必将自己的姓名、准考证号填写在答题卡上。 2．作答时，务必将答案写在答题卡上。写在本试卷及草稿纸上无效。 3．考试结束后，将本试卷和答题卡一并交回。 可能用到的相对原子质量：H-1 C-12 O-16 Ni-59 Cu-64 Mg-24 I-127 一、选择题：本题包括13小题。每小题6分，共78分，在每小题给出的四个选项中，只有一个选项符合题意。 1．脂肽是一种高效环保材料，在化妆品、洗涤工业等领域得到广泛应用,脂肽是由枯草芽孢杆菌分泌的生物表面活性剂，其结构如下图所示，下列叙述正确的是 A．该化合物的空间结构主要由氨基酸的空间结构决定 B．该化合物加热变性后仍能与双缩脲试剂产生紫色反应 C．枯草芽孢杆菌分泌脂肽需要经过内质网、高尔基体等结构 D．该化合物的合成至少要经过7次氨基酸之间的脱水缩合反应 2．2020年10月5日，诺贝尔生理学或医学奖授予哈维·阿尔特、迈克尔·霍顿和查尔斯·M·赖斯三位科学家，以表彰他们在发现“丙型肝炎病毒”（即HCV）方面作出的贡献。该病毒体呈球形，为单股正链RNA病毒（中心法则：+RNA→蛋白质；+RNA→-RNA→大量+RNA），其衣壳外包绕含脂质的囊膜，囊膜上有刺突。下列关于该病毒的说法正确的是 A．HCV的预防只需要切断传播途径和注射疫苗即可加以防控 B．HCV与HIV都可使人类染病，可通过无丝分裂延续子代 C．HCV的增殖离不开宿主细胞提供氨基酸、核苷酸和核糖体等 D．若要培养该病毒用于研究疫苗，需要提供相应的营养物质和活的大肠杆菌 3．下列有关“基本骨架”或“骨架”的叙述，错误的是 A．真核细胞中由纤维素组成细胞骨架，与细胞运动、分裂和分化有关 B．DNA分子中的脱氧核糖和磷酸交替连接排在外侧构成基本骨架

高考理科数学模拟试卷(含答案)

高考理科数学模拟试卷（含答案） 本试卷分选择题和非选择题两部分. 第Ⅰ卷(选择题)1至2页,第Ⅱ卷 (非选择题)3至4页,共4页,满分150分,考试时间120分钟. 注意事项： 1.答题前,务必将自己的姓名、考籍号填写在答题卡规定的位置上. 2.答选择题时,必须使用2B 铅笔将答题卡上对应题目的答案标号涂黑,如需改动,用橡皮擦擦干净后,再选涂其它答案标号. 3.答非选择题时,必须使用0.5毫米黑色签字笔,将答案书写在答题卡规定位置上. 4.所有题目必须在答题卡上作答,在试题卷上答题无效. 5.考试结束后,只将答题卡交回. 第Ⅰ卷 (选择题,共60分) 一、选择题：本大题共12小题,每小题5分,共60分.在每小题给出的四个选项中,只有一项是符合题目要求的. 1. 已知集合2 {1,0,1,2,3,4},{|,}A B y y x x A =-==∈,则A B =I (A){0,1,2} (B){0,1,4} (C){1,0,1,2}- (D){1,0,1,4}- 2. 已知复数1 1i z = +,则||z = (A) 2 (B)1 (D)2 3. 设函数()f x 为奇函数,当0x >时,2 ()2,f x x =-则((1))f f = (A)1- (B)2- (C)1 (D)2 4. 已知单位向量12,e e 的夹角为 2π 3 ,则122e e -= (A)3 (B)7 5. 已知双曲线22 221(0,0)x y a b a b -=>>的渐近线方程为3y x =±,则双曲线的离心率是 (B) 3 (C)10 (D)10 9 6. 在等比数列{}n a 中,10,a >则“41a a <”是“53a a <”的

密接式车钩缓冲装置检修作业指导书

作业指导书 密接式钩缓装置检修

密接式钩缓装置检修岗位作业要领 标准化密接式钩缓检修岗位安全风险提示 1.工作时必须穿戴防砸皮鞋，防止车轮碾伤或铁屑扎伤； 2.必须戴安全帽、防护眼镜，防止异物溅入眼睛； 3.检修时要轻拿轻放，检修、搬运、存放时均不得落地； 4.使用升降小车取钩时，注意安装牢固后再分解车钩。

目次 1.工前准备 (1) 2.密接式车钩装置与车体分离 (2) 3.分解钩缓装置 (3) 4.零部件检修 (7) 5.密接钩装置组装及试验 (14) 6.密接钩装车 (18) 7.钩高调整 (20) 8.完工清理 (22)

钩缓装置检修作业指导书类别：A2、A3级检修系统：车钩缓冲装置部件：密接式钩缓装置 密接式钩缓装置检修作业指导书适用车型：25T 作业人员：车辆钳工3-4名（岗位合格证）作业时间：6小时/个 工装工具：1.钢卷尺； 2.钩缓升降车； 3.活动扳手、手锤、钩引、力矩扳手； 4.托盘。作业材料：砂轮片、护目镜、扫帚、簸箕、拖布、平板调整垫 作业场所：辅库 环境要求：通风、自然采光良好 操作规程：钩缓升降车技术操作规程

参考资料： 1.《铁路客车段修规程（试行）》.（铁总运〔2014〕349号）. 2.《车辆钳工》.中国铁道出版社.2011 3.《车辆处转发中国铁路总公司运输局关于印发客车常见故障专项整治方案的通知》（辆函〔2015〕240号） 4.《中国铁路总公司运输局关于印发客车检修规程勘误的通知》（运辆客车函〔2016〕137号） 安全防护及注意事项： 1.——徒手搬运配件时，防止掉落，避免伤及人员； 2.——打磨配件时，注意力集中，避免伤及人员。 基本技术要求： 1.车钩缓冲装置整体分解下车，清除锈垢，可见部位外观检查须良好，探伤部件须露出金属本色。回转机构、连 挂系统分解检修，缓冲器、钩体、安装座状态检查，表面无裂纹。橡胶件A2修状态不良时更新，A3修时更新。 2.探伤件经热处理、调修后或经过焊修、机械加工的探伤部位须复探。 3.有力矩要求的防松螺母均须按表一标准用扭力扳手检查，其余螺母、螺栓可参考执行。 4.所有组装配件须是合格品。

2019高考文科数学模拟试卷(文科)一

2019高考文科数学模拟试卷 一、选择题 1. 已知集合{ } 2 230A x N x x =∈+-≤，则集合A 的真子集个数为 （A ）31 （B ）32 （C ）3 （D ）4 2. 若复数()()21z ai i =-+的实部为1，则其虚部为 （A ）3 （B ）3i （C ） 1 （D ）i 3.设实数2log 3a =，12 13b ??= ??? ，13 log 2c =，则有 （A ）a b c >> （B ）a c b >> （C ）b a c >> （D ）b c a >> 4.已知1 cos()43 π α+ =，则sin2α= （A ）79- （B ）79 （C ）22± （D ）79 ± 5. 宋元时期数学名著《算学启蒙》中有关于“松竹并生”的问题：松长五尺，竹长两尺，松日自半，竹日自倍，松竹何日而长等，右图是源于其思想的一个程序框图，若输入的,a b 分别为5,2，则输出的n 等于 （A ）2 （B ）3 （C ）4 （D ）5 6.如图，AB 为圆O 的一条弦，且4AB =，则OA AB =u u u r u u u r g （A ）4 （B ）-4 （C ）8 （D ）-8 7.以下命题正确的个数是 ①函数()f x 在0x x =处导数存在，若0:()0p f x '=；0:q x x =是()f x 的极值点， 则p 是q 的必要不充分条件 ②实数G 为实数a ，b 的等比中项，则G ab =± ③两个非零向量a r 与b r ，若夹角0a b

宁夏银川一中2021届高三下学期返校测试理综-生物试题

银川一中2021届高三年级返校测试 理科综合能力试卷-生物部分 命题教师：注意事项： 1．答卷前，考生务必将自己的姓名、准考证号填写在答题卡上。 2．作答时，务必将答案写在答题卡上。写在本试卷及草稿纸上无效。 3．考试结束后，将本试卷和答题卡一并交回。 可能用到的相对原子质量：H-1 N-14 O-16 Na-23 S-32 Mn-55 一、选择题：本题包括13小题。每小题6分，共78分，在每小题给出的四个选项中，只 有一个选项符合题意。 1．用驴皮熬成的阿胶已有两千多年的应用历史。其滋补作用体现为：加快新陈代谢，促进组织细胞再生和增强免疫力。下列说法正确的是 A．阿胶具有滋补作用的原因是含有对人体有益的Zn、Fe、Ca等微量元素 B．驴皮细胞的脂肪含量较低，其主要储能物质是葡萄糖 C．食用阿胶能减少人体对糖类的摄入，因为阿胶中含有的多糖主要是纤维素 D．用驴皮熬成的阿胶为人体提供的主要营养物质之一可能是必需氨基酸 2．科学家使用相同的完全培养液分别培 养水稻和番茄，一段时间后，检测培 养液中的离子浓度，如图所示。 下列说法错误的是 A．水稻和番茄对离子吸收具选择性的 直接原因与膜上载体有关 B．定期向培养液中通入空气有助于促进根细胞对离子的吸收 C．Mg和Ca等矿质元素在细胞中主要以离子形式存在 D．水稻对Mg2+和Ca2+的吸收量比水多，番茄吸收水比吸收SiO2+的量多 3．无丝分裂又叫核粒纽丝分裂，是最早被发现的一种细胞分裂方式，细胞不经过有丝分裂各时期分裂为大致相等的两部分的细胞分裂方式。下列叙述正确的是 A．无丝分裂不进行DNA分子的复制

B．蛙的红细胞和细菌都能进行无丝分裂 C．无丝分裂中，核膜和核仁不消失，没有染色体的变化 D．秋水仙素可抑制无丝分裂中细胞的分裂，从而使细胞体积增大 4．达尔文的自然选择学说，揭示了生物进化的机制，解释了适应性的形成和物种形成的原因；但其理论并不完善，现代生物进化理论极大地丰富和发展了达尔文的自然选择学说。 下列有关生物进化的描述错误的是 A．自然选择学说指出可遗传变异是生物进化的原材料，包括突变和基因重组 B．适应的形成是由于具有有利变异的个体更容易生存并留下后代，是自然选择的结果C．现代生物进化理论在分子水平和种群水平对达尔文自然选择学说进行了补充与丰富D．中性突变学说认为决定生物进化方向的是中性突变的逐渐积累，而不是自然选择5．对照实验是生物科学探究中常用的实验方法之一，设置对照实验的方法也多种多样。下列关于对照实验的说法，错误的是 A．“低温诱导染色体加倍”的实验中，作为对照的常温组也要用卡诺氏液处理 B．“探究生长素类似物促进扦插枝条生根”的预实验中，不需要设置对照实验 C．“探究血浆维持pH相对稳定”的实验中，清水组和缓冲液组都作为对照组 D．沃泰默探究狗胰液分泌调节的实验中，将稀盐酸注入狗的血液能起对照作用 6．下列说法中不属于负反馈调节的是 A．胰岛素的分泌量增加会降低血糖浓度，血糖浓度反过来影响胰岛素的分泌 B．甲状旁腺激素引起血钙含量升高，高血钙又抑制了甲状旁腺的分泌 C．一片草原的兔子数量增多，导致青草减少的同时兔的天敌数量增多，会导致兔子的数量减少 D．促甲状腺激素释放激素会促进垂体分泌促甲状腺激素，促甲状腺激素会促进甲状腺分泌甲状腺激素 29．（12分） 某研究小组利用某植物进行下列关于光合作用有关的实验： 第一步：将一植株保留一叶片a和一幼嫩果实c，b为叶片和果实连接的茎； 第二步：把处理好的植株放入一透明小室，并放到光合作用最适的温度和光照强度下培养； 第三步：向小室充入一定量14CO2，密封小室，立即用仪器测定a、b、c三处的放射性物质含量并记录；

全国高考文科数学模拟试题及答案

2017年普通高等学校招生全国统一模拟考试 文科数学 考场：___________座位号：___________ 本试卷分第I 卷（选择题）和第II 卷（非选择题）两部分。满分150分，考试时间120分 钟. 第I 卷（选择题共60分） 选择题：本大题共12小题，每小题5分，共60分.在每小题给出的四个选项中，只有一项是符合题目要求的。 (1)设集合A=｛4，5，7，9｝，B=｛3，4，7，8，9｝，全集U A B =，则集合 () U A B 中的元素共有( ) (A) 3个 （B ） 4个 （C ）5个 （D ）6个 （2）（2） 复数 3223i i +=-( ) （A ）1 （B ）1- （C ）i (D)i - （3）已知()()3,2,1,0a b =-=-，向量a b λ+与2a b -垂直，则实数λ的值为（ ） （A ）17- （B ）17 （C ）1 6 - （D ）16 （4）已知tan a =4,cot β=1 3 ,则tan(a+β)=( ) (A)711 (B)711- (C) 713 (D) 713 - （5）已知双曲线)0(13 2 22>=- a y a x 的离心率为2，则=a （ ） A. 2 B. 26 C. 2 5 D. 1 （6）已知函数()f x 的反函数为()()10g x x ＝＋2lgx ＞，则=+)1()1(g f ( ) （A ）0 （B ）1 （C ）2 （D ）4

（7）在函数①|2|cos x y =，②|cos |x y = ，③)62cos(π + =x y ,④)4 2tan(π -=x y 中，最小正周期为π的所有函数为（ ) A.①②③ B. ①③④ C. ②④ D. ①③ （8）如图，网格纸的各小格都是正方形，粗实线画出的事一个几何体的三视图，则这个几 何体是（ ） A.三棱锥 B.三棱柱 C.四棱锥 D.四棱柱 （9）若0tan >α，则( ) A. 0sin >α B. 0cos >α C. 02sin >α D. 02cos >α (10) 如果函数3cos(2)y x φ=+的图像关于点4(,0)3 π 中心对称，那么φ的最小值为( ) (A) 6π (B) 4π (C) 3π (D) 2 π （11）设,x y 满足24, 1,22,x y x y x y +≥?? -≥??-≤? 则z x y =+ ( ) （A ）有最小值2，最大值3 （B ）有最小值2，无最大值 （C ）有最大值3，无最小值 （D ）既无最小值，也无最大值 （12）已知椭圆2 2:12 x C y +=的右焦点为F,右准线l ，点A l ∈，线段AF 交C 于点B 。若3FA FB =,则AF =( ) (A) (B) 2 (C) (D) 3 第Ⅱ卷（非选择题 共90分）