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GL424-WOGXX中文资料

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Genesys Logic, Inc.
GL424
SD/MMC Flash Card Controller
Datasheet Revision 1.00 Apr. 18, 2007

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GL424 SD/MMC Flash Card Controller
Copyright:
Copyright ? 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARDTM LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
Is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://https://www.wendangku.net/doc/2917797457.html,
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GL424 SD/MMC Flash Card Controller
Revision History
Revision 0.90 1.00 Date 04/06/2006 04/18/2007 First formal release Add Die Pad, 46 PIN LGA, 51PIN LGA 1. Pin Assignment, p.11 2. Package Dimension, p.30 Description
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GL424 SD/MMC Flash Card Controller
TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 7 1.1 CARD INTERFACE ..................................................................................... 8 1.2 FLASH ACCESS INTERFACE ....................................................................... 8 1.3 EMBEDDED CPU ........................................................................................ 8 CHAPTER 2 FEATURES .............................................................................. 9 2.1 SD HOST INTERFACE ................................................................................. 9 2.2 MMC HOST INTERFACE ............................................................................ 9 2.3 FLASH MEMORY INTERFACE ..................................................................... 9 2.4 MICRO CONTROLLER AND ANALOG SYSTEM ......................................... 10 2.5 8KV-ESD PROTECTION ........................................................................... 10 2.6 DUAL CHANNEL FLASH TO REACH TOP READ/WRITE SPEED .............. 10 2.7 DUAL VOLTAGE APPLICATION ................................................................. 10 2.8 PRODUCT PACKAGES ............................................................................... 10 2.9 TECHNOLOGY........................................................................................... 10 2.10 MANUFACTURE ...................................................................................... 10 CHAPTER 3 PIN ASSIGNMENT .............................................................. 11 3.1 PINOUT ..................................................................................................... 11 3.2 PIN DESCRIPTIONS ................................................................................... 16 3.2.1 Regulator Interface......................................................................... 16 3.2.2 Card Interface ................................................................................. 18 3.2.3 Flash Interface................................................................................. 21 3.2.4 System Interface.............................................................................. 24 3.2.5 Test Interface................................................................................... 27 CHAPTER 4 ELECTRICAL CHARACTERISTICS............................... 28 4.1 ABSOLUTE MAXIMUM RATINGS .............................................................. 28 4.2 BUS OPERATING CONDITIONS ................................................................. 28 4.3 D.C. CHARACTERISTICS .......................................................................... 28 CHAPTER 5 PACKAGE DIMENSION..................................................... 30 CHAPTER 6 ORDERING INFORMATION ............................................ 34
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GL424 SD/MMC Flash Card Controller
LIST OF FIGURES
FIGURE 1. 1 - GL424 BLOCK DIAGRAM .............................................................................. 8 FIGURE 3.1 - 46 PIN LQFN PINOUT .................................................................................. 11 FIGURE 3.2 - 54 PIN VFBGA PINOUT ............................................................................... 12 FIGURE 3.3 – DIE PAD PINOUT .......................................................................................... 13 FIGURE 3.4 – 46 PIN LGA PINOUT .................................................................................... 14 FIGURE 3.5 – 51 PIN LGA PINOUT .................................................................................... 15 FIGURE 5.1- 46 PIN LQFN PACKAGE DIMENSION ........................................................... 30 FIGURE 5.2- 54 PIN VFBGA PACKAGE DIMENSION......................................................... 31 FIGURE 5.3- 46 PIN LGA PACKAGE DIMENSION ............................................................. 32 FIGURE 5.4- 51 PIN LGA PACKAGE DIMENSION ............................................................. 33
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GL424 SD/MMC Flash Card Controller
LIST OF TABLES
TABLE 3.1 - 46 PIN LQFN REGULATOR INTERFACE ....................................................... 16 TABLE 3.2 - 54 PIN VFBGA REGULATOR INTERFACE .................................................... 16 TABLE 3.3 – DIE PAD REGULATOR INTERFACE ................................................................ 16 TABLE 3.4 – 46 PIN LGA REGULATOR INTERFACE ......................................................... 17 TABLE 3.5 – 51 PIN LGA REGULATOR INTERFACE ......................................................... 17 TABLE 3.3 - 46 PIN LQFN CARD INTERFACE .................................................................. 18 TABLE 3.4 - 54 PIN VFBGA CARD INTERFACE ............................................................... 18 TABLE 3.5 – DIE PAD CARD INTERFACE ........................................................................... 19 TABLE 3.6 - 46 PIN LGA CARD INTERFACE ..................................................................... 20 TABLE 3.7 - 51 PIN LGA CARD INTERFACE ..................................................................... 20 TABLE 3.8 - 46 PIN LQFN FLASH INTERFACE ................................................................. 21 TABLE 3.9 - 54 PIN VFBGA FLASH INTERFACE .............................................................. 21 TABLE 3.10 – DIE PAD FLASH INTERFACE ........................................................................ 22 TABLE 3.11 – 46 PIN LGA FLASH INTERFACE ................................................................. 23 TABLE 3.12 – 51 PIN LGA FLASH INTERFACE ................................................................. 23 TABLE 3.13 - 46 PIN LQFN SYSTEM INTERFACE ............................................................ 24 TABLE 3.14 - 54 PIN VFBGA SYSTEM INTERFACE.......................................................... 24 TABLE 3.15 - DIE PAD SYSTEM INTERFACE ...................................................................... 25 TABLE 3.16 - 46 PIN LGA SYSTEM INTERFACE ............................................................... 26 TABLE 3.17 - 51 PIN LGA SYSTEM INTERFACE ............................................................... 26 TABLE 3.18 - 54 PIN VFBGA TEST INTERFACE .............................................................. 27 TABLE 3.19 - DIE PAD TEST INTERFACE ........................................................................... 27 TABLE 4.1 - ABSOLUTE MAXIMUM RATINGS .................................................................... 28 TABLE 4.2 - BUS OPERATING CONDITIONS ....................................................................... 28 TABLE 4.3 - D.C. CHARACTERISTICS ................................................................................ 28 TABLE 6.1- ORDERING INFORMATION .............................................................................. 34
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GL424 SD/MMC Flash Card Controller
CHAPTER 1 GENERAL DESCRIPTION
GL424 is a single-chip controller for SD and MMC memory cards. It is designed based on SD1.0/SD1.1/SD2.0 and MMC3.3/MMC4.0 specification. Its unique RAM based firmware strategy provides flexibility for fast compatibility and performance improvement, therefore, give customers strong support to win in today’s fast-changing market. With its simple interface, customers can easily apply it to SD and MMC memory cards manufacturing at the same time.
GL424 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and diagnostic, as well as power management. With a built-in flash management algorithm, GL424 is applicable for most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS.
GL424 is packaged LQFN-46 and VFBGA-54. Both die and LQFN/VFBGA package are available and completely meet SD and MMC memory card mechanical thickness requirement. card sockets provides easy PCB layout. The pin assignment that fits to
GL424 is unique in its three advanced features: (1) Dual-channel solution as well as normal single channel solution with top access speed; (2) Dual voltage for both 1.8V and 3.3V interface; (3) 8KV-ESD protecting the whole card.
VFBGA54 packaged GL424 has a dual channel flash access interface, which remarkably speed up read/write performance. It supports 16-bit flash also.
GL424 provides 8KV ESD (human body mode) and 15KV ESD (mechanical mode) protection. Especially, GL424 can also provide such high voltage ESD protection to FLASH on the whole SD/MMC card. Therefore, greatly improved SD/MMC card’s reliability and high quality in unpredictable application environment.
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GL424 SD/MMC Flash Card Controller
Flash1 Interface HOST Interface Host Interface CARD Controller Flash Access IF Flash2 Interface
GL424
Figure 1. 1 - GL424 Block Diagram
1.1 CARD Interface
The card controller, complied with SD/MMC specification, explains commands from SD/MMC host and transfers data between SD/MMC host and flash.
1.2 Flash Access Interface
The flash access interface communicates with CPU. It also manages two channels of flash, based on flash commands. Moreover, it implements defect processing, ECC, and address mapping, etc.
1.3 Embedded CPU
Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and SRAM, decodes and executes them. It also manages control and status signals between flash access interface and itself.
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GL424 SD/MMC Flash Card Controller
CHAPTER 2 FEATURES
2.1 SD Host Interface
2.2 MMC Host Interface
2.3 Flash Memory Interface
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? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Complies with SD Specification, Version 2.0 Complies with SD Specification, Version 1.1 Complies with SD Specification, Version 1.0 Supports SPI mode and CPRM functions Supports clock rate up to 25 MHz for SD1.0 Supports clock rate up to 52 MHz for SD1.1 and SD2.0 Buffers for multi-block flash memory programming DMA operation between buffers and flash memory Supports automatic CRC16 generation and verification on DATA3-0 Supports SD card exceed 4Gbytes capacity
Complies with MultiMediaCard System Specification, Version 4.0 Complies with MultiMediaCard System Specification, Version 3.3 Supports SPI mode and CPRM functions Supports clock rate up to 20 MHz for MMC3.3 Supports clock rate up to 52 MHz for MMC4.0 Buffers for multi-block flash memory programming DMA operation between buffers and flash memory Supports automatic CRC16 generation and verification on DATA7-0
Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS / MICRON / ST / HYNIX) Supports dual-channel, 16 bits flash (VFBGA54 package and die) Drives up to 4 flash memory chips, respectively (VFBGA54 package and die) Supports 64M / 128M / 256M / 512M / 1G / 2G / 4G / 8G bits flash chips Embedded firmware support for flash file system (FTL) Built-in flash management algorithm Powerful ECC for error detection and correction up to 6 bytes per 512bytes
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GL424 SD/MMC Flash Card Controller
2.4 Micro Controller and Analog System
2.5 8KV-ESD protection ? 8KV human body ESD protection (contact discharge mode) for the whole card (not only controller
chip itself)
2.6 Dual Channel FLASH to reach top Read/Write Speed
2.7 Dual voltage application
2.8 Product Packages
2.9 Technology
2.10 Manufacture
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RISC core with fast speed and less code size Flexibility to update system code Ability to add customers’ own feature
? 15KV mechanical mode ESD protection (air discharge mode) for the whole card (not only
controller chip itself)
GL424 provides dual channel flash access solution. This can reach the read/write speed almost doubled compared with single channel solution.
GL424 provides the solution for dual voltage application. This means MMC4.0 card with GL424 can work with either 1.8V or 3.3V host interface.
46-pin LQFN package 54-pin VFBGA package 46-pin LGA package 51-pin LGA package
0.18um process
Easy firmware development environment Supports firmware upgrade tool via PC
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GL424 SD/MMC Flash Card Controller
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinout
Figure 3.1 - 46 Pin LQFN Pinout
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GL424 SD/MMC Flash Card Controller
Figure 3.2 - 54 Pin VFBGA Pinout
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PAD1 PAD1 5 PAD1 6 PAD1 7 PAD1 8 PAD2 9 PAD2 0 PAD2 1 PAD2 2 PAD2 3 PAD2 4 PAD2 5 PAD2 6 PAD2 7 PAD2 8 PAD3 9 PAD3 0 PAD3 1 PAD3 2 PAD3 3 PAD3 4 PAD3 5 PAD3 6 PAD3 7 PAD3 8 PAD4 9 PAD4 0 PAD4 1 PAD4 2 PAD4 3 4 PAD_OSCO PAD_T0 PAD_T1 PAD_T2 PAD_T3 PAD_T4 PAD_T5 PAD_T6 VDDIN PAD_T7 PAD_CE0_B PAD_CE1_B PAD_ALE PAD_CLE PAD_WP_B PAD_RE_B PAD_WE_B PAD_BUSY_B PAD_DA7 PAD_DA6 PAD_DA5 V18IN VDDIN PAD_DA4 GNDIN PAD_DA3 PAD_DA2 PAD_DA1 PAD_DA0 PAD_Prt_B PAD4 PAD4 5 PAD4 6 PAD4 7 PAD4 8 PAD5 9 PAD5 0 PAD5 1 PAD5 2 PAD5 3 PAD5 4 PAD5 5 PAD5 6 PAD5 7 PAD5 8 PAD6 9 PAD6 0 1 PAD_DETECT PAD_DETECT PAD_HDATA2 PAD_HDATA2 PAD_HDATA3 PAD_HDATA3 PAD_HCMD PAD_HCMD VCC PAD_HCLK PAD_HCLK GND GND PAD_HDATA0 PAD_HDATA0 PAD_HDATA1 PAD_HDATA1
Figure 3.3 – Die Pad Pinout
GL424 SD/MMC Flash Card Controller
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GL424 SD/MMC Flash Card Controller
3.2 Pin Descriptions 3.2.1 Regulator Interface
Table 3.1 - 46 PIN LQFN Regulator Interface
Pin No. 1 2 3 4 5 6 Pin Name R1 R2 V18OUT VIN GND GNDOUT Type A A O P P P External Resistor pad External Resistor pad 1.8V output (Max.100mA) 3.3V power Ground Ground output Description
Table 3.2 - 54 PIN VFBGA Regulator Interface
Pin No.
A6 A5 B5 C4 A4 B4 G5
Pin Name
R1 R2 V18OUT V18Fsh VIN GND GNDX
Type
A A O O P P P External Resistor pad External Resistor pad
Description
1.8V output (Max.100mA) 1.8V output (Max.30mA) 3.3V power Ground Ground
Table 3.3 – Die Pad Regulator Interface
Pad No.
PAD1 PAD2 PAD3
Pad Name
R1 R2 V18-out2
Type
A A O External Resistor pad External Resistor pad
Description
1.8V output (Max.100mA) (Double Bonding) Regulator 1.8V output (Double Bonding) 1.8V output (Max.40mA)
PAD4 PAD5
V18-out2 V18-out1
O O
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GL424 SD/MMC Flash Card Controller
PAD6
VIN
P
3.3V power (Tri-bonding ) 3.3V power (Tri-bonding ) 3.3V power (Tri-bonding ) Ground (Double Bonding) Ground (Double Bonding) Ground output when enhanced 8KV-ESD protected
PAD7
VIN
P
PAD8
VIN
P
PAD9
GND
P
PAD10 PAD11
GND GNDOUT
P P
Table 3.4 – 46 PIN LGA Regulator Interface
Pin No.
16 17 18 19 20 21
Pin Name
R1 R2 V18OUT VIN GND GNDOUT
Type
A A O P P P External Resistor pad External Resistor pad
Description
1.8V output (Max.100mA) 3.3V power Ground Ground
Table 3.5 – 51 PIN LGA Regulator Interface
Pin No.
17 18 19 48 20 21 22
Pin Name
R1 R2 V18 V18Fsh VIN GND GNDX
Type
A A O O P P P External Resistor pad External Resistor pad
Description
1.8V output (Max.100mA) 1.8V output (Max.30mA) 3.3V power Ground Ground
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GL424 SD/MMC Flash Card Controller
Note :
A: Analog I: Input O: Output P: Power supply B: Bi-direction
3.2.2 Card Interface
Table 3.3 - 46 PIN LQFN Card Interface
Pin No.
20 18
Pin Name
HCLK HCMD
Type
I B HCLK from HOST
Description
SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST.
22
HDATA0
B
23
HDATA1
B
16
HDATA2
B
17 25 26 27 28
HDATA3 HDATA4 HDATA5 HDATA6 HDATA7
B B B B B
Table 3.4 - 54 PIN VFBGA Card Interface
Pin No.
H1 F2
Pin Name
HCLK HCMD
Type
I B HCLK from HOST
Description
SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST Page 18
J2
HDATA0
B
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GL424 SD/MMC Flash Card Controller
J1
HDATA1
B
SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST.
E1
HDATA2
B
F1 J3 H2 H4 H3
HDATA3 HDATA4 HDATA5 HDATA6 HDATA7
B B B B B
Table 3.5 – Die Pad Card Interface
Pad No.
PAD54 PAD55
Pad Name
PAD_HCLK PAD_HCLK
Type
B B HCLK from HOST Backup PAD (No Bonding)
Description
PAD51
PAD_HCMD
B
SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST Backup PAD (No Bonding) SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST Backup PAD (No Bonding) SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected Backup PAD (No Bonding) SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected Backup PAD (No Bonding)
PAD52
PAD_HCMD
B
PAD59
PAD_HDATA0
B
PAD58
PAD_HDATA0
B
PAD61
PAD_HDATA1
B
PAD60
PAD_HDATA1
B
PAD47
PAD_HDATA2
B
PAD48
PAD_HDATA2
B
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GL424 SD/MMC Flash Card Controller
Table 3.6 - 46 PIN LGA Card Interface
Pin No.
37 35
Pin Name
HCLK HCMD
Type
I B HCLK from HOST
Description
SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. MMC mode: HDATA6 from/to HOST. MMC mode: HDATA7 from/to HOST.
39
HDATA0
B
40
HDATA1
B
33
HDATA2
B
34 42 43 44 45
HDATA3 HDATA4 HDATA5 HDATA6 HDATA7
B B B B B
Table 3.7 - 51 PIN LGA Card Interface
Pin No.
38 36
Pin Name
HCLK HCMD
Type
I B HCLK from HOST
Description
SD/MMC mode: HCMD from/to HOST SPI mode: Data-in signal from HOST SD/MMC mode: HDATA0 from/to HOST. SPI mode: Data-out signal to HOST SD/MMC mode: HDATA1 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA2 from/to HOST. SPI mode: not connected SD/MMC mode: HDATA3 from/to HOST. SPI mode: CS signal MMC mode: HDATA4 from/to HOST. MMC mode: HDATA5 from/to HOST. Page 20
40
HDATA0
B
41
HDATA1
B
34
HDATA2
B
35 42 43
HDATA3 HDATA4 HDATA5
B B B
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