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74HCT5555D中文资料

DATA SHEET

Product speci?cation

File under Integrated Circuits, IC06

September 1993

INTEGRATED CIRCUITS

74HC/HCT5555

Programmable delay timer with oscillator

For a complete data sheet, please also download:

?The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications ?The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ?The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

FEATURES

?Positive and negative edge triggered

?Retriggerable or non-retriggerable ?Programmable delay

minimum: 100 ns

maximum: depends on input frequency and division ratio ?Divide-by range of 2 to 224?Direct reset terminates output pulse

?Very low power consumption in triggered start mode

?3 oscillator operating modes:

–RC oscillator

–Crystal oscillator

–External oscillator

?Device is unaffected by variations in temperature and V CC when using an external oscillator ?Automatic power-ON reset ?Schmitt trigger action on both trigger inputs

?Direct drive for a power transistor ?Low power consumption in active mode with respect to TTL type timers

?High precision due to digital timing ?Output capability: 20 mA

?I CC category: MSI.

APPLICATIONS

?Motor control

?Attic fan timers

?Delay circuits

?Automotive applications ?Precision timing

?Domestic appliances.GENERAL DESCRIPTION

The 74HC/HCT5555 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard

no.7A.

The 74HC/HCT5555 are precision

programmable delay timers which

consist of:

?24-stage binary counter

?integrated oscillator (using external

timing components)

?retriggerable/non-retriggerable

monostable

?automatic power-ON reset

?output control logic

?oscillator control logic

?overriding asynchronous master

reset (MR).

QUICK REFERENCE DATA

GND = 0 V; T amb = 25°C; t r = t f = 6 ns.

Notes

1.C PD is used to determine the dynamic power dissipation (P D inμW):

P D = C PD x V CC2 x f i +Σ(C L x V CC2 x f o) where:

f i = input frequency in MHz

f o = output frequency in MHz

Σ(C L x V CC2 x f o) = sum of outputs.

C L = output load capacitance in pF

V CC = supply voltage in V

2.For HC the condition is V I = GND to V CC

For HCT the condition is V I=GND to V CC?1.5 V.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS TYP.UNIT t PHL/t PLH propagation delay C L = 15 pF;

V CC= 5 V

A,B to Q/Q2424ns

MR to Q/Q1920ns

RS to Q/Q2628ns

C I input capacitance 3.5 3.5pF

C P

D power dissipation

capacitance per buffer

notes 1 and 22336pF

EXTENDED TYPE

NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE 74HC/HCT5555N16DIL plastic SOT38Z 74HC/HCT5555D16SO16plastic SOT109A

PINNING SYMBOL PIN DESCRIPTION

RS 1clock input/oscillator pin R TC 2external resistor connection C TC 3external capacitor connection A 4trigger input (positive-edge triggered)

B 5trigger input (negative-edge triggered)

RTR/RTR 6retriggerable/non-retriggerable input (active HIGH/active LOW)Q 7pulse output (active LOW)GND 8ground (0 V)

Q 9pulse output (active HIGH)S 0?S 310, 11,12, 13programmable input OSC CON 14oscillator control

MR 15master reset input (active HIGH)

V CC

positive supply voltage

Fig.1 Pin configuration.

handbook, halfpage

12345678

1514131211109

5555

GND

V CC

MGA642

R TC C TC Q

RS OSC CON

MR A B RTR/RTR

Q 0S 1S 2S S 3Fig.2 IEC logic diagram.

handbook, halfpage

MGA643

I = 0

R R

&CT = 0CT = m

V16

917

16G17

CX RX 1248X / Y CTRDIVm

[T]Y = 0

Y = 15

! G

151011121323141645

Fig.3 Functional diagram.

handbook, full pagewidth

MGA644

R TC

C TC

MONOSTABLE CIRCUITRY

Q RS OSC CON

MR A B 114154569

310111213POWER-ON RESET

RTR/RTR

OUTPUT STAGE

Q 24 - STAGE COUNTER CP

S S S S 3

FUNCTIONAL DESCRIPTION The oscillator configuration allows the design of RC or crystal oscillator circuits. The device can operate from an external clock signal applied to the RS input (R TC and C TC must not be connected). The oscillator frequency is determined by the external timing components (R T and C T ), within the frequency range 1 Hz to 4 MHz (32kHz to 20 MHz with crystal oscillator).

In the HCT version the MR input is TTL compatible but the RS input has CMOS input switching levels. The RS input can be driven by TTL input levels if RS is tied to V CC via a pull-up resistor.

The counter divides the frequency to obtain a long pulse duration. The 24-stage is digitally programmed via the select inputs (S 0 to S 3). Pin S 3 can also be used to select the test mode,which is a convenient way of functionally testing the counter.The “5555” is triggered on either the positive-edge, negative-edge or both.?Trigger pulse applied to input A for positive-edge triggering ?Trigger pulse applied input B for negative-edge triggering ?Trigger pulse applied to inputs A and B (tied together) for both positive-edge and negative triggering.

The Schmitt trigger action in the trigger inputs, transforms slowly changing input signals into sharply defined jitter-free output signals and provides the circuit with excellent noise immunity.

The OSC CON input is used to select the oscillator mode, either

continuously running (OSC CON =HIGH) or triggered start mode (OSC CON = LOW). The continuously running mode is selected where a start-up delay is an undesirable

feature and the triggered start mode is selected where very low power consumption is the primary concern.The start of the programmed time delay occurs when output Q goes HIGH (in the triggered start mode, the previously disabled oscillator will start-up). After the programmed time delay, the flip-flop stages are reset and the output returns to its original state.

An internal power-on reset is used to reset all flip-flop stages.

The output pulse can be terminated by the asynchronous overriding master reset (MR), this results in all flip-flop stages being reset. The output signal is capable of driving a power transistor. The output time delay is calculated using the following formula (minimum time delay is 100ns):

Once triggered, the output width may be extended by retriggering the gated, active HIGH-going input A or the active LOW-going input B. By repeating this process, the output pulse period (Q = HIGH,Q = LOW)can be made as long as desired. This mode is selected by RTR/RTR =HIGH. A LOW on RTR/RTR makes,once triggered, the outputs (Q,Q)independent of further transitions of inputs A and B.

f i --division ratio (s).×

TEST MODE

Set S 3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S 0,S 1 and S 2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255pulses, this sets all flip-flop stages to a logic HIGH level. Set S 3 to a logic HIGH level, this causes the counter to divide-by 224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16777216) clock pulses.FUNCTION TABLE

Notes

1.H = HIGH voltage level

L = LOW voltage level X = don't care

↑ = LOW-to-HIGH transition ↓= HIGH-to-LOW transition.

INPUTS

OUTPUTS

MR A B Q Q H X X L

H L ↑X one HIGH level output pulse one LOW level output pulse L

↓

one HIGH level output pulse

one LOW level output pulse

DELAY TIME SELECTION

SELECT INPUTS

OUTPUT Q/Q (FREQUENCY DIVIDING)S 3S 2S 1S 0BINARY

DECIMAL

L L L L 212L L L H 224L L H L 238L L H H 2416L H L L 2532L H L H 2664L H H L 27128L H H H 28256......H L L L 217131072H L L H 218262144H L H L 219524288H L H H 2201048576H H L L 2212097152H H L H 2224194304H H H L 2238388608H

224

16777216

Fig.5 Timing diagram.

Timing example shown for S 3, S 2, S 1, S 0 = 0011 (binary 24, decimal 16).

handbook, full pagewidth 1

2345678910111213141516

MGA649

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard I CC category: MSI.

DC CHARACTERISTICS FOR 74HC

SYM-BOL PARAMETER

T amb (°C)

UNIT

TEST CONDITION

+25?40to+85?40to+125V

(V)

V I OTHER MIN TYP MAX MIN MAX MIN MAX

V OH HIGH level

output voltage

Q and Q

outputs 1.9

4.4

5.9

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

2.0

4.5

6.0

I o =?20μA

V OH HIGH level

output voltage

Q and Q

outputs 3.98

5.48

4.32

5.81

3.84

5.34

3.7

5.2

4.5

6.0

I o =?6.0 mA

I o =?7.8 mA

V OH HIGH level

output voltage

Q and Q

outputs 3.3

4.8

4.5

2.7

4.2

4.5

6.0

I o =?20 mA

V OL LOW level

output voltage

Q and Q

outputs ?

0.1

2.0

4.5

6.0

I o = 20μA

V OL LOW level

output voltage

Q and Q

outputs ?

0.15

0.26

0.33

0.40

4.5

6.0

I o = 6.0 mA

I o= 7.8 mA

V OL LOW level

output voltage

Q and Q

outputs ?

0.9

1.14

1.34

4.5

6.0

I o = 20 mA

I o = 25 mA

V IH HIGH level

input voltage

RS input 1.7

3.6

4.8

1.7

3.6

4.8

1.7

3.6

4.8

4.5

6.0

V IL LOW level

input voltage

RS input ?

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

2.0

4.5

6.0

V OH HIGH level

output voltage

R TC output 3.98

5.48

3.84

5.34

3.7

5.2

4.5

6.0

RS =GND;

OSC CON

= V CC

I o =?2.6 mA

I o =?3.3 mA

3.98

5.48

3.84

5.34

3.7

5.2

4.5

6.0

RS = V CC;

OSC CON

= GND;

untriggered

I o =?0.65 mA

I o =?0.85 mA

1.9

4.4

5.9

2.0

4.5

1.9

4.4

5.9

1.9

4.4

5.9

2.0

4.5

6.0

RS = V CC;

OSC CON

= V CC

I o =?20μA

1.9

4.4

5.9

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

4.5

6.0

RS = V CC;

OSC CON

= GND;

untriggered

I o =?20μA

V OH HIGH level

output voltage

C TC output 3.98

5.48

3.84

5.34

3.7

5.2

4.5

6.0

RS = V IH;

OSC CON

= V IH

I o =?3.2 mA

I o =?4.2 mA

V OL LOW level

output voltage

R TC output ?

0.26

0.33

0.4

4.5

RS = V CC;

OSC CON

= V CC

I o = 2.6 mA I o

= 3.3 mA

0.1

2.0

4.5

RS = V CC;

OSC CON

= V CC

I o = 20μA

V OL LOW level

output voltage

C TC output ?

0.26

0.33

0.4

4.5

6.0

RS = V IL;

OSC CON

= V IL;

untriggered

I o = 3.2 mA I o

= 4.2 mA

SYM-BOL PARAMETER

T amb (°C)

UNIT

TEST CONDITION

+25?40to+85?40to+125V

(V)

V I OTHER MIN TYP MAX MIN MAX MIN MAX

AC CHARACTERISTICS FOR 74HC GND = 0 V;t r = t f = 6 ns;C L = 50 pF.

SYMBOL PARAMETER

T amb (°C)

UNIT

TEST CONDITION

+25?40to+85?40to+125V

(V)

WAVEFORMS MIN TYP MAX MIN MAX MIN MAX

t PLH/t PHL propagation

delay A,B to

Q,Q ?

240

300

360

2.0

4.5

6.0

Fig.6

t PLH/t PHL propagation

delay MR to Q,

Q ?

185

230

280

2.0

4.5

6.0

Fig.7

t PLH/t PHL propagation

delay RS to Q,

Q ?

250

315

375

2.0

4.5

6.0

Fig.8; note 1

t THL/t TLH output

transition time ?

110

2.0

4.5

6.0

Fig.6

t W trigger pulse

width

A = HIGH

B = LOW 70

105

2.0

4.5

6.0

Fig.6

t W master reset

pulse width

HIGH 70

?105

2.0

4.5

6.0

Fig.7

t W clock pulse

width RS;

HIGH or LOW 80

100

120

2.0

4.5

6.0

Fig.8

t W minimum

output pulse

width

Q = HIGH,

Q = LOW ?

275

100

2.0

4.5

6.0

Fig.6; note 1

t rt retrigger time

A,B ?

2.0

4.5

6.0

Fig.10; note 2

R EXT external timing

resistor 5

1000

2.0

5.0

Fig.13

C EXT external timing

capacitor 50

no limits

2.0

5.0

Fig.13

t rem removal time

MR to A,B 120

150

180

2.0

4.5

6.0

Fig.7

Notes

1.One stage selected.

2.It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period

exceeds the clock input cycle time divided by 2.3.One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the

RS clock input.4.One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of

the RS clock input.

f max

maximum clock pulse frequency 21012 5.91821??? 1.8810??? 1.36.68???MHz MHz MHz 2.04.56.0Fig.8; note 3

f max

maximum clock pulse frequency

63035

24.87589

???

4.82428

???

42024

???

MHz MHz MHz 2.04.56.0

Fig.9; note 4

SYMBOL

PARAMETER

T amb (°C)

UNIT

TEST CONDITION +25?40to +85?40to +125V CC (V)WAVEFORMS MIN

TYP MAX MIN MAX MIN MAX

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Speci?cations”. Output capability: non-standard; bus driver with extended speci?cation on V OH and V OL I CC category: MSI.

SYMBOL PARAMETER

T amb (°C)

UNIT

TEST CONDITION

+25?40to+85?0to+125V

(V)

V I OTHER MIN TYP MAX MIN MAX MIN MAX

V OH HIGH level

output voltage

Q and Q

outputs

4.4 4.5? 4.4? 4.4?V 4.5I o =?20μA

V OH HIGH level

output voltage

Q and Q

outputs

3.98

4.32? 3.84? 3.7?V 4.5I o =?6 mA

V OH HIGH level

output voltage

Q and Q

outputs

3.3??3? 2.7?V

4.5I o =?20 mA

V OL LOW level

output voltage

Q and Q

outputs

?00.1?0.1?0.1V 4.5I o = 20μA

V OL LOW level

output voltage

Q and Q

outputs

?0.150.26?0.33?0.40V 4.5I o = 6 mA

V OL LOW level

output voltage

Q and Q

outputs

??0.9? 1.14? 1.34V 4.5?I o = 20 mA

Notes

1.The RS input has CMOS input switching levels.

2.The value of additional quiescent supply current (?I CC ) for a unit load of 1 is given in the family specifications. To

determine ?I CC per input, multiply this value by the unit load coefficient shown in the following table.UNIT LOAD COEFFICIENT

V OH

HIGH level output

voltage R TC output

3.98?

3.84?

3.7

4.5

RS = GND;

OSC CON =V CC I o =?2.6 mA

3.98?? 3.84? 3.7?V

4.5

RS = V CC ;OSC CON = GND;untriggered I o =

?0.65 mA

4.4 4.5? 4.4? 4.4?V 4.5

RS = V CC ;OSC CON = V CC I o =?20μA

4.4 4.5? 4.4? 4.4?V 4.5

RS = V CC ;OSC CON = GND;untriggered I o =?20μA

V OH

HIGH level output

voltage C TC output 3.98?? 3.84? 3.7?V 4.5

RS = V IH ;OSC CON = V IH I o =?3.2 mA

V OL

LOW level output

voltage R TC output ??0.26?0.33?0.4V 4.5RS = V CC ;OSC CON = V CC I o = 2.6 mA

?00.1?0.1?0.1V 4.5RS = V CC ;OSC CON = V CC I o = 20μA

V OL LOW level output

voltage C TC output

??0.26?0.33?0.4V 4.5RS = V IL ;OSC CON = V IL ;

untriggered

I o = 3.2 mA

INPUT UNIT LOAD COEFFICIENT

MR 0.35A 0.69B 0.50RTR/RTR 0.35OSC CON 1.20S 0 - S 20.65S 3

0.40

SYMBOL PARAMETER

T amb (°C)

UNIT TEST CONDITION

+25

?40to +85?0to +125V

CC (V)V I

OTHER MIN TYP MAX MIN MAX

MIN MAX

AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r = t f = 6 ns;C L = 50 pF.

SYMBOL PARAMETER

T amb (°C)

UNIT

TEST CONDITION

+25?40to+85?40to+125V

(V)

WAVEFORMS MIN TYP MAX MIN MAX MIN MAX

t PLH/t PHL propagation

delay A,B to

Q,Q

?2848?60?72ns 4.5Fig.6

t PHL/t PLH propagation

delay MR to Q,

?2441?51?62ns 4.5Fig.7

t PHL/t PLH propagation

delay RS to Q,

?3254?68?81ns 4.5Fig.8; note 1

t THL/t TLH output

transition time

?715?19?22ns 4.5Fig.6

t W trigger pulse

width

A = HIGH

B=LOW

2112?26?32?ns 4.5Fig.6

t W master reset

pulse width

HIGH

145?18?21?ns 4.5Fig.7

t W clock pulse

width RS;

HIGH or LOW

169?20?24?ns 4.5Fig.8

t W minimum

output pulse

width

Q = HIGH,

Q = LOW

?100?????ns 4.5Fig.6

t rt retrigger time

A,B

?0?????ns 4.5Fig.10; note 2

R EXT external timing

resistor

1?1000????k? 4.5Fig.13

C EXT external timing

capacitor

50no limits pF 4.5Fig.13

t rem removal time

MR to A,B

2414?30?36?ns 4.5Fig.7

f max maximum

clock pulse

frequency

1018?8? 6.6?MHz 4.5Fig.8; note 3

f max maximum

clock pulse

frequency

3075?24?20?MHz 4.5Fig.9; note 4

Notes

1.One stage selected.

2.It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period

exceeds the clock input cycle time divided by 2.

3.One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the

RS clock input.

4.One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of

the RS clock input.

AC WAVEFORMS

Fig.6

Waveforms showing the triggering of the delay timer by input A or B, the minimum pulse widths of the trigger inputs A and B, the output pulse width and output transition times.

(1)HC : V M =50%; V I =GND to V CC .

HCT: V M =1.3 V; V I =GND to 3 V.

handbook, full pagewidth

t W

Q OUTPUT

MGA653

Q OUTPUT

90%

10%

A INPUT

B INPUT

V M (1)

t TLH

t THL

90%

10%

t W GND

V M

(1)

90%

10%

t W

90%

10%

t PHL t PLH

V M (1)

t TLH

t THL

Fig.7

Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Q and Q) propagation delays and the master reset to trigger inputs (A and B) removal time.

(1)HC : V M =50%; V I =GND to V CC .

HCT: V M =1.3 V; V I =GND to 3 V.

handbook, full pagewidth

t PHL

V M (1)

t W

t PLH

Q OUTPUT

MR INPUT

MGA652-1

V M (1)

Q OUTPUT

t rem

A INPUT

B INPUT

V M (1)

V M

(1)

V M (1)

t rem

Fig.8

Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency.

(1)HC : V M =50%; V I =GND to V CC .

HCT: V M =1.3 V; V I =GND to 3 V.

handbook, full pagewidth

t PHL

V M (1)

t W

t PLH

Q OUTPUT

RS INPUT

MGA651

V CC

2V M (1)

Q OUTPUT

1/f max

Fig.9

Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency (Output waveforms are not synchronized with respect to the RS waveform).

(1)HC : V M =50%; V I =GND to V CC .

HCT: V M =1.3 V; V I =GND to 3 V.

handbook, full pagewidth

t PHL V M (1)

1/f max

t PLH Q OUTPUT

RS INPUT

MGA654

V M (1)

Q OUTPUT

V M (1)

Fig.10 Output pulse control using retrigger pulse (RTR/RTR = HIGH).

(1)HC : V M =50%; V I =GND to V CC .

HCT: V M =1.3 V; V I =GND to 3 V.

handbook, full pagewidth

A INPUT

Q OUTPUT

B INPUT

t W

t r t

t W

MGA650

APPLICATION INFORMATION

Fig.11Test set-up for measuring forward

transconductance g fs = di o /dv i at v o is constant (see Fig.12) and MR = LOW.handbook, halfpage

MGA645

A output 100 F

V CC

input

0.47 F R = 560 k ?bias

i o

(f = 1 kHz)

GND

v i μμFig.12Typical forward transconductance g fs as a

function of the supply voltage at V CC at T amb = 25°C.

handbook, halfpage MBA333

1412

108

0123456

(mA/V)

CC V (V)

max.

min.

typ.

Fig.13 Application information.C t curve at R t = 100 k ?; R2 = 200 k ?.R t curve at C t = 1 nF; R2 = 2 x R t .

RC oscillator frequency as a function of R t and C t at V CC = 2 to 6 V; T amb = 25°C.

handbook, halfpage

103MGA647

104105

610105103

102

f osc (Hz)R ( )t C ( F)t 10–4

10–3

10–210–1

R t

C t

?μ

Fig.14 Example of an RC oscillator.

Typical formula for oscillator frequency:

f osc 1

2.5R t C t

××-------------------------------=handbook, halfpage

MGA646

1MR (from logic)

R TC C TC 3R t

C t