CL-PS7110中文资料
CL-PS7110
Data Book
May 1997
Version 1.5 OVERVIEW
FEATURES
s
Ultra low power
—Designed for applications that require long battery life while using standard AA/AAA batteries
—Average 20 mA in normal operation (everything on)—Average 5 mA in idle mode (clock to the CPU stopped, everything else running)
— Average 3 μ A in standby mode (realtime clock on and everything else stopped)
s Performance matching 33-MHz Intel ? ’486-based PC
— 15 Vax ? -MIPS (Dhrystone ? ) at 18 MHz
s ARM710A microprocessor
—ARM7 CPU
—8 Kbytes of four-way set-associative cache
—MMU with 64-entry TLB (transition look-aside buffer)—
Little endian
s DRAM controller
—Connects up to four banks of DRAM, with each bank being 32 bits wide and up to 256 Mbytes in size
The CL-PS7110 is designed for ultra-low-power applications such as organizers/PDAs, two-way pagers, smart phones, and hand-held internet browsers. The device’s core-logic functionality is built around an ARM710A microprocessor with 8Kbytes of four-way set-associative uni?ed cache. At 18.432 MHz (for 3-V operation), the CL-PS7110delivers nearly 15 Vax-MIPS of performance (based on Dhrystone ? benchmark) — roughly the same
(cont.)
(cont.)
DATA BOOK v1.5
2
CL-PS7110
Low-Power System-on-a-Chip
OVERVIEW (cont.)
system. The system can have an 8-bit-wide boot option to optimize memory size.
The DRAM interface allows direct connection of up to 4 banks of DRAM, each bank containing up to 256 Mbytes. To assure the lowest possible power consumption, the CL-PS7110 supports self-refresh DRAMs, which are placed a low-power state by the device when it enters its low-power standby mode.
Serial Interface
For RS232 serial communications, the CL-PS7110includes a UART with two 16-byte FIFOs for receive and transmit data. The UART supports bit rates of up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the Rx/Tx signals to/from the UART to enable these sig-nals to drive an infrared communication interface directly.
A full-duplex codec interface allows direct connec-tion of a standard codec chip to the CL-PS7110,allowing storage and playback of sound.
s ROM/SRAM/?ash memory control
—Decodes eight separate memory segments of 256 Mbytes
—Each segment can be con?gured as 8, 16, or 32 bits wide and support page-mode access
—Programmable access time for conventional SRAM/ROM/?ash memory
—Expansion device can also be a PC Card (PCMCIA) controller
s Codec interface
—Provides all necessary clocks and timing pulses and performs serialization of the data stream (or vice versa) to or from standard telephony codecs —Data transfer at 64 kbps
s Synchronous serial interface
—Supports SPI ? 1 or Microwire ? 2 -compatible interface
s 36-bit general-purpose I/O
—Four 8-bit and one 4-bit GPIO port
—Supports scanning keyboard matrix
2
Microwire is a registered trademark of National Semicon-ductor ? .
s 16C550-style UART
—Supports bit rates up to 115.2 kbps
—Contains two 16-byte FIFOs for Tx and Rx —Supports modem control signals
s SIR (slow (9600–115.2 kbps) infrared) encoder
—IrDA (Infrared Data Association) SIR protocol encoder can be optionally switched into Tx and Rx signals of the UART up to 115 kbps
s DC-to-DC converter interface
—Provides two 96-kHz clock outputs, whose duty ratio are programmable (from 1-in-16 to 15-in-16)
s LCD controller
—Interfaces directly to a single-scan panel monochrome LCD
—Panel size is programmable and is any width (line length) from 16 to 1024 pixels in 16-pixel increments
—Video frame size programmable up to 128 Kbytes —Bits per pixel programmable from 1, 2, or 4
—T wo 32-bit palette registers to support 4-, 2-, or 1-bit pixel values for mapping to any of the 16 grayscale values
s Two timer counters s Realtime clock (32-bit)
level of performance offered by a 33-MHz Intel ? ’486-based PC.
As shown in the system block diagram, simply adding desired memory and peripherals to the highly inte-grated CL-PS7110 completes a hand-held orga-nizer/PDA system board. All the interface logic is integrated on-chip.
The CL-PS7110 is packaged in a 208-pin VQFP package, with a body size of 28-mm square, lead pitch of 0.5 mm, and thickness of 1.4 mm.
Memory Interface
There are two main external memory interfaces and a DMA controller that fetches video display data for the LCD controller from main DRAM memory.The SRAM/ROM-style interface has programmable wait state timings and includes burst-mode capability,with eight chip selects decoding eight 256-Mbyte sections of addressable space. For maximum ?exibil-ity, each bank can be speci?ed to be 8, 16 or 32 bits wide to enable the use of low-cost memory in a 32-bit FEATURES
(cont.)
CL-PS7110
Low-Power System-on-a-Chip
A CL-PS7110–Based System
A separate synchronous serial interface sup-ports two industry-standard protocols (SPI?and Microwire?) for interfacing to standard devices such as an ADC, allowing for peripheral expansion such as the use of a digitizer pen. Power Management
The CL-PS7110 is designed for low-power operation. There are three basic power states:q Standby — This state is equivalent to the com-puter being switched off (no display), and the main oscillator is shut down. Only the realtime clock is running.
q Idle — In this state,the device is functioning and all oscillators are running, but the processor clock is halted while waiting for an event such as
a key press.
q Operating — This state is the same as the idle state, except that the processor clock is running.
3 DATA BOOK v1.5
DATA BOOK v1.5
4
TABLE OF CONTENTS CL-PS7110
Low-Power System-on-a-Chip
TABLE OF CONTENTS
LIST OF TABLES..............................................................................................7LIST OF FIGURES............................................................................................8CONVENTIONS................................................................................................91.
FUNCTIONAL DESCRIPTION (11)
1.1Overview..............................................................................................................................111.2General................................................................................................................................121.2.1Clocking............................................................................................................................131.2.2CPU Core.........................................................................................................................131.2.3Interrupt Controller............................................................................................................131.2.4Memory Interface and DMA..............................................................................................141.2.5Expansion and Memory Controller for SRAM/ROM/Flash Interface.................................171.2.6DRAM Controller ..............................................................................................................191.2.7PCMCIA Support..............................................................................................................191.2.8Codec Interface................................................................................................................211.2.9Synchronous Serial Interface ...........................................................................................211.2.10LCD Controller..................................................................................................................211.2.11Internal UART and SIR Encoder.......................................................................................221.2.12Timer Counters.................................................................................................................231.2.13Realtime Clock .................................................................................................................231.2.14DC-to-DC Converter.........................................................................................................231.2.15Keyboard Control..............................................................................................................261.2.16GPIO.................................................................................................................................261.2.17Buzzer Control..................................................................................................................261.2.18Battery Management........................................................................................................271.2.19State Control.....................................................................................................................271.2.20Power Management..........................................................................................................281.2.21Software Model for Power Management...........................................................................291.2.22Resets (29)
2.
PIN INFORMATION (31)
2.1Pin Diagram.........................................................................................................................312.2Pin Description Conventions................................................................................................322.3Pin Descriptions...................................................................................................................322.4
Pin Descriptions (35)
3.PROGRAMMING INTERFACE (39)
3.1Memory Map........................................................................................................................393.2Internal Registers.................................................................................................................403.2.1P ADR — Port A Data Register .........................................................................................413.2.2PBDR — Port B Data Register.........................................................................................413.2.3PCDR — Port C Data Register.........................................................................................423.2.4PDDR — Port D Data Register.........................................................................................423.2.5P ADDR — Port A Data Direction Register........................................................................423.2.6PBDDR — Port B Data Direction Register.......................................................................423.2.7PCDDR — Port C Data Direction Register.......................................................................423.2.8PDDDR — Port D Data Direction Register.. (42)
CL-PS7110
Low-Power System-on-a-Chip
3.2.9PEDR — Port E Data Register (42)
3.2.10PEDDR — Port E Data Direction Register (42)
3.2.11SYSCON — System Control Register (43)
3.2.12SYSFLG — System Status Flags Register (45)
3.2.13MEMCFG1 — Memory Con?guration Register 1 (47)
3.2.14MEMCFG2 — Memory Con?guration Register 2 (47)
3.2.15DRFPR — DRAM Refresh Period Register (49)
3.2.16INTSR — Interrupt Status Register (50)
3.2.17INTMR — Interrupt Mask Register (52)
3.2.18LCDCON — LCD Control Register (52)
3.2.19TC1D — Timer Counter 1 Data Register (53)
3.2.20TC2D — Timer Counter 2 Data Register (53)
3.2.21RTCDR — Realtime Clock Data Register (53)
3.2.22RTCMR — Realtime Clock Match Register (53)
3.2.23PMPCON — Pump Control Register (54)
3.2.24CODR — Codec Interface Data Register (54)
3.2.25UARTDR — UART Data Register (55)
3.2.26UBRLCR — UART Bit Rate and Line Control Register (55)
3.2.27P ALLSW Least-Signi?cant Word-LCD Palette Register (56)
3.2.28P ALMSW Most-Signi?cant Word-LCD Palette Register (57)
3.2.29SYNCIO Synchronous Serial Interface Data Register (58)
3.2.30STFCLR — Clear All Start Up Reason Flags Location (58)
3.2.31BLEOI — Battery Low End of Interrupt (58)
3.2.32MCEOI — Media Changed End of Interrupt (59)
3.2.33TEOI — Tick End of Interrupt Location (59)
3.2.34TC1EOI TC1 — End of Interrupt Location (59)
3.2.35TC2EOI TC2 — End Of Interrupt Location (59)
3.2.36RTCEOI — RTC Match End Of Interrupt (59)
3.2.37UMSEOI — UART Modem Status Changed End of Interrupt (59)
3.2.38COEOI — Codec End of Interrupt Location (59)
3.2.39HALT — Enter Idle State Location (59)
3.2.40STDBY — Enter Standby State Location (59)
4.ELECTRICAL SPECIFICATIONS (60)
4.1Absolute Maximum Ratings (60)
4.2Recommended Operating Conditions (60)
4.3DC Characteristics (61)
4.4AC Characteristics (62)
4.5I/O Buffer Characteristics (70)
4.6Test Modes (70)
4.6.1Oscillator and PLL Bypass Mode (71)
4.6.2Functional (EPB) Test Mode (71)
4.6.3Oscillator and PLL T est Mode (71)
4.6.4Pin Test Mode (72)
4.6.5High-Z (System) T est Mode (73)
4.6.6T est ROM Mode (73)
4.6.7Software-Selectable T est Functionality (74)
5.PACKAGE SPECIFICATIONS (75)
5.1208-Pin VQFP Package Outline Drawing (75)
5 DATA BOOK v1.5TABLE OF CONTENTS
DATA BOOK v1.5
6
TABLE OF CONTENTS CL-PS7110
Low-Power System-on-a-Chip
6.
ORDERING INFORMATION ..........................................................................76BIT INDEX.......................................................................................................77INDEX.. (79)
CL-PS7110
Low-Power System-on-a-Chip
LIST OF TABLES
Table 1-1.Interrupt Allocation (14)
Table 1-2.Physical-to-DRAM Address Mapping (19)
Table 1-3.DRAM Address Mapping (20)
Table 2-1.External Signal Functions (32)
Table 2-2.Numeric Pin Listing (35)
Table 3-1.Memory Map (39)
Table 3-2.Internal I/O Memory Locations (40)
Table 3-3.Bits in SYSCON (43)
Table 3-4.Keyboard Scan Field (43)
Table 3-5.ADCCLK Frequencies (45)
Table 3-6.Bits in the System Status Flags Register (45)
Table 3-7.Values of the Bus Width Field (48)
Table 3-8.PCMCIA Mode Bus Width (48)
Table 3-9.Values of the Random Access Wait State Field (49)
Table 3-10.Values of the Sequential Access Wait State Field (49)
Table 3-11.Sense of DC-to-DC Converter Control Lines (54)
Table 3-12.Internal UART Bit Rates (56)
Table 3-13.UART Word Length (56)
Table 3-14. Least-Signi?cant Word Palette Assignments (57)
Table 3-15.Most-Signi?cant Word Palette Assignments (57)
Table 3-16.Grayscale Value to Color Mapping (57)
Table 3-17.Bits in SYNCIO Write Register (58)
Table 4-1.DC Characteristics (61)
Table 4-2.AC Characteristics (62)
Table 4-3.I/O Buffer Output Characteristics (70)
Table 4-4.CL-PS7110 Hardware T est Modes (70)
Table 4-5.EPB Test Mode Signal Assignment (71)
Table 4-6.Oscillator and PLL T est Mode Signals (72)
Table 4-7.Chip Select Address Ranges During Test ROM Mode (73)
Table 4-8.Expansion and ROM Interface Bus Width During Test ROM Mode (73)
7 DATA BOOK v1.5LIST OF TABLES
DATA BOOK v1.5
8
LIST OF FIGURES CL-PS7110
Low-Power System-on-a-Chip
LIST OF FIGURES
Figure 1-1.Functional Block Diagram.......................................................................................11Figure 1-2.Word Write to 16-bit SRAM.....................................................................................16Figure 1-3.Word Write to 8-bit SRAM.......................................................................................17Figure 1-4.Memory Segment Usage........................................................................................18Figure 1-5.Video Buffer Mapping .............................................................................................22Figure 1-6.Sample Schematic for Positive V EE Control Circuitry .............................................25Figure 1-7.Sample Schematic for Negative V EE
Control Circuitry............................................26Figure 1-8.State Diagram.........................................................................................................28Figure 4-1.Expansion and ROM Read Timing..........................................................................63Figure 4-2.Expansion and ROM Write Timing..........................................................................64Figure 4-3.DRAM Read Cycles................................................................................................65Figure 4-4.DRAM Write Cycles................................................................................................66Figure 4-5.Video Quad Word Read..........................................................................................67Figure 4-6.DRAM CAS-Before-RAS Refresh Cycle.................................................................68Figure 4-7.
LCD Controller Timing (69)
CL-PS7110
Low-Power System-on-a-Chip
CONVENTIONS
This following section presents conventions used in this data book.
Abbreviations and Acronyms
The following table lists abbreviations and acronyms used in this data book.
Acronym or
De?nition
Abbreviation
AC alternating current
ADC analog-to-digital
codec coder/decoder
CMOS complementary metal-oxide semiconductor
CPU central processing unit
DC direct current
DMA direct-memory access
DRAM dynamic random-access memory
EPB embedded peripheral bus
FCS frame check sequence
FIFO?rst in/?rst out
GPIO general-purpose I/O
ICT in circuit test
IrDA SIR infrared data association, slow (9600–115.2 kbps) infrared
LCD liquid-crystal display
LSB least-signi?cant bit
MIPS millions of instructions per second
MMU memory management unit
PCB printed circuit board
PDA personal digital assistant
PIA peripheral interface adapter
PLL phase locked loop
PSU power supply unit
RAM random-access memory
RISC reduced-instruction-set computer
ROM read-only memory
RTC realtime clock
SRAM static random-access memory
TLB translation look-aside buffer
9 DATA BOOK v1.5CONVENTIONS
DATA BOOK v1.5
10
CONVENTIONS CL-PS7110
Low-Power System-on-a-Chip
Measurement Abbreviations
OTHER CONVENTIONS
Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For example, 14h and 03CAh are hexadecimal numbers.
Binary numbers are enclosed in single quotation marks when in text. For example, ‘11’ is a binary number.Numbers not indicated by an h or single quotation marks are decimal.
The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indicates a pin that is a ‘no connect’.
UART universal asynchronous receiver transmitter VQFP
very-tight-pitch quad ?at pack
Symbol
Units of measure
°C degree Celsius
Hz hertz (cycle per second)Kbyte kilobyte (1,024 bytes)kHz kilohertz k ?kilohm
Mbps megabits (1,048,576 bits) per second Mbyte megabyte (1,048,576 bytes)MHz megahertz (1,000 kilohertz)μF microfarad μA microampere
μs microsecond (1,000 nanoseconds)mA milliampere
ms millisecond (1,000 microseconds)ns nanosecond V volt W
watt
Acronym or Abbreviation
De?nition (cont.)
CL-PS7110
Low-Power System-on-a-Chip
1.FUNCTIONAL DESCRIPTION
1.1Overview
The CL-PS7110 is a single-device embedded controller designed to be used in ultra-low-cost applications such as a hand-held personal organizers and hand-held internet browsers. There are other devices offered by Cirrus Logic (https://www.wendangku.net/doc/2c18514028.html,) such as fax/modem chipsets, IR chipsets, codecs, etc., that can be used around the CL-PS7110 to build a complete hand-held organizer. The CL-PS7110 oper-ates at both 3 V and 5 V. However, the AC timings shown in this data book (v1.5) re?ect 3-V operation. Figure 1-1 shows a simpli?ed functional block diagram of the CL-PS7110. All external memory and peripheral devices are connected to the 32-bit data bus, using the external 28-bit address bus and control signals. Bus transfer times can be extended using the EXPRDY signal to lengthen bus cycles. The max-imum burst transfer rate of the external bus is approximately 70 Mbytes/sec.
Figure 1-1. Functional Block Diagram
The core-logic functionality is built around an ARM710A microprocessor and 8 Kbytes of cache. At 18.432 MHz (for 3-V operation) and with an on-chip 8-Kbyte cache (four-way set-associative), the CL-PS7110 delivers approximately 15 MIPS of sustained performance (18.4 MIPS peak). This is approximately the same as a 33-MHz, ’486-based PC.
11 DATA BOOK v1.5FUNCTIONAL DESCRIPTION
DATA BOOK v1.5
12
FUNCTIONAL DESCRIPTION CL-PS7110
Low-Power System-on-a-Chip
The CL-PS7110 design is optimized for low power dissipation at 3-V operation. At 18.432-MHz clock speed, the device dissipates 66 mW during the ‘operating state’ (all oscillators and processor clock run-ning), 15 mW in the ‘idle state’ (all oscillators running, but processor clock is halted), and 10-μW in the ‘standby state’ (no display and the main oscillator is shut down). For a de?nition of the three states, refer to the Section 1.2.19 on page 27.
The CL-PS7110 can interface to up to four banks of DRAM; each bank can be up to 256 Mbytes in size.There is also an interface for two ROMs, each up to 256 Mbytes, and six expansion devices also up to 256 Mbytes. These expansion devices could be additional ROM or a PC Card controller. The CL-PS7110has a built-in, high-speed (115 kbps) UART with Rx and Tx FIFOs, and also supports the IrDA SIR proto-col.
The CL-PS7110 is fabricated with a 0.6-μm CMOS process and is fully static. The CL-PS7110 is a 208-pin VQFP with a body size of 28-mm square, a lead pitch of 0.5 mm, and a maximum thickness of 1.5 mm.
1.2General
The CL-PS7110 is built around the ARM710A processor core. For a more detailed description of the ARM710A, refer to the ARM710A Data Sheet (https://www.wendangku.net/doc/2c18514028.html,/). The principle functional blocks in CL-PS7110 are:
q ARM710A CPU core
q Memory management unit from the ARM700 and ARM710 processors
q 8 Kbytes of uni?ed instruction and data cache, plus a four-way set-associative cache controller q Interrupt and fast interrupt controller
q Expansion and ROM interface giving 8 × 256-Mbyte expansion segments with independent wait state control q DRAM controller supporting Fast Page mode and self-refresh in Standby mode q 36 bits of general-purpose peripheral I/O q Telephony codec interface and 16-byte FIFO
q Programmable, 4-bits-per-pixel LCD controller, mapping the video buffer into the main DRAM
q
Full-duplex UART and two 16-byte FIFOs, plus logic to implement the IrDA SIR protocol, capable of speeds up to 115 kbps
q Two 16-bit general-purpose counter timers q A 32-bit realtime clock and comparator q DC-to-DC converter interface
q System state control and power management
q Synchronous serial interface for Microwire ? or SPI ? peripherals (such as ADCs)q Pin test and device-isolation logic q External tracing support for debug
q
Main oscillator and PLL (phase locked loop) to generate the system clock of 18.432 MHz from a 3.6864-MHz crystal
q
A low-power 32.768-kHz oscillator
CL-PS7110
Low-Power System-on-a-Chip
1.2.1Clocking
The main bus clock runs at 18.432 MHz and is derived from the output of the 3.6864-MHz oscillator, using an on-chip PLL to multiply by 10 and then divide by 2 to ensure a proper 50–50 mark space ratio is achieved. The main bus clock is routed only to the ARM710A, the LCD controller, the memory controller peripherals, and the baud-rate generator. Clocks required for the other peripherals are lower frequency, and are generally not required to be synchronous to the main bus clock. These clocks are centrally gen-erated using ripple count stages where possible to minimize power consumption, and distributed to the appropriate peripherals.
1.2.2CPU Core
The ARM710A microprocessor is a 32-bit RISC processor directly connected to the 8-Kbyte uni?ed cache. This cache has 512 lines of four words arranged as a four-way set-associative cache. The cache is directly connected to the ARM710A microprocessor and caches the virtual address from the processor. The MMU translates the virtual address into a physical address, it contains a 64-entry TLB (translation look aside buffer) and is post cache, that is, it only translates external memory references (cache misses) to save power.
Refer to descriptions of the Interrupt Status register (INTSR) and Internal Mask register (INTMR) in the ARM710A Data Sheet.
1.2.3Interrupt Controller
The ARM710A has two interrupt types: IRQ (interrupt request) and FIQ (fast interrupt request). The inter-rupt controller in the CL-PS7110 controls interrupts from 16 different sources. Twelve interrupt sources are mapped to the IRQ input and four sources are mapped to the FIQ input. FIQs have a higher priority than IRQs; if two interrupts within the same group (IRQ or FIQ) are active, software must resolve the order in which they are serviced.
All interrupts are level-sensitive,that is, they must conform to the following sequence.
1)The device asserts the appropriate interrupt request line.
2)If the appropriate bit is set in the Interrupt Mask register, either FIQ or IRQ is asserted by the interrupt con-
troller.
3)If interrupts are enabled, the processor jumps to the appropriate vector.
4)Interrupt dispatch software reads the Interrupt Status register to establish the source(s) of the interrupt, then
calls the appropriate interrupt service routine(s).
5)Software in the interrupt service routine clears the interrupt source by some action speci?c to the device
requesting the interrupt (for example, reading the UART Rx register).
6)The interrupt service routine can then re-enable interrupts, any other pending interrupts are serviced in a sim-
ilar way or returned to the interrupt dispatch code, which checks for any more pending interrupts and dis-patches them accordingly.
13 DATA BOOK v1.5FUNCTIONAL DESCRIPTION
DATA BOOK v1.5
14
FUNCTIONAL DESCRIPTION CL-PS7110
Low-Power System-on-a-Chip
1.2.4Memory Interface and DMA
The CL-PS7110 memory controller is designed for maximum ?exibility. Requests for external memory accesses from the ARM710A are decoded and the appropriate external memory access or internal bus cycle is initiated accordingly.
There are two main external memory interfaces:
q DRAM controller
q
Expansion memory controller for SRAM/FLASH/ROM
The CL-PS7110 provides a DMA controller (see Section 1.2.5) that allows video display data for the LCD controller to be fetched directly from main DRAM memory, independent of internal CL-PS7110 activity.Bus cycles generated by the CL-PS7110 depend on the requester and the target. The possible requesters are the ARM710A core, the DMA controller and the DRAM refresh controller. The two types of targets are DRAM banks and ROM/expansion banks. A data transfer may take multiple bus cycles. The arbitration for the bus is at the beginning of a transfer. The priority is ?xed with DMA highest, then refresh, followed by the ARM710A. Once granted the bus, the maximum burst to a ROM/expansion bank is four bus cycles,regardless of the transfer width. The ARM710A core can produce byte, word, multi-word accesses. Multi-
Table 1-1.
Interrupt Allocation
Interrupt
Bit in Mask and ISR
Name
Comment
FIQ 0EXTFIQ External fast interrupt input (NEXTFIQ pin).FIQ 1BLINT Battery low interrupt.FIQ 2WEINT Watch dog expired interrupt.FIQ 3MCINT Media changed interrupt.IRQ 4CSINT Codec sound interrupt.
IRQ 5EINT1External interrupt input 1 (NEINT1 pin).IRQ 6EINT2External interrupt input 2 (NEINT2 pin). IRQ 7EINT3External interrupt input 3 (EINT3 pin).IRQ 8TC1OI TC1 under ?ow interrupt.IRQ 9TC2OI TC2 under ?ow interrupt.IRQ 10RTCMI RTC compare match interrupt.IRQ 11TINT 64-Hz tick interrupt.
IRQ 12UTXINT Internal UART transmit FIFO empty interrupt.IRQ 13URXINT Internal UART receive FIFO full interrupt.IRQ 14UMSINT Internal UART modem status changed interrupt.IRQ
15
SSEOTI
Synchronous serial interface end of transfer interrupt.
CL-PS7110
Low-Power System-on-a-Chip
word accesses are produced by cache line fetches and block data transfer instructions. They can be con-sidered a burst of word reads.
Reads
For byte reads, the CL-PS7110 will rotate the data if needed so that, regardless of the width of the mem-ory bank, the addressed byte is in the correct position. The remaining bytes will be ?lled with zeros. Nor-mally, word accesses to non-word aligned addresses cause an alignment fault. However, if the alignment fault check in the MMU is not enabled, a word read from an address offset from a word boundary will cause the data to be rotated into the register as if it were a byte read. Half-word aligned reads will place the data in correct bytes of the register. T wo shift operations are then required to zero-?ll or sign extend the data.
Writes
During byte writes, the data is replicated on each of the four bytes of the data bus. For DRAM writes, there is CAS line per byte and only the CAS for the correct byte is enabled. For writes to byte-wide ROM/expan-sion banks, the nMWE signal is directly used as the write enable. For writable 16-bit ROM/expansion banks, two write enables must be decoded from the WORD, nMWE and address line A0 (refer to Figure 1-2). For writable 32-bit ROM/expansion banks, four write enables must be decoded from the same signals plus the A1 address line. A byte write always causes a single bus cycle. Word writes to word-aligned addresses are handled by the CL-PS7110, regardless of the width of the ROM/expansion bank. Accesses to 8- or 16-bit-wide banks will cause multiple bus cycles (refer to Figure 1-3). Word writes to non-word-aligned addresses normally cause a alignment fault. If the alignment fault check in the MMU is not enabled, non-aligned work writes act as if both low address bits were zero.
15 DATA BOOK v1.5FUNCTIONAL DESCRIPTION
DATA BOOK v1.5
16
FUNCTIONAL DESCRIPTION CL-PS7110
Low-Power System-on-a-Chip
NOTE:A store of 0X01234567 is split into two 16-bit stores by CL-PS7110 hardware.
Figure 1-2. Word Write to 16-bit SRAM
EXPCLK
NCS CS NMWE
A
WORD
D
EXPRDY
111111011111
0000
000014400000000000002
XXXXXXXX XXXX4567XXXX0123
NMOE
17
DATA BOOK v1.5FUNCTIONAL DESCRIPTION
CL-PS7110
Low-Power System-on-a-Chip
NOTE:A store of 0X0123456 is split into four 8-bit stores by CL-PS7110 hardware.
Figure 1-3. Word Write to 8-bit SRAM
1.2.5Expansion and Memory Controller for SRAM/ROM/Flash Interface
Eight separate linear memory or expansion segments are decoded by the CL-PS7110. Each segment is 256 Mbytes in size and can be interfaced by using a conventional SRAM-like interface. Each segment can be individually programmed to be 8, 16, or 32 bits wide, support Page mode access, and execute from 0–4 wait states. In addition, bus cycles can be extended using the EXPRDY input signal. T wo segments are allocated to ROM program segments and six to memory-mapped expansion. However, this is arbitrary and can be rede?ned. Page mode access is accomplished by running up to four accesses together, this can signi?cantly improve bus bandwidth to devices, such as ROMs. Sequential Burst mode access is always faulted (the bus returned to idle) after four accesses , regardless of bus width to allow DMA and refresh cycles.
Each memory area has a single byte control register ?eld, allowing the bus width and access timing to be programmed. Refer to the description of MEMCFG1 and MEMCFG2 registers on page 47.
EXPCLK
NCS CS NMWE
A
WORD
EXPRDY
1111101111111110
0000
000021C 00000000000001000000200000030000220
XXXXXXXX XXXXXX67XXXXXX45XXXXXX23XXXXXX01
D NMOE
DATA BOOK v1.5
18
FUNCTIONAL DESCRIPTION CL-PS7110
Low-Power System-on-a-Chip
Figure 1-4 shows the usage of such memory segments.
Figure 1-4. Memory Segment Usage
The width of each the ROM/expansion bank is set in its Memory Con?guration Register 1 (see Section 3.2.13). This register is cleared to zero by a power-on reset. The CL-PS7110 boots from ROM/expansion bank 0. To allow for booting from 8- or 32-bit memory devices, the state of port E bit 0 is sampled during power-on reset and stored into the BOOT8BIT Mode register. If this bit is low, all zeros in the width ?eld of a memory con?guration register indicates a 32-bit-wide bank and all ones a 8-bit device.If this bit is high, the decoding of the bus width ?eld is inverted, so all zeros indicates a 8-bit device.This way, a pull-up or pull-down on port E bit 0 indicates the size of the boot device. For consistency, the BOOT8BIT Mode has the same effect on all ROM/expansion banks.
The PCMCIA mode is a special case. If the width ?eld of the Memory Con?guration Register 1 is set to PCMCIA mode, the upper address bits are decoded to determine the bus width and type of access. The PCMCIA address bits A0 to A25 are driven by CL-PS7110 address bits A0 to A25. CL-PS7110 address bits A26 and A27 are decoded to specify the type and width of the access. If both are zeros, it is an access to the 8-bit-wide attribute memory. If only A26 is a one, it is an access to the 16-bit-wide common memory.If only A27 is a one, it is an access to a 8-bit-wide I/O register. If both are ones, it is an access to a 16-bit-wide I/O register.
The ARM710A core only supports byte or word accesses. Normally, word accesses are converted to mul-tiple bus cycles that match the width of the ROM/expansion bank. Word accesses to PCMCIA 16-bit-wide
CL-PS7110
Low-Power System-on-a-Chip
I/O registers are the exception. Reading or writing an I/O register may have side effects, so a single 16-bit access is needed. A byte access may trigger a side effect before the other byte is transferred, and a word access could affect neighboring I/O registers. To provide 16-bit-wide accesses, no bus width con-version is done for word accesses. Instead, there is a single bus cycle with only data bits D0 to D15 valid. If alignment fault checking is enabled in the ARM710A core, all word accesses require a word-aligned address, that is both A0 and A1 must be zero. To access the 16-bit I/O registers that are not at word-aligned addresses (that is, A1 is one), the CL-PS7110 makes special use of address bit 25. For a PCMCIA bank, if address bits A25 to A27 are all ones, the A25 output pin is driven low and the A1 output pin is driven high.This restricts 16-bit accesses to the low 32 Mbytes of the PCMCIA I/O space, but allows access to all registers in this range.
1.2.6DRAM Controller
The DRAM controller in the CL-PS7110 provides all connections to directly interface up to four banks of DRAM. Each bank is 32-bits wide and up to 256 Mbytes in size. Four RAS lines are provided, one per bank and four CAS lines are provided, one per byte line. As the DRAM device size is not programmable, if devices are used that are smaller than the largest size supported (1 Gbit) this leads to a segmented memory map, each bank being separated by 256 Mbytes. Segments that are smaller than the bank size repeat within the bank. Table 1-2 shows the mapping of physical address to DRAM row and column address. This mapping has been organized to support any DRAM device size from 4 Mbit to 1 Gbit with a ‘square’ row and column con?guration, that is, the number of column addresses is equal to the number of row addresses. If a non-square DRAM is used, further fragmentation of the memory map can occur; however, the smallest contiguous segment is always 1 Mbyte.
In addition to supporting standard refresh cycles, self-refresh DRAM is supported such that system DRAM can be put into a low-power state by the ARM710A before entering its low-power Standby mode. DMA takes priority over other external memory or I/O accesses under the control of the internal bus arbi-ter. Requests for more data are received from the FIFO buffer at the front end of the datapath through the LCD controller. The DMA request is serviced by providing a quad word of data from the frame buffer that starts at location zero in main DRAM memory. Meanwhile the CPU continues execution, including accesses to the other peripherals. Refer to Section 1.2.10 on page 21 for the description of the LCD con-troller.
1.2.7PCMCIA Support
As mentioned in Section 1.2.5 (expansion memory controller), there are eight separate linear memory segments supported and one can use one of the segments to interface with a PCMCIA card.
To design a PCMCIA-card interface to support 3/5-V cards and hot insertion, isolation buffers for address and data will be required. A sample design is provided in CL-PS7110 Evaluation kit. A P AL (22LV10) is used to decode PCMCIA card signals out of the CL-PS7110 address and control bus. The P AL equations are available in the Evaluation Kit User’s Manual.
Table 1-2.Physical-to-DRAM Address Mapping
Memory Address
DRAM
Column
DRAM Row Pin Name
0A2A10A27/DRA0
1A3A11A26/DRA1
19 DATA BOOK v1.5FUNCTIONAL DESCRIPTION
DATA BOOK v1.5
20
FUNCTIONAL DESCRIPTION CL-PS7110
Low-Power System-on-a-Chip
T able 1-3 shows the address mapping for various DRAMs with square and non-square row and address inputs assuming two ×16 devices are connected to each RAS line. This mapping is then repeated every 256 Mbytes for each DRAM bank. n is given by n = 0xC + bank number (for example, 0xC for bank 0;0xF for bank 3, etc.).2A4A12A25/DRA23A5A13A24/DRA34A6A14A23/DRA45A7A15A22/DRA56A8A16A21/DRA67A9A17A20/DRA78A19A18A19/DRA89A21A20A18/DRA910A23A22A17/DRA1011A25A24A16/DRA1112
A27
A26
A15/DRA12
Table 1-3.
DRAM Address Mapping
Device Size
Address Con?guration
Total Size of Bank
Address Range of
Segment(s)
Size of Segment(s)
4 Mbits 9 Row × 9 Column 1 Mbyte n000.0000–n00F .FFFF 1 Mbyte 16 Mbits
10 Row × 10 Column
4 Mbytes
n000.0000–n03F .FFFF 4 Mbytes
16 Mbits 12 Row × 8 Column 4 Mbytes n000.0000– n007.FFFF n010.0000–n017.FFFF n040.0000–n047.FFFF n050.0000–n057.FFFF n100.0000–n107.FFFF n110.0000–n117.FFFF n140.0000–n147.FFFF n150.0000–n157.FFFF 512 Kbytes
64 Mbits 11 Row × 11 Column 16 Mbytes n000.0000–n0FF .FFFF 16 Mbytes
64 Mbits 13 Row × 9 Column 16 Mbytes n000.0000–n01F .FFFF n040.0000–n05F .FFFF n100.0000–n11F .FFFF n140.0000–n15F .FFFF n400.0000–n41F .FFFF n440.0000–n45F .FFFF n500.0000–n51F .FFFF n540.0000–n55F .FFFF 2 Mbytes
256 Mbits 12 Row × 12 Column 64 Mbytes n000.0000–n3FF .FFFF 64 Mbytes 1 Gbit
13 Row × 13 Column
256 Mbytes
n000.0000–nFFF .FFFF
256 Mbytes
Table 1-2.
Physical-to-DRAM Address Mapping (cont.)