I2C-BUS Specification
THE I 2C-BUS SPECIFICATION
VERSION 2.1
JANUARY 2000
CONTENTS
1PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . . 3 1.2Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . 3 1.3Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . 3 1.4Purchase of Philips I2C-bus components . . 3 2THE I2C-BUS BENEFITS DESIGNERS
AND MANUFACTURERS. . . . . . . . . . . . . . .4 2.1Designer benefits . . . . . . . . . . . . . . . . . . . . 4 2.2Manufacturer benefits. . . . . . . . . . . . . . . . . 6 3INTRODUCTION TO THE I2C-BUS
SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 4THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 5GENERAL CHARACTERISTICS . . . . . . . . .8 6BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 6.1Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2START and STOP conditions. . . . . . . . . . . 9 7TRANSFERRING DATA. . . . . . . . . . . . . . .10 7.1Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 8ARBITRATION AND CLOCK
GENERATION . . . . . . . . . . . . . . . . . . . . . .11 8.1Synchronization . . . . . . . . . . . . . . . . . . . . 11 8.2Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3Use of the clock synchronizing
mechanism as a handshake. . . . . . . . . . . 13 9FORMATS WITH 7-BIT ADDRESSES. . . .13 107-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 10.1Definition of bits in the first byte . . . . . . . . 15 10.1.1General call address. . . . . . . . . . . . . . . . . 16 10.1.2START byte . . . . . . . . . . . . . . . . . . . . . . . 17 10.1.3CBUS compatibility. . . . . . . . . . . . . . . . . . 18 11EXTENSIONS TO THE STANDARD-
MODE I2C-BUS SPECIFICATION . . . . . . .19 12FAST-MODE. . . . . . . . . . . . . . . . . . . . . . . .19 13Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .20 13.1High speed transfer. . . . . . . . . . . . . . . . . . 20 13.2Serial data transfer format in Hs-mode. . . 21 13.3Switching from F/S- to Hs-mode and
back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313.4Hs-mode devices at lower speed modes. . 24 13.5Mixed speed modes on one serial bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.5.1F/S-mode transfer in a mixed-speed bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.2Hs-mode transfer in a mixed-speed bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.3Timing requirements for the bridge in a
mixed-speed bus system. . . . . . . . . . . . . . 27 1410-BIT ADDRESSING. . . . . . . . . . . . . . . . 27 14.1Definition of bits in the first two bytes. . . . . 27 14.2Formats with 10-bit addresses. . . . . . . . . . 27 14.3General call address and start byte with
10-bit addressing. . . . . . . . . . . . . . . . . . . . 30 15ELECTRICAL SPECIFICATIONS
AND TIMING FOR I/O STAGES
AND BUS LINES. . . . . . . . . . . . . . . . . . . . 30 15.1Standard- and Fast-mode devices. . . . . . . 30 15.2Hs-mode devices. . . . . . . . . . . . . . . . . . . . 34 16ELECTRICAL CONNECTIONS OF
I2C-BUS DEVICES TO THE BUS LINES . 37 16.1Maximum and minimum values of
resistors R p and R s for Standard-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 17APPLICATION INFORMATION. . . . . . . . . 41 17.1Slope-controlled output stages of
Fast-mode I2C-bus devices. . . . . . . . . . . . 41 17.2Switched pull-up circuit for Fast-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 17.3Wiring pattern of the bus lines. . . . . . . . . . 42 17.4Maximum and minimum values of
resistors R p and R s for Fast-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 17.5Maximum and minimum values of
resistors R p and R s for Hs-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 18BI-DIRECTIONAL LEVEL SHIFTER
FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 18.1Connecting devices with different
logic levels. . . . . . . . . . . . . . . . . . . . . . . . . 43 18.1.1Operation of the level shifter . . . . . . . . . . . 44 19DEVELOPMENT TOOLS AVAILABLE
FROM PHILIPS. . . . . . . . . . . . . . . . . . . . . 45 20SUPPORT LITERATURE . . . . . . . . . . . . . 46
1PREFACE
1.1Version 1.0 - 1992
This version of the 1992 I2C-bus specification includes the following modifications:
?Programming of a slave address by software has been omitted. The realization of this feature is rather complicated and has not been used.
?The “low-speed mode” has been omitted. This mode is, in fact, a subset of the total I2C-bus specification and need not be specified explicitly.
?The Fast-mode is added. This allows a fourfold increase of the bit rate up to 400kbit/s. Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100kbit/s I2C-bus system.
?10-bit addressing is added. This allows 1024 additional slave addresses.
?Slope control and input filtering for Fast-mode devices is specified to improve the EMC behaviour.
NOTE: Neither the 100kbit/s I2C-bus system nor the 100kbit/s devices have been changed.
1.2Version
2.0 - 1998
The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those requirements and includes the following modifications:
?The High-speed mode (Hs-mode) is added. This allows an increase in the bit rate up to 3.4Mbit/s. Hs-mode devices can be mixed with Fast- and Standard-mode devices on the one I2C-bus system with bit rates from 0 to 3.4Mbit/s.
?The low output level and hysteresis of devices with a supply voltage of 2V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices.
?The 0.6V at 6mA requirement for the output stages of Fast-mode devices has been omitted.
?The fixed input levels for new devices are replaced by bus voltage-related levels.
?Application information for bi-directional level shifter is added.
1.3Version
2.1 - 2000
Version 2.1 of the I2C-bus specification includes the following minor modifications:
?After a repeated START condition in Hs-mode, it is possible to stretch the clock signal SCLH (see Section13.2 and Figs22, 25 and 32).
?Some timing parameters in Hs-mode have been relaxed (see Tables6 and 7).
1.4Purchase of Philips I2C-bus components
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips.
Possible data transfer formats are:
?Master-transmitter transmits to slave-receiver. The transfer direction is not changed (see Fig.11).?Master reads slave immediately after first byte (see Fig.12). At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a not-acknowledge (A).?Combined format (see Fig.13). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A).
NOTES:
https://www.wendangku.net/doc/2218637009.html,bined formats can be used, for example, to
control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred.2.All decisions on auto-increment or decrement of
previously accessed memory locations etc. are taken by the designer of the device.3.Each byte is followed by an acknowledgment bit as
indicated by the A or A blocks in the sequence.4.I 2C-bus compatible devices must reset their bus logic
on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address, even if these START conditions are not positioned according to the proper format.5. A START condition immediately followed by a STOP
condition (void message) is an illegal format.
Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address.
The transfer direction is not changed.
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,,
,,,,,,,,,,,,MBC605
A/A
A '0' (write)
data transferred
(n bytes + acknowledge)
A = acknowledge (SDA LOW)A = not acknowledge (SDA HIGH)S = START condition P = STOP condition
R/W from master to slave from slave to master
DATA
DATA A SLAVE ADDRESS S P
Fig.12 A master reads a slave immediately after the first byte.
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,,
,,,,,,,,
MBC606
A
(read)
data transferred (n bytes + acknowledge)
R/W
A
1
P
DATA
DATA
SLAVE ADDRESS
S
A
2THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS
In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:
?Some intelligent control, usually a single-chip microcontroller
?General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters
?Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling.
To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. At present, Philips’ IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits.
Here are some of the features of the I2C-bus:
?Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)
?Each device connected to the bus is software addressable by a unique address and simple
master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers
?It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer
?Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100kbit/s in the Standard-mode, up to 400kbit/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode
?On-chip filtering rejects spikes on the bus data line to preserve data integrity ?The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400pF.
Figure1 shows two examples of I2C-bus applications. 2.1Designer benefits
I2C-bus compatible ICs allow a system design to rapidly progress directly from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus. Here are some of the features of I2C-bus compatible ICs which are particularly attractive to designers:?Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic.
?No need to design bus interfaces because the I2C-bus interface is already integrated on-chip.
?Integrated addressing and data-transfer protocol allow systems to be completely software-defined
?The same IC types can often be used in many different applications
?Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs
?ICs can be added to or removed from a system without affecting any other circuits on the bus
?Fault diagnosis and debugging are simple; malfunctions can be immediately traced
?Software development time can be reduced by assembling a library of reusable software modules.
In addition to these advantages, the CMOS ICs in the
I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems.
They all have:
?Extremely low current consumption
?High noise immunity
?Wide supply voltage range
?Wide operating temperature range.
Fig.1 Two examples of I 2C-bus applications: (a) a high performance highly-integrated TV set
(b) DECT cordless phone base-station.
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SDA SCL
MICRO-CONTROLLER PCB83C528
PLL
SYNTHESIZER
TSA5512
NON-VOLATILE MEMORY PCF8582E
STEREO / DUAL SOUND DECODER TDA9840
HI-FI AUDIO
PROCESSOR TDA9860
SINGLE-CHIP TEXT SAA52XX
M/S COLOUR DECODER TDA9160A
PICTURE SIGNAL
IMPROVEMENT
TDA4670
VIDEO
PROCESSOR
TDA4685
ON-SCREEN
DISPLAY
PCA8510
(a)MSB575
SDA
SCL
LINE
INTERFACE
PCA1070
BURST MODE CONTROLLER
PCD5042
ADPCM
PCD5032
(b)
DTMF
GENERATOR PCD3311
MICRO-CONTROLLER P80CLXXX
2.2Manufacturer benefits
I2C-bus compatible ICs don’t only assist designers, they also give a wide range of benefits to equipment manufacturers because:
?The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result - smaller and less expensive PCBs
?The completely integrated I2C-bus protocol eliminates the need for address decoders and other ‘glue logic’?The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line
?The availability of I2C-bus compatible ICs in SO (small outline), VSO (very small outline) as well as DIL packages reduces space requirements even more. These are just some of the benefits. In addition, I2C-bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around a basic model. Upgrades for new equipment, or enhanced-feature models (i.e. extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed, it’s simply a matter of selecting a micro-controller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it’s easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor.
3INTRODUCTION TO THE I2C-BUS SPECIFICATION For 8-bit oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be established:
?A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders
?The cost of connecting the various devices within the system must be minimized ?A system that performs a control function doesn’t require high-speed data transfer
?Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure.
To produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don’t have the throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system.
Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in the specification of the I2C-bus.
4THE I2C-BUS CONCEPT
The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
Table 1
Definition of I 2C-bus terminology
The I 2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let’s consider the case of a data transfer between two microcontrollers connected to the I 2C-bus (see Fig.2). This highlights the master-slave and receiver-transmitter relationships to be found on the I 2C-bus. It should be noted that these relationships are not permanent, but only
depend on the direction of data transfer at that time. The transfer of data would proceed as follows:
1) Suppose microcontroller A wants to send information to microcontroller B:
?microcontroller A (master), addresses microcontroller B (slave)?microcontroller A (master-transmitter), sends data to microcontroller B (slave- receiver)?microcontroller A terminates the transfer
2) If microcontroller A wants to receive information from microcontroller B:
?microcontroller A (master) addresses microcontroller B (slave)?microcontroller A (master- receiver) receives data from microcontroller B (slave- transmitter)?microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the transfer.
The possibility of connecting more than one
microcontroller to the I 2C-bus means that more than one master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event - an arbitration procedure has been developed. This
procedure relies on the wired-AND connection of all I 2C interfaces to the I 2C-bus.
If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line (for more detailed information concerning arbitration see Section 8).
TERM DESCRIPTION
T ransmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by a master Multi-master
More than one master can attempt to control the bus at the same time without corrupting the message Arbitration
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted
Synchronization
Procedure to synchronize the clock signals of two or more devices
Fig.2 Example of an I 2C-bus configuration using two microcontrollers.
MBC645
SDA SCL
MICRO -CONTROLLER A
STATIC RAM OR EEPROM
LCD DRIVER
GATE ARRAY
ADC
MICRO -CONTROLLER B
Generation of clock signals on the I 2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.5
GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I 2C-bus can be transferred at rates of up to 100kbit/s in the
Standard-mode, up to 400kbit/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode. The number of
interfaces connected to the bus is solely dependent on the bus capacitance limit of 400pF. For information on High-speed mode master devices, see Section 13.
6
BIT TRANSFER
Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I 2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V DD (see Section 15 for electrical specifications). One clock pulse is generated for each data bit transferred.
6.1
Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.4).Fig.3 Connection of Standard- and Fast-mode devices to the I 2C-bus.
MBC631
SCLKN1OUT SCLK IN
SCLK
DATAN1OUT DATA IN DEVICE 1
SDA (Serial Data Line)SCL (Serial Clock Line)
SCLKN2OUT SCLK IN
SCLK DATAN2OUT DATA IN DEVICE 2
V DD
R p
R p
pull-up resistors
Fig.4 Bit transfer on the I 2C-bus.
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MBC621
data line stable;data valid
change of data allowed
SDA
SCL
6.2START and STOP conditions
Within the procedure of the I 2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions (see Fig.5).
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is specified in Section 15.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (see Fig. 10). For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However,
microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.
Fig.5 START and STOP conditions.
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MBC622
SDA SCL
P
STOP condition
SDA
SCL
S
START condition
7TRANSFERRING DATA 7.1
Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see Fig.6). If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data and releases clock line SCL.
In some cases, it’s permitted to use a different format from the I 2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated (see Section 10.1.3).7.2
Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse (see Fig.7). Of course, set-up and hold times (specified in Section 15) must also be taken into account.
Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received, except when the message starts with a CBUS address (see Section 10.1.3).
When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the
not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates a STOP or a repeated START condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition.
Fig.6 Data transfer on the I 2C-bus.
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MSC608
Sr or P
SDA
Sr
P
SCL
STOP or repeated START
condition
S or Sr
START or repeated START
condition
12 3 - 89ACK
9ACK
7812MSB
acknowledgement signal from slave
byte complete,interrupt within slave
clock line held low while interrupts are serviced
acknowledgement signal from receiver
Fig.7 Acknowledge on the I 2C-bus.
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MBC602
S START condition
9
821clock pulse for acknowledgement
not acknowledge
acknowledge
DATA OUTPUT BY TRANSMITTER
DATA OUTPUT BY RECEIVER
SCL FROM MASTER
8ARBITRATION AND CLOCK GENERATION 8.1
Synchronization
All masters generate their own clock on the SCL line to transfer messages on the I 2C-bus. Data is only valid during the HIGH period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to take place.
Clock synchronization is performed using the wired-AND connection of I 2C interfaces to the SCL line. This means
that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached (see Fig.8). However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time.
Fig.8 Clock synchronization during the arbitration procedure.
CLK 1
CLK 2
SCL
counter reset
wait state
start counting HIGH period
MBC632
When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW.In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.8.2
Arbitration
A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (t HD;STA ) of the START condition which results in a defined START condition to the bus.
Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is
transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits (addressing information is given in Sections 10 and 14). If the masters are each trying
to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter, or acknowledge-bits if they are master-receiver. Because address and data information on the I 2C-bus is determined by the winning master, no information is lost during the arbitration process.
A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration.
As an Hs-mode master has a unique 8-bit master code, it will always finish the arbitration during the first byte (see Section 13).
If a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing
master must therefore switch over immediately to its slave mode.
Figure 9 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the data transfer initiated by the winning master.
Fig.9 Arbitration procedure of two masters.
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MSC609
DATA 1
DATA 2
SDA
SCL
S
master 1 loses arbitration
DATA 1 SDA
Since control of the I 2C-bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I 2C-bus. If it’s possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isn’t allowed between:
?A repeated START condition and a data bit ?A STOP condition and a data bit
?A repeated START condition and a STOP condition.
Slaves are not involved in the arbitration procedure.8.3Use of the clock synchronizing mechanism as a handshake In addition to being used during the arbitration procedure, the clock synchronization mechanism can be used to
enable receivers to cope with fast data transfers, on either a byte level or a bit level.
On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can
then hold the SCL line LOW after reception and
acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure (see Fig.6).
On the bit level, a device such as a microcontroller with or without limited hardware for the I 2C-bus, can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device.
In Hs-mode, this handshake feature can only be used on byte level (see Section 13).9
FORMATS WITH 7-BIT ADDRESSES
Data transfers follow the format shown in Fig.10. After the START condition (S), a slave address is sent. This
address is 7bits long followed by an eighth bit which is a
data direction bit (R/W) - a ‘zero’ indicates a transmission
(WRITE), a ‘one’ indicates a request for data (READ). A
data transfer is always terminated by a STOP condition (P)
generated by the master. However, if a master still wishes
to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without
first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Fig.10 A complete data transfer.
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S 1 – 789 1 – 789 1 – 789
P
STOP condition
START condition
DATA ACK
DATA ACK ADDRESS ACK R/W SDA
SCL
MBC604
Fig.13 Combined format.
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MBC607
DATA A R/W read or write
A/A DATA A R/W (n bytes + ack.)direction of transfer may change at this point.
read or write
(n bytes + ack.)Sr = repeated START condition
A/A *
**not shaded because
transfer direction of
data and acknowledge bits depends on R/W bits.
SLAVE ADDRESS S Sr P
SLAVE ADDRESS 107-BIT ADDRESSING
The addressing procedure for the I 2C-bus is such that the first byte after the START condition usually determines which slave will be selected by the master. The exception is the ‘general call’ address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. However, devices can be made to ignore this address. The second byte of the general call address then defines the action to be taken. This procedure is explained in more detail in
Section 10.1.1. For information on 10-bit addressing, see Section 1410.1
Definition of bits in the first byte
The first seven bits of the first byte make up the slave
address (see Fig.14). The eighth bit is the LSB (least significant bit). It determines the direction of the message. A ‘zero’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘one’ in this position means that the master will read information from the slave.
When an address is sent, each device in a system
compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit.
A slave address can be made-up of a fixed and a programmable part. Since it’s likely that there will be several identical devices in a system, the programmable part of the slave address enables the maximum possible number of such devices to be connected to the I 2C-bus. The number of programmable address bits of a device depends on the number of pins available. For example, if a device has 4 fixed and 3 programmable address bits, a total of 8 identical devices can be connected to the same bus.
The I 2C-bus committee coordinates allocation of I 2C addresses. Further information can be obtained from the Philips representatives listed on the back cover. Two groups of eight addresses (0000XXX and 1111XXX) are reserved for the purposes shown in Table 2. The bit
combination 11110XX of the slave address is reserved for 10-bit addressing (see Section 14).
Fig.14 The first byte after the START procedure.
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MBC608
R/W
LSB MSB slave address
Table 2Definition of bits in the first byte
Notes
1. No device is allowed to acknowledge at the reception
of the START byte.
2.The CBUS address has been reserved to enable the
inter-mixing of CBUS compatible and I2C-bus
compatible devices in the same system. I2C-bus
compatible devices are not allowed to respond on
reception of this address.
3.The address reserved for a different bus format is
included to enable I2C and other protocols to be mixed.
Only I2C-bus compatible devices that can work with such formats and protocols are allowed to respond to this address.
10.1.1G ENERAL CALL ADDRESS
The general call address is for addressing every device connected to the I2C-bus. However, if a device doesn’t need any of the data supplied within the general call structure, it can ignore this address by not issuing an acknowledgment. If a device does require data from a general call address, it will acknowledge this address and behave as a slave- receiver. The second and following bytes will be acknowledged by every slave- receiver capable of handling this data. A slave which cannot process one of these bytes must ignore it by
not-acknowledging. The meaning of the general call address is always specified in the second byte (see Fig.15).
There are two cases to consider:
?When the least significant bit B is a ‘zero’.
?When the least significant bit B is a ‘one’.When bit B is a ‘zero’; the second byte has the following definition:
?00000110 (H‘06’). Reset and write programmable part of slave address by hardware. On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset and take in the programmable part of their address. Pre-cautions have to be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage, since these low levels would block the bus.?00000100 (H‘04’). Write programmable part of slave address by hardware. All devices which define the programmable part of their address by hardware (and which respond to the general call address) will latch this programmable part at the reception of this two byte sequence. The device will not reset.
?00000000 (H‘00’). This code is not allowed to be used as the second byte.
Sequences of programming procedure are published in the appropriate device data sheets.
The remaining codes have not been fixed and devices must ignore them.
When bit B is a ‘one’; the 2-byte sequence is a ‘hardware general call’. This means that the sequence is transmitted by a hardware master device, such as a keyboard scanner, which cannot be programmed to transmit a desired slave address. Since a hardware master doesn’t know in advance to which device the message has to be transferred, it can only generate this hardware general call and its own address - identifying itself to the system (see Fig.16).
The seven bits remaining in the second byte contain the address of the hardware master. This address is recognized by an intelligent device (e.g. a microcontroller) connected to the bus which will then direct the information from the hardware master. If the hardware master can also act as a slave, the slave address is identical to the master address.
SLAVE
ADDRESS
R/W BIT DESCRIPTION 0000 0000General call address 0000 0001ST ART byte(1)
0000 001X CBUS address(2)
0000 010X Reserved for different bus
format(3)
0000 011X Reserved for future purposes 0000 1XX X Hs-mode master code
1111 1XX X Reserved for future purposes 1111 0XX X10-bit slave addressing
Fig.15 General call address format.
MBC623
LSB
second byte
00000000A X X X X X X X B A
first byte
(general call address)
Fig.16 Data transfer from a hardware master-transmitter.
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MBC624
general call address
(B)
A A second byte
A A (n bytes + ack.)
S 00000000MASTER ADDRESS
1P
DATA DATA In some systems, an alternative could be that the
hardware master transmitter is set in the slave-receiver mode after the system reset. In this way, a system configuring master can tell the hardware master-
transmitter (which is now in slave-receiver mode) to which address data must be sent (see Fig.17). After this
programming procedure, the hardware master remains in the master-transmitter mode.10.1.2
ST ART BYTE
Microcontrollers can be connected to the I 2C-bus in two ways. A microcontroller with an on-chip hardware I 2C-bus interface can be programmed to be only interrupted by requests from the bus. When the device doesn’t have such
an interface, it must constantly monitor the bus via
software. Obviously, the more times the microcontroller monitors, or polls the bus, the less time it can spend carrying out its intended function.
There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling.
In this case, data transfer can be preceded by a start procedure which is much longer than normal (see Fig.18). The start procedure consists of:?A START condition (S)?A START byte (00000001)?An acknowledge clock pulse (ACK)?A repeated START condition (Sr).
Fig.17 Data transfer by a hardware-transmitter capable of dumping data directly to slave devices. (a) Configuring master sends dump address to hardware master
(b) Hardware master dumps data to selected slave.
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,,,,,,,,,
,,,,,,
,,,,,,,,,,,,MBC609
write
A
A (a)
(b)
R/W write
A A (n bytes + ack.)
A/A
R/W S P
SLAVE ADDR. H/W MASTER DUMP ADDR. FOR H/W MASTER X S
P
DUMP ADDR. FROM H/W MASTER DATA DATA
Fig.18 START byte procedure.MBC633
S
9
8
2
1
Sr
7
ACK
dummy
acknowledge
(HIGH)
start byte 00000001
SDA SCL
After the START condition S has been transmitted by a master which requires bus access, the START byte (00000001) is transmitted. Another microcontroller can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the START byte is detected. After detection of this LOW level on the SDA line, the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization.
A hardware receiver will reset on receipt of the repeated START condition Sr and will therefore ignore the START byte.
An acknowledge-related clock pulse is generated after the START byte. This is present only to conform with the byte handling format used on the bus. No device is allowed to acknowledge the START byte.10.1.3CBUS COMPATIBILITY
CBUS receivers can be connected to the Standard-mode I2C-bus. However, a third bus line called DLEN must then be connected and the acknowledge bit omitted. Normally, I2C transmissions are sequences of 8-bit bytes; CBUS compatible devices have different formats.
In a mixed bus structure, I2C-bus devices must not respond to the CBUS message. For this reason, a special CBUS address (0000001X) to which no I2C-bus compatible device will respond, has been reserved. After transmission of the CBUS address, the DLEN line can be made active and a CBUS-format transmission sent (see Fig.19). After the STOP condition, all devices are again ready to accept data.
Master-transmitters can send CBUS formats after sending the CBUS address. The transmission is ended by a STOP condition, recognized by all devices.
NOTE: If the CBUS configuration is known, and expansion with CBUS compatible devices isn’t foreseen, the designer is allowed to adapt the hold time to the specific requirements of the device(s) used.
MBC634
S P STOP condition
CBUS load pulse
n - data bits
CBUS address
START condition
R/W bit
ACK related clock pulse
SDA
SCL
DLEN
Fig.19 Data format of transmissions with CBUS transmitter/receiver.
11EXTENSIONS TO THE STANDARD-MODE I 2C-BUS
SPECIFICATION The Standard-mode I 2C-bus specification, with its data transfer rate of up to 100kbit/s and 7-bit addressing, has been in existence since the beginning of the 1980’s. This concept rapidly grew in popularity and is today accepted worldwide as a de facto standard with several hundred different compatible ICs on offer from Philips
Semiconductors and other suppliers. To meet the
demands for higher speeds, as well as make available more slave address for the growing number of new devices, the Standard-mode I 2C-bus specification was upgraded over the years and today is available with the following extensions:
? Fast-mode , with a bit rate up to 400kbit/s.
? High-speed mode (Hs-mode), with a bit rate up to 3.4Mbit/s.?10-bit addressing , which allows the use of up to 1024 additional slave addresses.There are two main reasons for extending the regular I 2C-bus specification:
?Many of today’s applications need to transfer large amounts of serial data and require bit rates far in excess of 100kbit/s (Standard-mode), or even 400kbit/s
(Fast-mode). As a result of continuing improvements in semiconductor technologies, I 2C-bus devices are now available with bit rates of up to 3.4Mbit/s (Hs-mode) without any noticeable increases in the manufacturing cost of the interface circuitry.?As most of the 112addresses available with the 7-bit addressing scheme were soon allocated, it became apparent that more address combinations were required to prevent problems with the allocation of slave
addresses for new devices. This problem was resolved with the new 10-bit addressing scheme, which allowed about a tenfold increase in available addresses.New slave devices with a Fast- or Hs-mode I 2C-bus interface can have a 7- or a 10-bit slave address. If
possible, a 7-bit address is preferred as it is the cheapest hardware solution and results in the shortest message length. Devices with 7- and 10-bit addresses can be mixed in the same I 2C-bus system regardless of whether it is an F/S- or Hs-mode system. Both existing and future masters can generate either 7- or 10-bit addresses.12FAST -MODE
With the Fast-mode I 2C-bus specification, the protocol, format, logic levels and maximum capacitive load for the SDA and SCL lines quoted in the Standard-mode I 2C-bus specification are unchanged. New devices with an I 2C-bus interface must meet at least the minimum requirements of the Fast- or Hs-mode specification (see Section 13).Fast-mode devices can receive and transmit at up to 400kbit/s. The minimum requirement is that they can synchronize with a 400kbit/s transfer; they can then
prolong the LOW period of the SCL signal to slow down the transfer. Fast-mode devices are downward-compatible and can communicate with Standard-mode devices in a 0to 100kbit/s I 2C-bus system. As Standard-mode
devices, however, are not upward compatible, they should not be incorporated in a Fast-mode I 2C-bus system as they cannot follow the higher transfer rate and unpredictable states would occur.
The Fast-mode I2C-bus specification has the following additional features compared with the Standard-mode:?The maximum bit rate is increased to 400kbit/s.?Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted. There is no need for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate.?The inputs of Fast-mode devices incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs.
?The output buffers of Fast-mode devices incorporate slope control of the falling edges of the SDA and SCL signals.
?If the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they don’t obstruct the bus lines.
?The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to 200pF, the pull-up device for each bus line can be a resistor; for bus loads between 200pF and 400pF, the pull-up device can be a current source
(3mA max.) or a switched resistor circuit (see Fig.43).
13Hs-MODE
High-speed mode (Hs-mode) devices offer a quantum leap in I2C-bus transfer speeds. Hs-mode devices can transfer information at bit rates of up to 3.4Mbit/s, yet they remain fully downward compatible with Fast- or Standard-mode (F/S-mode) devices for bi-directional communication in a mixed-speed bus system. With the exception that arbitration and clock synchronization is not performed during the Hs-mode transfer, the same serial bus protocol and data format is maintained as with the
F/S-mode system. Depending on the application, new devices may have a Fast or Hs-mode I2C-bus interface, although Hs-mode devices are preferred as they can be designed-in to a greater number of applications.
13.1High speed transfer
To achieve a bit transfer of up to 3.4Mbit/s the following improvements have been made to the regular I2C-bus specification:
?Hs-mode master devices have an open-drain output buffer for the SDAH signal and a combination of an open-drain pull-down and current-source pull-up circuit on the SCLH output(1). This current-source circuit shortens the rise time of the SCLH signal. Only the
current-source of one master is enabled at any one time, and only during Hs-mode.
?No arbitration or clock synchronization is performed during Hs-mode transfer in multi-master systems, which speeds-up bit handling capabilities. The arbitration procedure always finishes after a preceding master code transmission in F/S-mode.
?Hs-mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2. This relieves the timing requirements for set-up and hold times.
?As an option, Hs-mode master devices can have a built-in bridge(1). During Hs-mode transfer, the high speed data (SDAH) and high-speed serial clock (SCLH) lines of Hs-mode devices are separated by this bridge from the SDA and SCL lines of F/S-mode devices. This reduces the capacitive load of the SDAH and SCLH lines resulting in faster rise and fall times.
?The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate. Hs-mode slaves have open-drain output buffers on the SCLH and SDAH outputs. Optional pull-down transistors on the SCLH pin can be used to stretch the LOW level of the SCLH signal, although this is only allowed after the acknowledge bit in Hs-mode transfers.?The inputs of Hs-mode devices incorporate spike suppression and a Schmitt trigger at the SDAH and SCLH inputs.
?The output buffers of Hs-mode devices incorporate slope control of the falling edges of the SDAH and SCLH signals.
Figure20 shows the physical I2C-bus configuration in a system with only Hs-mode devices. Pins SDA and SCL on the master devices are only used in mixed-speed bus systems and are not connected in an Hs-mode only system. In such cases, these pins can be used for other functions.
Optional series resistors R s protect the I/O stages of the I2C-bus devices from high-voltage spikes on the bus lines and minimize ringing and interference.
Pull-up resistors R p maintain the SDAH and SCLH lines at a HIGH level when the bus is free and ensure the signals are pulled up from a LOW to a HIGH level within the required rise time. For higher capacitive bus-line loads (>100pF), the resistor R p can be replaced by external current source pull-ups to meet the rise time requirements. Unless proceeded by an acknowledge bit, the rise time of the SCLH clock pulses in Hs-mode transfers is shortened by the internal current-source pull-up circuit MCS of the active master.
(1)Patent application pending.