DDR2内存引脚功能定义
《计算机维修技术第2版》
易建勋编著
清华大学出版社2009.8
附件3-6：64位DDR2SDRAM Unb-DIMM内存条引脚功能定义（240脚）
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1VREF41VSS81DQ33121VSS161NC(CB4)201VSS 2VSS42NC(CB0)*82VSS122DQ4162NC(CB5)*202DM4 3DQ043NC(CB1)*83DQS4123DQ5163VSS203NC 4DQ144VSS84DQS4124VSS164NC(DM8)*204VSS 5VSS45NC(DQS8)*85VSS125DM0165NC205DQ38 6DQS046NC(DQS8)*86DQ34126NC166VSS206DQ39 7DQS047VSS87DQ35127VSS167NC(CB6)*207VSS 8VSS48NC(CB2)*88VSS128DQ6168NC(CB7)*208DQ44 9DQ249NC(CB3)*89DQ40129DQ7169VSS209DQ45 10DQ350VSS90DQ41130VSS170VDDQ210VSS 11VSS51VDDQ91VSS131DQ12171CKE1211DM5 12DQ852CKE092DQS5132DQ13172VDD212NC 13DQ953VDD93DQS5133VSS173A15213VSS 14VSS54BA294VSS134DM1174A14214DQ46 15DQS155NC95DQ42135NC175VDDQ215DQ47 16DQS156VDDQ96DQ43136VSS176A12216VSS 17VSS57A1197VSS137CK1177A9217DQ52 18NC58A798DQ48138CK1178VDD218DQ53 19NC59VDD99DQ49139VSS179A8219VSS 20VSS60A5100VSS140DQ14180A6220CK2 21DQ1061A4101SA2141DQ15181VDDQ221CK2
22DQ1162VDDQ102NC,TEST1142VSS182A3222VSS
23VSS63A2103VSS143DQ20183A1223DM6
24DQ1664VDD104DQS6144DQ21184VDD224NC
25DQ1765VSS105DQS6145VSS185CK0225VSS
26VSS66VSS106VSS146DM2186CK0226DQ54
27DQS267VDD107DQ50147NC187VDD227DQ55
28DQS268NC108DQ51148VSS188A0228VSS
29VSS69VDD109VSS149DQ22189VDD229DQ60
30DQ1870A10/AP110DQ56150DQ23190BA1230DQ61
31DQ1971BA0111DQ57151VSS191VDDQ231VSS
32VSS72VDDQ112VSS152DQ28192RAS232DM7
33DQ2473WE113DQS7153DQ29193S0233NC
34DQ2574CAS114DQS7154VSS194VDDQ234VSS
35VSS75VDDQ115VSS155DM3195ODT0235DQ62
36DQS376S1116DQ58156NC196A13236DQ63
37DQS377ODT1117DQ59157VSS197VDD237VSS
38VSS78VDDQ118VSS158DQ30198VSS238VDDSPD 39DQ2679VSS119SDA159DQ31199DQ36239SA0
40DQ2780DQ32120SCL160VSS200DQ37240SA1
DDR2内存引脚
Front Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1VREF31DQ1961A491VSS121VSS151VSS181VDDQ211DM5/DQS14 2VSS32VSS62VDDQ92DQS5#122DQ4152DQ28182A3212NC/DQS14# 3DQ033DQ2463A293DQS5123DQ5153DQ29183A1213VSS
4DQ134DQ2564VDD94VSS124VSS154VSS184VDD214DQ46
5VSS35VSS65VSS95DQ42125DM0/DQS9155DM3/DQS12185CK0215DQ47
6DQS0#36DQS3#66VSS96DQ43126NC/DQS9#156NC/DQS12#186CK0#216VSS
7DQS037DQS367VDD97VSS127VSS157VSS187VDD217DQ52
8VSS38VSS68PAR_IN98DQ48128DQ6158DQ30188A0218DQ53
9DQ239DQ2669VDD99DQ49129DQ7159DQ31189VDD219VSS
10DQ340DQ2770A10/AP100VSS130VSS160VSS190BA1220RFU
11VSS41VSS71BA0101SA2131DQ12161CB4191VDDQ221RFU
12DQ842CB072VDDQ102NC132DQ13162CB5192RAS#222VSS
13DQ943CB173WE#103VSS133VSS163VSS193S0#223DM6/DQS15 14VSS44VSS74CAS#104DQS6#134DM1/DQS10164DM8/DQS17194VDDQ224NC/DQS15# 15DQS1#45DQS8#75VDDQ105DQS6135NC/DQS10#165NC/DQS17#195ODT0225VSS
16DQS146DQS876S1#106VSS136VSS166VSS196NC/A13226DQ54
17VSS47VSS770DT1107DQ50137RFU167CB6197VDD227DQ55
18RESET#48CB278VDDQ108DQ51138RFU168CB7198VSS228VSS
19NC49CB379VSS109VSS139VSS169VSS199DQ36229DQ60
20VSS50VSS80DQ32110DQ56140DQ14170VDDQ200DQ37230DQ61
21DQ1051VDDQ81DQ33111DQ57141DQ15171CKE1201VSS231VSS
22DQ1152CKE082VSS112VSS142VSS172VDD202DM4/DQS13232DM7/DQS16 23VSS53VDD83DQS4#113DQS7#143DQ20173NC203NC/DQS13#233NC/DQS16# 24DQ1654NC/BA284DQS4114DQS7144DQ21174NC204VSS234VSS
25DQ1755ERR_OUT85VSS115VSS145VSS175VDDQ205DQ38235DQ62
26VSS56VDDQ86DQ34116DQ58146DM2/DQS11176A12206DQ39236DQ63
27DQS2#57A1187DQ35117DQ59147NC/DQS11#177A9207VSS237VSS
28DQS258A788VSS118VSS148VSS178VDD208DQ44238VDDSPD
29VSS59VDD89DQ40119SDA149DQ22179A8209DQ45239SA0
30DQ1860A590DQ41120SCL150DQ23180A6210VSS240SA1
Note:Pin196is NC for512MB,or A13for1GB and2GB;pin54is NC for512MB and1GB,or BA2for2GB.
Pin Descriptions
Pin numbers may not correlate with symbols;refer to Pin Assignment table above for more information.
Pin Numbers Symbol Type Description
195ODT0Input On-Die Termination:ODT(registered HIGH)enables termination resistance internal to the DDR2SDRAM.
When enabled,ODT is only applied to each of the following pins:DQ,DQS,DQS#,RDQS,RDQS#,CB,
and DM.The ODT input will be ignored if disabled via the LOAD MODE command.
185,186CK0,CK0#Input Clock:CK and CK#are differential clock inputs.All address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of CK#.Output data(DQs and DQS/DQS#)is
referenced to the crossings of CK and CK#.
52CKE0Input Clock Enable:CKE(registered HIGH)activates and CKE(registered LOW)deactivates clocking circuitry on
the DDR2SDRAM.The specific circuitry that is enabled/disabled is dependent on the DDR2SDRAM
configuration and operating mode.CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations(all device banks idle),or ACTIVE POWERDOWN(row ACTIVE in any device bank).
CKE is synchronous for POWER-DOWN entry,POWER-DOWN exit,output disable,and for SELF
REFRESH entry.CKE is asynchronous for SELF REFRESH exit.Input buffers(excluding CK,CK#,CKE,
and ODT)are disabled during POWER-DOWN.Input buffers(excluding CKE)are disabled during SELF
REFRESH.CKE is an SSTL_18input but will detect a LVCMOS LOW level once VDD is applied during
first power-up.After Vref has become stable during the power on and initialization sequence,it must be
maintained for proper operation of the CKE receiver.For proper self-refresh operation VREF must be
maintained to this input.
193S0#Input Chip Select:S#enables(registered LOW)and disables(registered HIGH)the command decoder.All
commands are masked when S#is registered HIGH.S#provides for external rank selection on systems with
multiple ranks.S#is considered part of the command code.
73,74,192RAS#,CAS#,Input Command Inputs:RAS#,CAS#,and WE#(along with S#)define the command being entered.
WE#
54(2GB),71,190BA0,BA1,BA2
(2GB)Input Bank Address Inputs:BA0–BA1/BA2define to which device bank an ACTIVE,READ,WRITE,or PRECHARGE command is being applied.BA0–BA1define which mode register including MR,EMR,
EMR(2),and EMR(3)is loaded during the LOAD MODE command.
57,58,60,61,63,70,176,177,179,180, 182,183,188,196(1GB,2GB)A0–A12
(512MB)
A0–A13(1GB,
2GB)
Input Address Inputs:Provide the row address for ACTIVE commands,and the column address and auto precharge
bit(A10)for Read/Write commands,to select one location out of the memory array in the respective bank.
A10sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device
bank(A10LOW,device bank selected by BA0–BA1/BA2)or all device banks(A10HIGH).The address
inputs also provide the op-code during a LOAD MODE command.
3,4,9,10,12,13,21,22,24,25,30,31,
33,34,39,40,80,81,86,87,89,90,95,
96,98,99,107,108,110,111,116,117,
122,123,128,129,131,132,140,141,
143,144,149,150,152,153,158,159,
199,200,205,206,208,209,214,215,
217,218,226,227,229,230,235,236
DQ0–DQ63I/O Data Input/Output:Bidirectional data bus.
6,7,15,16,27,28,36,37,45,46,83,84, 92,93,104,105,113,114,126,135,147, 156,165,203,212,224,233125,134,146, 155,164,202,211,223,232DQS0–DQS8,
DQS0#–
DQS17#,
DM0–DM8
(DQS9–DQS17)
I/O Data Strobe:Output with read data,input with write data for source synchronous operation.Edge-aligned
with read data,center aligned with write data.DQS#is only used when differential data strobe mode is
enabled via the LOAD MODE command.Input Data Mask:DM is an input mask signal for write data.Input
data is masked when DM is sampled HIGH along with that input data during a WRITE access.DM is
sampled on both edges of DQS.Although DM pins are input-only,the DM loading is designed to match that
of DQ and DQS pins.If RDQS is disabled,DQS0–DQS17become DM0–DM8and DQS9#–DQS17#are not
used.
42,43,48,49,161,162,167,168CB0–CB7I/O Check Bits.
68PAR_IN Input Parity bit for the address and control bus.
55ERR_OUT Output Parity error found on the address and control bus.
120SCL Input Serial Clock for Presence-Detect:SCL is used to synchronize the presence-detect data transfer to and from
the module.
101,239,240SA0–SA2Input Presence-Detect Address Inputs:These pins are used to configure the presence-detect device.
119SDA I/O Serial Presence-Detect Data:SDA is a bidirectional pin used to transfer addresses and data into and out of the
presence-detect portion of the module.
18RESET#Input Asynchronously forces all registered outputs LOW when RESET#is LOW.This signal can be used during
power up to ensure that CKE is LOW and DQs are High-Z.
VDD Supply Power Supply:1.8V±0.1V.
53,59,64,67,69,172,178,184,187,189,
197,
51,56,62,72,75,78,170,175,181,191,
VDDQ Supply DQ Power Supply:1.8V±0.1V.
194,
1VREF Supply SSTL_18reference voltage.
VSS Supply Ground.
2,5,8,11,14,17,20,23,26,29,32,35,
38,41,44,47,50,65,66,79,82,85,88,
91,94,97,100,103,106,109,112,115,118,
121,124,127,130,133,136,139,142,
145,148,151,154,157,160,163,166,
169,198,201,204,207,210,213,216,
219,222,225,228,231,234,237
238VDDSPD Supply Serial EEPROM positive power supply:+1.7V to+3.6V.
19,54(512MB,1GB),76,77,102,171,
NC—No Connect:These pins should be left unconnected.
196(512MB),173,174,
137,138,220,221RFU—Reserved for future use.