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DAC4815BP中文资料

118+V L +V S 10V

Quad 12-Bit Digital-to-Analog Converter

(8-Bit Port Interface)

INCLUDES INTERNAL REFERENCES AND ? 1991 Burr-Brown Corporation

PDS-1112B

Printed in U.S.A. October, 1993

SBAS013

SPECIFICATIONS, Guaranteed over T

= –40°C to +85°C unless otherwise specified.

ELECTRICAL

Specifications as shown for V S = ±12V or ±15V, V L = +5V, and R L = 2k? unless otherwise noted.

DAC4815

Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated c ircuits be handled and stored using appropriate ESD protection methods.

PACKAGE INFORMATION

PACKAGE DRAWING

MODEL PACKAGE NUMBER (1)

DAC4815AP 28-Pin Plastic DIP 215DAC4815BP

28-PIn Plastic DIP

215

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

SPECIFICATIONS (CONT), Guaranteed over T A = –40°C to +85°C unless otherwise specified.

ELECTRICAL

Specifications as shown for V S = ±12V or ±15V, V L = +5V, and R L = 2k ? unless otherwise noted.

DAC4815AP

DAC4815BP

PARAMETER

CONDITIONS

MIN TYP

MAX MIN TYP

MAX UNITS TEMPERATURE RANGE Specified –40+85**°C Operating

–40

+85

°C Thermal Resistance, θJA

75*°C/W

NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes effect of voltage output DAC, voltage references.(4) Guaranteed but not tested.

PIN DESIGNATIONS

PIN DESCRIPTOR FUNCTION

1V OUT B Analog output voltage, DAC B 28A 2Address line 2 input 2V OUT A Analog output voltage, DAC A

27A 1Address line 1 input 3–V REF Out Negative reference voltage output (–10V output)26A 0Address line 0 input 4V REF In ± Reference voltage input

25D 7Data bit 7 input 5+V REF Out Positive reference voltage output (+10V output)24D 6Data bit 6 input 6BPO Bipolar offset input, DAC A, B, C, and D 23D 5Data bit 5 input 7–V S Negative analog power supply, –15V input 22D 4Data bit 4 input 8+V S Positive analog power supply, +15V input 21D 3Data bit 3 input 9AGND Analog common 20D 2Data bit 2 input 10DGND Digital common

19D 1Data bit 1 input 11+V L

Positive logic power supply, +5V input 18D 0Data bit 0 input

12V OUT D Analog output voltage, DAC D 17LE Latch data enable, DAC A, B, C, and D 13V OUT C Analog output voltage, DAC C 16CS Chip select enable, DAC A, B, C, and D 14

CLR

Asynchronous input reset to zero

Write input, DAC A, B, C, and D

A 2A 1A 0D 7D 6D 5D 4D 3D 2D 1D 0LE CS WR

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15V OUT B V OUT A –V REF Out V REF In +V REF Out

BPO –V S +V S AGND DGND +V L V OUT D V OUT C CLR

DAC4815

PIN CONFIGURATIONS

Top View

ABSOLUTE MAXIMUM RATINGS

+V L to AGND.................................................................................0V, +7V +V L to DGND ................................................................................0V, +7V +V S to AGND ..............................................................................0V, +18V –V S to AGND ...............................................................................0V,–18V AGND to DGND ................................................................................±0.3V Any digital input to GND.................................................–0.3V, +V L +0.3V Ref In to AGND ..................................................................................±25V Ref In to DGND..................................................................................±25V Storage Temperature Range ..........................................–55°C to +125°C Operating Temperature Range .........................................–40°C to +85°C Lead Temperature (soldering, 10s)................................................+300°C Junction Temperature ....................................................................+155°C Output Short Circuit ...................................Continuous to common or ±V S Reference Short Circuit..............................Continuous to common or +V S

DAC4815

CROSSTALK (Bipolar Mode)

Time (500ns/div)

V O U T

TYPICAL PERFORMANCE CURVES

T A = +25°C, V S = ±12V or ±15V, V L = +5V unless otherwise noted.

V OUT B

NOTE: Crosstalk is dominated by digital crosstalk/

feedthrough of LE signal.

V OUT A LE

+5V

PSRR vs FREQUENCY (Bipolar Mode)

70 60

50 40 30 20 10 0P S R R (d B )

10k

100k

Frequency (Hz)

NOISE vs BANDWIDTH (Bipolar Mode)

250

200

150

100

0V o l t a

g e N o i s e (μV r m s )

100

10k 100k

Frequency (Hz)

CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR

vs TEMPERATURE

1.5E+00 1.0E+00 5.0E+00 0.0E+00 –5.0E–01 –1.0E+00 –1.5E+00

? B i p o l a r O f f s e t a n d Z e r o E r r o r (m V )

–40

–20

+80

Temperature (°C)

1.5E–02 1.0E–02

5.0E–03 0.0E+00 –5.0E–03 –1.0E–02 –1.5E–02

? G a i n E r r o r (%)

100

POWER SUPPLY CURRENT vs TEMPERATURE

21.8 21.5

21.2 20.9 20.6 20.3 20 19.4

±I S (m A ) A n a l o g S u p p l y

–40

–20

Temperature (°C)

+I L (m A ) L o g i c S u p p l y

6 5

4 3 2 1 0

OUTPUT VOLTAGE SWING vs RESISTOR LOAD

Load Resistance ( )?

20 15

0V O U T (V p -p )

100

10k

DAC4815

MAJOR CARRY GLITCH

Time (1μs/div)

V O

U T (20m V /d i v )

SETTLING TIME

BIPOLAR (+10V to –10V Step)

Time (2μs/div)?V A r o u n d –10V (2m V /d i v )

SETTLING TIME BIPOLAR (–10V to +10V)

Time (1μs/div)

?V A r o u n d +10V (2m V /d i v )

DIGITAL FEEDTHROUGH

Time (500ns/div)

V O U T (5m V /d i v )

FULL-SCALE OUTPUT SWING

BIPOLAR (20V Step)

Time (2μs/div)

V O U T (5V /d i v )

TYPICAL PERFORMANCE CURVES (CONT)

T A = +25°C, V S = ±12V or ±15V, V L = +5V unless otherwise noted.

V OUT

NOTE: Data transition 800HEX to 7FF HEX .

DAC output noise due to activity on digital inputs with latch disabled.

V OUT

V OUT LE

V OUT

+10V +5V 0V

+5V 0V

+5V –10V 0V

DAC4815

FUNCTIONAL BLOCK DIAGRAM, DAC4815 — Quad 12-bit DAC, 8-bit Port

DAC4815

TIMING CHARACTERISTICS

+V L = +5V, T A = –40°C to +85°C.

NOTE: X = Don’t care.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB change in the output voltage when the input code changes by 1 LSB. A differential nonlinearity specification of ±1 LSB maximum guarantees monotonicity.BIPOLAR ZERO ERROR

The output voltage for code 800HEX .

GAIN ERROR

The deviation of the output voltage span (V MAX – V MIN )from the ideal span of 20V – 1 LSB (bipolar mode). The gain error is specified with and without the internal +10V refer-ence error included.

OUTPUT SETTLING TIME

The time required for the output voltage to settle within a percentage-of-full-scale error band for a full scale transition.Settling to ±0.012% (1/2 LSB) is specified for the DAC4815.

DISCUSSION OF SPECIFICATIONS

INPUT CODES

All digital inputs of the DAC4815 are TTL and 5V CMOS compatible. Input codes for the DAC4815 are BOB (Bipolar Offset Binary). See Figure 3 for ±10V bipolar connection.INTEGRAL OR RELATIVE LINEARITY

This term, also know as end point linearity, describes the transfer function of analog output to digital input code.Integral linearity error is the deviation of the analog output versus code transfer function from a straight line drawn through the end points.

BIPOLAR OUTPUTS FOR SELECTED INPUT

DIGITAL INPUT BIPOLAR (BOB)FFF HEX +Full Scale 800HEX Zero

7FF HEX Zero – 1 LSB 000HEX

–Full Scale

INTERFACE LOGIC TRUTH TABLE

CLR LE CS WR A 2A 1A 0FUNCTION

100000DAC A LS input register loaded with D7-D0(LSB)1100001DAC A MS input register loaded with D3(MSB)-D0*******DAC B LS input register loaded with D7-D0(LSB)1100011DAC B MS input register loaded with D3(MSB)-D0*******DAC C LS input register loaded with D7-D0(LSB)1100101DAC C MS input register loaded with D3(MSB)-D0*******DAC D LS input register loaded with D7-D0(LSB)1100111DAC D MS input register loaded with D3(MSB)-D0

1001X X X All DAC registers updated simultaneously from input registers 1000X X X All DAC registers are transparent 1X 1X X X X No data transfer 11X 1X X X No data transfer

Input registers cleared = 000HEX , DAC registers = 800HEX

DAC4815

DIGITAL-TO-ANALOG GLITCH

Ideally, the DAC output would make a clean step change in response to an input code change. In reality, glitches occur during the transition. See Typical Performance Curves. DIGITAL CROSSTALK

Digital crosstalk is the glitch impulse measured at the output of one DAC due to a full scale transition on the other DAC—see Typical Performance Curves. It is dominated by digital coupling. Also, the integrated area of the glitch pulse is specified in nV–s. See table of electrical specifications.

DIGITAL FEEDTHROUGH

Digital feedthrough is the noise at a DAC output due to activity on the digital inputs—see Typical Performance Curves.

OPERATION

Depending on the address selected, the 4 MSBs or the 8 LSBs are written into the appropriate input register for each DAC when the WR signal is brought low. The data are latched in the input register when the WR goes high. Data are then transferred from the input registers to the DAC latch DAC latch registers when LE goes high. All DACs are updated simultaneously.

When CLR is brought low, the input registers are cleared to 000HEX while the DAC registers = 800HEX. If LE is brought low after CLR the DACs are updated with 000HEX resulting in –10V (bipolar) or OV (unipolar) on the output. CIRCUIT DESCRIPTION

Each of the four DACs in the DAC4815 consists of a CMOS logic section, a CMOS DAC cell, and an output amplifier. One buried-zener +10.0V reference and a –10V reference are shared by all DACs.

Figure 1 is a simplified circuit for a DAC cell. An R, 2R ladder network is driven by a voltage reference at V REF. Current from the ladder is switched either to I OUT or AGND by 12 single-pole double-throw CMOS switches. This main-tains constant current in each leg of the ladder regardless of digital input code. This makes the resistance at V REF con-stant (it can be driven by either a voltage or current refer-ence). The reference can be either positive or negative polarity with a range of up to ±10V.

CMOS switches included in series with the ladder terminat-ing resistor and the feedback resistor, R FB, compensate for the temperature drift of the ladder switch ON resistance. The output op amps are connected as transimpedance ampli-fiers to convert the DAC-cell output current into an output voltage. They have been specially designed and compen-sated for precision and fast settling in this application.

POWER SUPPLY CONNECTIONS

The DAC4815 is specified for operation with power sup-plies of V L = +5V and V S = either ±12V or ±15V. Even with the V S supplies at ±11.4V the DACs can swing a full ±10V.

Power supply decoupling capacitors (1μF tantalum) should be located close to the DAC power supply connections.

Separate digital and analog ground pins are provided to permit separate current returns. They should be connected together at one point. Proper layout of the two current returns will prevent digital logic switching currents from degrading the analog output signal. The analog ground current is code dependent so the impedance to the system reference ground must be kept to a minimum. Connect DACs as shown in Figure 2 or use a ground plane to keep ground impedance less than 0.1? for less than 0.1LSB error.

±10V OUTPUT RANGE CONNECTION

For a ±10V bipolar output connect the DAC4815 as shown in Figure 3.

CONNECTION TO DIGITAL BUS

DAC4815s can easily be connected to a μprocessor bus.

Decode your address lines to derive the control signals shown in Figure 4. Only one LATCH signal is required for

a system where all DAC4815s are updated simultaneously.

If your want to update DAC4815s independently, use sepa-rate LATCH signals. The LATCH and WRITE signals can be brought low simultaneously to update the DAC registers with the same processor instruction that writes the final 8-bit data word the DAC input registers.

FIGURE 1. Simplified Circuit Diagram of DAC Cell.

DAC4815

FIGURE 2. Recommended Ground Connections for Multiple DAC Packages.

DAC4815

FIGURE 3. Analog Connections for ±10V DAC Output.

FIGURE 4. Logic Connections for Multiple DAC4815

Packages.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish

MSL Peak Temp (3)DAC4815AP OBSOLETE PDIP NTD 28TBD Call TI Call TI DAC4815BP

OBSOLETE

PDIP

NTD

TBD

Call TI

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/354906734.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

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30-Mar-2005

Addendum-Page 1

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