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LF13333中文资料

LF11331/LF13331/LF11332/LF13332/LF11333/LF13333/LF11201/LF13201/LF11202/LF13202Quad SPST JFET Analog Switches

General Description

These devices are a monolithic combination of bipolar and JFET technology producing the industry’s first one chip quad JFET switch.A unique circuit technique is employed to main-tain a constant resistance over the analog voltage range of ±10V.The input is designed to operate from minimum TTL levels,and switch operation also ensures a break-before-make action.

These devices operate from ±15V supplies and swing a ±10V analog signal.The JFET switches are designed for ap-plications where a dc to medium frequency analog signal needs to be controlled.

Features

n Analog signals are not loaded

n Constant “ON”resistance for signals up to ±10V and 100kHz

n Pin compatible with CMOS switches with the advantage of blow out free handling

n Small signal analog signals to 50MHz n Break-before-make action:t OFF

n High open switch isolation at 1.0MHz:?50dB n Low leakage in “OFF”state:<1.0nA n TTL,DTL,RTL compatibility

n Single disable pin opens all switches in package on LF11331,LF11332,LF11333

n LF11201is pin compatible with DG201

Test Circuit and Schematic Diagram

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FIGURE 1.Typical Circuit for One Switch

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FIGURE 2.Schematic Diagram (Normally Open)

January 1995

LF11331/LF13331/LF11332/LF13332/LF11333/LF13333/LF11201/LF13201/LF11202/LF13202Quad SPST JFET Analog Switches

?1999National Semiconductor Corporation https://www.wendangku.net/doc/356291415.html,

Absolute Maximum Ratings(Note1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

(Note2)

Supply Voltage(V CC?V EE)36V Reference Voltage V EE≤V R≤V CC Logic Input Voltage V R?4.0V≤V IN≤V R+6.0V Analog Voltage V EE≤V A≤V CC+6V;

V A≤V EE+36V Analog Current|I A|<20mA Power Dissipation(Note3)

Molded DIP(N Suffix)500mW Cavity DIP(D Suffix)900mW Operating Temperature Range

LF11201,2and LF11331,2,3?55?C to+125?C LF13201,2and LF13331,2,30?C to+70?C Storage Temperature?65?C to+150?C Soldering Information

N and D Package(10sec.)300?C SO Package:

Vapor Phase(60sec.)215?C Infrared(15sec.)220?C

Electrical Characteristics(Note4)

LF11331/2/3LF13331/2/3

Symbol Parameter Conditions LF11201/2LF13201/2Units

Min Typ Max Min Typ Max

R ON“ON”Resistance V A=0,I D=1mA T A=25?C150200150250?

200300200350?R ON Match“ON”Resistance Matching T A=25?C5201050?V A Analog Range±10±11±10±11V I S(ON)+Leakage Current in“ON”Condition Switch“ON,”V S=V D=±10V T A=25?C0.350.310nA I D(ON)3100330nA I S(OFF)Source Current in“OFF”Condition Switch“OFF,”V S=+10V,T A=25?C0.450.410nA

V D=?10V3100330nA I D(OFF)Drain Current in“OFF”Condition Switch“OFF,”V S=+10V,T A=25?C0.150.110nA

V D=?10V3100330nA V INH Logical“1”Input Voltage 2.0 2.0V V INL Logical“0”Input Voltage0.80.8V

I INH Logical“1”Input Current V IN=5V T A=25?C 3.610

253.640

100μA

I INL Logical“0”Input Current V IN=0.8T A=25?C0.10.1μA

11μA t ON Delay Time“ON”V S=±10V,(Figure3)T A=25?C500500ns t OFF Delay Time“OFF”V S=±10V,(Figure3)T A=25?C9090ns t ON?t OFF Break-Before-Make V S=±10V,(Figure3)T A=25?C8080ns C S(OFF)Source Capacitance Switch“OFF,”V S=±10V T A=25?C 4.0 4.0pF C D(OFF)Drain Capacitance Switch“OFF,”V D=±10V T A=25?C 3.0 3.0pF C S(ON)+Active Source and Drain Capacitance Switch“ON,”V S=V D=0V T A=25?C 5.0 5.0pF C D(ON)

I SO(OFF)“OFF”Isolation(Figure4),(Note5)T A=25?C?50?50dB CT Crosstalk(Figure4),(Note5)T A=25?C?65?65dB SR Analog Slew Rate(Note6)T A=25?C5050V/μs

I DIS Disable Current(Figure5),(Note7)T A=25?C0.4 1.00.6 1.5mA

0.6 1.50.9 2.3mA

I EE Negative Supply Current All Switches“OFF,”V S=±10V T A=25?C 3.0 5.0 4.37.0mA

4.27.5 6.010.5mA

I R Reference Supply Current All Switches“OFF,”V S=±10V T A=25?C 2.0 4.0 2.7 5.0mA

2.8 6.0

3.87.5mA

I CC Positive Supply Current All Switches“OFF,”V S=±10V T A=25?C 4.5 6.07.09.0mA

6.39.09.813.5mA

Note1:“Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.

Note2:Refer to RETSF11201X,RETSF11331X,RETSF11332X and RETSF11333X for military specifications.

Note3:For operating at high temperature the molded DIP products must be derated based on a+100?C maximum junction temperature and a thermal resistance of+150?C/W,devices in the cavity DIP are based on a+150?C maximum junction temperature and are derated at±100?C/W.

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Electrical Characteristics(Note4)(Continued)

Note4:Unless otherwise specified,V CC=+15V,V EE=?15V,V R=0V,and limits apply for?55?C≤T A≤+125?C for the LF11331/2/3and the LF11201/2,?25?C≤T A≤+85?C for the LF13331/2/3and the LF13201/2.

Note5:These parameters are limited by the pin to pin capacitance of the package.

Note6:This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.

Note7:All switches in the device are turned“OFF”by saturating a transistor at the disable node as shown in Figure5.The delay time will be approximately equal to the t ON or t OFF plus the delay introduced by the external transistor.

Note8:This graph indicates the analog current at which1%of the analog current is lost when the drain is positive with respect to the source.

Note9:θJA(Typical)Thermal Resistance

Molded DIP(N)85?C/W

Cavity DIP(D)100?C/W

Small Outline(M)105?C/W

Connection Diagrams(Top View for SO and Dual-In-Line Packages)(All Switches Shown are For Logical“0”)

LF11331/LF13331

DS005667-1LF11332/LF13332

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LF11333/LF13333

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LF11201/LF13201

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Connection Diagrams(Top View for SO and Dual-In-Line Packages)(All Switches Shown are For Logical “0”)(Continued)

LF11202/LF13202

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Order Number LF13201D,LF11201D,LF11201D/883,LF13202D,LF11202D,LF11202D/883,LF13331D,LF11331D, LF11331D/883,LF13332D,LF11332D,LF11332D/883,LF13333D,LF11333D or LH11333D/883

See NS Package Number D16C

Order Number LF13201M,LF13202M,LF13331M,LF13332M or LF13333M

See NS Package Number M16A

Order Number LF13201N,LF13202N,LF13331N,LF13332N or LF13333N

See NS Package Number N16A

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Test Circuit and Typical Performance Curves

Delay Time,Rise Time,Settling Time,and

Switching Transients

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DS005667-19DS005667-20

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Additional Test Circuits

Typical Performance Characteristics

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FIGURE 3.t ON ,t OFF Test Circuit and Waveforms for a Normally Open Switch

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FIGURE 4.“OFF”Isolation,Crosstalk,Small Signal Response

“ON”Resistance

DS005667-23“ON”Resistance

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“ON”Resistance

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Typical Performance Characteristics(Continued)

Break-Before-Make Action

DS005667-26Switching Times

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Crosstalk and“OFF”

Isolation vs Frequency

Using Test Circuit of

Figure5

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Supply Current

DS005667-29Supply Current

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Supply Current

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Switch Leakage Currents

DS005667-32Switch Leakage Current

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Switch Capacitances

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Typical Performance Characteristics

(Continued)

Application Hints

GENERAL INFORMATION

These devices are monolithic quad JFET analog switches with “ON”resistances which are essentially independent of analog voltage or analog current.The leakage currents are typically less than 1nA at 25?C in both the “OFF”and “ON”switch states and introduce negligible errors in most applica-tions.Each switch is controlled by minimum TTL logic levels at its input and is designed to turn “OFF”faster than it will turn “ON.”This prevents two analog sources from being tran-siently connected together during switching.The switches were designed for applications which require break-before-make action,no analog current loss,medium speed switching times and moderate analog currents.

Because these analog switches are JFET rather than CMOS,they do not require special handling.

LOGIC INPUTS

The logic input (IN),of each switch,is referenced to two for-ward diode drops (1.4V at 25?C)from the reference supply (V R )which makes it compatible with DTL,RTL,and TTL logic families.For normal operation,the logic “0”voltage can range from 0.8V to ?4.0V with respect to V R and the logic “1”voltage can range from 2.0V to 6.0V with respect to V R ,pro-vided V IN is not greater than (V CC ?2.5V).If the input voltage is greater than (V CC ?2.5V),the input current will increase.If

the input voltage exceeds 6.0V or ?4.0V with respect to V R ,a resistor in series with the input should be used to limit the input current to less than 100μA.ANALOG VOLTAGE AND CURRENT

Analog Voltage

Each switch has a constant “ON”resistance (R ON )for analog voltages from (V EE +5V)to (V CC ?5V).For analog voltages greater than (V CC ?5V),the switch will remain ON indepen-dent of the logic input voltage.For analog voltages less than (V EE +5V),the ON resistance of the switch will increase.Al-though the switch will not operate normally when the analog voltage is out of the previously mentioned range,the source voltage can go to either (V EE +36V)or (V CC +6V),whichever is more positive,and can go as negative as V EE without de-struction.The drain (D)voltage can also go to either (V EE +36V)or (V CC +6V),whichever is more positive,and can go as negative as (V CC ?36V)without destruction.

Analog Current

With the source (S)positive with respect to the drain (D),the R ON is constant for low analog currents,but will increase at higher currents (>5mA)when the FET enters the saturation region.However,if the drain is positive with respect to the source and a small analog current loss at high analog cur-rents (Note 6)is tolerable,a low R ON can be maintained for analog currents greater than 5mA at 25?C.

Slew Rate of Analog Voltage Above Which Signal Loading Occurs

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Small Signal Response

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Maximum Accurate Analog Current vs Temperature

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Logical “1”Input Bias Current

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Application Hints(Continued)

LEAKAGE CURRENTS

The drain and source leakage currents,in both the ON and the OFF states of each switch,are typically less than1nA at 25?C and less than100nA at125?C.As shown in the typical curves,these leakage currents are Dependent on power supply voltages,analog voltage,analog current and the source to drain voltage.

DELAY TIMES

The delay time OFF(t OFF)is essentially independent of both the analog voltage and temperature.The delay time ON (t ON)will decrease as either(V CC?V A)decreases or the tem-perature decreases.

POWER SUPPLIES

The voltage between the positive supply(V CC)and either the negative supply(V EE)or the reference supply(V R)can be as much as36V.To accommodate variations in input logic refer-ence voltages,V R can range from V EE to(V CC?4.5V).Care should be taken to ensure that the power supply leads for the device never become reversed in polarity or that the device is never inadvertently installed backwards in a test socket.If one of these conditions occurs,the supplies would zener an internal diode to an unlimited current;and result in a de-stroyed device.

SWITCHING TRANSIENTS

When a switch is turned OFF or ON,transients will appear at the load due to the internal transient voltage at the gate of the switch JFET being coupled to the drain and source by the junction capacitances of the JFET.The magnitude of these transients is dependent on the load.A lower value R L produces a lower transient voltage.A negative transient oc-curs during the delay time ON,while a positive transient oc-curs during the delay time OFF.These transients are rela-tively small when compared to faster switch families. DISABLE NODE

This node can be used,as shown in Figure5,to turn all the switches in the unit off independent of logic inputs.Normally, the node floats freely at an internal diode drop(≈0.7V)above V R.When the external transistor in Figure5is saturated,the node is pulled very close to V R and the unit is disabled.Typi-cally,the current from the node will be less than1mA.This feature is not available on the LF11201or LF11202series.

Typical Applications

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FIGURE5.Disable Function

Sample and Hold with Reset

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