vhdl的电子秒表设计
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////// // Company:
// Engineer:
//
// Create Date: 23:23:56 11/10/2013
// Design Name:
// Module Name: miaobiao
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module miaobiao(CLK_50M,SP,CLR,CLK_1K,EN,LED,OUTBCD, SEG );
input CLK_50M;
input SP;
input CLR;
output CLK_1K;
output EN;
output [6:0] LED;
output [3:0] OUTBCD;
output [7:0] SEG;
wire CLK_1K;
wire EN;
wire[6:0] LED;
wire[3:0] OUTBCD;
wire[7:0] SEG;
wire[3:0]MS10;
wire[3:0]MS100;
wire[3:0]S1;
wire[3:0]S10;
CTRL U0(CLR,CLK_50M,SP,EN);
CB50000 U1(CLK_50M,CLK_1K);
COUNT U2(CLK_1K,CLR,EN,MS10,MS100,S1,S10);
MULX U3(CLR,CLK_50M,EN,MS10,MS100,S1,S10,OUTBCD,SEG);
BCD7 U4(OUTBCD,LED);
endmodule
//分频模块，将50Mhz时钟分频成1khz；module CB50000(CLK_50M,CLK_1K);
input CLK_50M;
output CLK_1K;
reg CLK_1K;
reg count;
always@(posedge CLK_50M)
begin
if(count==49999)
begin
count<=0;
CLK_1K<=~CLK_1K;
end
else
count<=count+1'b1;
end
endmodule
//控制模块
module CTRL(CLR,CLK_50M,SP,EN);
input CLR;
input CLK_50M;
input SP;
output EN;
reg EN;
parameter S0=1'b0;
parameter S1=1'b1;
reg CURRENT_STATE;
reg NEXT_STATE;
always@(SP or CURRENT_STATE)
begin
case(CURRENT_STATE)
S0: begin
EN<=1'b1;
if(SP==1'b1)
NEXT_STATE<=S1;
else
NEXT_STATE<=S0;
end
S1: begin
EN<=1'b0;
if(SP==1'b1)
NEXT_STATE<=S1;
else
NEXT_STATE<=S0;
end
endcase
end
always@(CLK_50M)
begin
if(CLR==1'b1)
CURRENT_STATE<=S0;
else if(CLK_50M==1'b1)
CURRENT_STATE<=NEXT_STATE;
end
endmodule
//十进制计数器模块
module CDU10(CLK_1K,CLR,EN,CN,COUNT10);
input CLK_1K;
input CLR;
input EN;
output CN;
reg CN;
output[3:0]COUNT10;
wire[3:0]COUNT10;
reg[3:0]SCOUNT10;
assign COUNT10=SCOUNT10;
always@(posedge CLK_1K or posedge CLR or posedge EN) begin
if(CLR==1'b1)
begin
SCOUNT10<=4'b0000;
CN<=1'b0;
end
else
begin
if(EN==1'b1)
begin
if(SCOUNT10==4'b1001)
begin
CN<=1'b1;
SCOUNT10<=4'b0000;
end
else
begin
CN<=1'b0;
SCOUNT10<=SCOUNT10+1'b1;
end
end
end
end
endmodule
//六进制计数器模块
module CDU6(CLK_1K,CLR,EN,CN,COUNT6);
input CLK_1K;
input CLR;
input EN;
output CN;
reg CN;
output[3:0]COUNT6;
wire[3:0]COUNT6;
reg[3:0]SCOUNT6;
assign COUNT6=SCOUNT6;
always@(posedge CLK_1K or posedge CLR or posedge EN) begin
if(CLR==1'b1)
begin
SCOUNT6<=4'b0000;
CN<=1'b0;
end
else
begin
if(EN==1'b1)
begin
if(SCOUNT6==4'b0101)
begin
CN<=1'b1;
SCOUNT6<=4'b0000;
end
else
begin
CN<=1'b0;
SCOUNT6<=SCOUNT6+1'b1;
end
end
end
end
endmodule
//整体计数器模块，10ms，100ms，1s，10s部分
module COUNT(CLK_1K,CLR,EN,S_10MS,S_100MS,S_1S,S_10S);
input CLK_1K;
input CLR;
input EN;
output[3:0]S_10MS;
wire[3:0]S_1OMS;
output[3:0]S_100MS;
wire[3:0]S_1O0MS;
output[3:0]S_1S;
wire[3:0]S_1S;
output[3:0]S_10S;
wire[3:0]S_1OS;
wire A;
wire B;
wire C;
wire D;
CDU10 U1(CLK_1K,CLR,EN,A,S_10MS);
CDU10 U2(A,CLR,EN,B,S_100MS);
CDU10 U3(B,CLR,EN,C,S_1S);
CDU6 U4(C,CLR,EN,D,S_10S);
endmodule
//显示模块
module MULX(CLK_50M,CLR,EN,S_10MS,S_100MS,S_1S,S_10S,OUTBCD,SEG);
input CLK_50M;
input CLR;
input EN;
input[3:0]S_10MS;
input[3:0]S_100MS;
input[3:0]S_1S;
input[3:0]S_10S;
output[3:0]OUTBCD;
reg[3:0]OUTBCD;
output[7:0]SEG;
reg[7:0]SEG;
reg[3:0]COUNT;
always@(posedge CLK_50M)
begin
if(CLR==1'b1)
COUNT<=4'b1111;
else
begin
if(EN==1'b1)
COUNT<=4'b0000;
else
COUNT<=COUNT+1'b1;
end
end
always@(CLK_50M)
begin
if(CLK_50M==1'b1)
begin
case(COUNT)
4'b0000:
begin
OUTBCD<=S_10MS;
SEG<=8'b11111110;
end
4'b0001:
begin
OUTBCD<=S_100MS;
SEG<=8'b11111101;
end
4'b0010:
begin
OUTBCD<=S_1S;
SEG<=8'b11111011;
end
4'b0011:
begin
OUTBCD<=S_10S;
SEG<=8'b11110111;
end
4'b0100:
begin
OUTBCD<=S_10MS;
SEG<=8'b11111110;
end
4'b0101:
begin
OUTBCD<=S_100MS;
SEG<=8'b11111101;
end
4'b0110:
begin
OUTBCD<=S_1S;
SEG<=8'b11111011;
end
4'b0111:
begin
OUTBCD<=S_10S;
SEG<=8'b11110111;
end
default:
begin
OUTBCD<=4'b0000;
SEG<=8'b00000000;
end
endcase
end
end
endmodule
//BCD七段译码器驱动器模块
module BCD7(BCD,LED);
input[3:0] BCD;
output[6:0] LED;
wire[6:0] LED;
assign
LED=(BCD==4'b0000)?7'b1111110:(BCD==4'b0001)?7'b0110000:(BCD==4'b0010)?7'b1101101:(B CD==4'b0011)?
7'b1111001:(BCD==4'b0100)?7'b0110011:(BCD==4'b0101)?7'b1011011:(BCD==4'b0110)?
7'b1011111:(BCD==4'b0111)?7'b1110000:(BCD==4'b1000)?7'b1111111:(BCD==4'b1001)?7' b1111011:7'b0000000;
endmodule