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GS864018T-300I中文资料

GS864018/32/36T-300/250/200/167

4M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs 300 MHz –167 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O

100-Pin TQFP Commercial Temp Industrial Temp Features

? FT pin for user-configurable flow through or pipeline operation

? Single Cycle Deselect (SCD) operation

? 2.5 V or 3.3 V +10%/–10% core power supply ? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins ? Default to Interleaved Pipeline mode

? Byte Write (BW) and/or Global Write (GW) operation ? Internal self-timed write cycle

? Automatic power-down for portable applications ? JEDEC-standard 100-lead TQFP package ? Pb-Free 100-lead TQFP package available

Functional Description

Applications

The GS864018/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS864018/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-300-250-200-167Unit Pipeline 3-1-1-1

KQ tCycle 3.3 4.0 5.0 6.0ns (x18)Curr (x32/x36)

480410350305mA Flow Through 2-1-1-1

t KQ tCycle 5.55.5 6.56.57.57.58.08.0ns ns Curr (x18)Curr (x32/x36)

285330

245280

220250

210240

mA mA

807978777675747372

7170

69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP B

V SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1

A 0

A A V S S

V D D

A A A A A A A A

A A E 1

E 2 N C N C B B

B A

E 3

C K G W B W V

D D

V S S

G A D S C A D S P A D V A A

A 4M x 18Top View DQP A A NC NC NC NC NC NC NC NC

NC NC NC NC NC NC NC

NC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950

FT GS864018/32/36T-300/250/200/167

GS864018 100-Pin TQFP Pinout (Package T)

807978777675747372

7170

69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1

A 0

A A V S S

V D D

A A A A A A A A

A A E 1

E 2 B D

B C

B B

B A

E 3

C K G W B W V

D D

V S S

G A D S C A D S P A D V A A

A 2M x 32Top View DQ

B N

C DQ B DQ B DQ B DQ A DQ A DQ A DQ A NC

DQ C DQ C DQ C DQ D DQ D DQ D NC

DQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950

FT GS864018/32/36T-300/250/200/167

GS864032 100-Pin TQFP Pinout (Package T)

807978777675747372

7170

69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C3V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1

A 0

A A V S S

V D D

A A A A A A A A

A A E 1

E 2 B D

B C

B B

B A

E 3

C K G W B W V

D D

V S S

G A D S C A D S P A D V A A

A 2M x 36Top View DQ

B DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP A

DQ C DQ C DQ C DQ D DQ D DQ D DQP D

DQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950

FT GS864018/32/36T-300/250/200/167

GS864036 100-Pin TQFP Pinout (Package T)

TQFP Pin Description

Symbol

Type

Description

A 0, A 1I Address field LSBs and Address Counter preset Inputs

A I Address Inputs DQ A DQ

B DQ

C DQ

D I/O

Data Input and Output pins

NC No Connect

BW I Byte Write —Writes all enabled bytes; active low B A , B B I Byte Write Enable for DQ A , DQ B Data I/Os; active low B C , B D I Byte Write Enable for DQ C , DQ D Data I/Os; active low

CK I Clock Input Signal; active high

GW I Global Write Enable —Writes all bytes; active low

E 1, E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low

ADV I Burst address counter advance enable; active low ADSP, ADSC

I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low

V DD I Core power supply V SS I I/O and Core Ground V DDQ

Output driver power supply

GS864018/32/36T-300/250/200/167

A0A1

D1Q1Q0

Counter Load

D Q

R e g i s t e r

A0–An

LBO ADV CK ADSC ADSP GW BW E 1G

Power Down Control

Memory Array

E 2E 3

DQx1–DQx9

Note: Only x36 version shown for simplicity.

B A

B B

B C

B D

FT GS864018/32/36 Block Diagram

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance Control

ZQ L High Drive (Low Impedance)H or NC Low Drive (High Impedance)9th Bit Enable

L or NC Activate DQPx I/Os (x18/x3672 mode)H

Deactivate DQPx I/Os (x16/x3272 mode)

GS864018/32/36T-300/250/200/167

Note:

There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Note:

The burst counter wraps to initial state on the 5th clock.Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st address 000110112nd address 011011003rd address 101100014th address

Interleaved Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st address 000110112nd address 010011103rd address 101100014th address

Burst Counter Sequences

BPR 1999.05.18

GS864018/32/36T-300/250/200/167

Byte Write Truth Table

Function

B A

B B

B C

B D

Notes

Read H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes

2, 3, 4

Write all bytes L X X X X X

1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.

3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4.Bytes “C ” and “D ” are only available on the x32 and x36 versions.

Synchronous Truth Table

Operation

Address Used

State Diagram Key 5

E 1

E 2

ADSP ADSC

ADV

W 3

DQ 4

Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW

H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst Current H X X H H T D 1.X = Don’t Care, H = High, L = Low

2. E = T (True) if E 2 = 1 and E 3 = 0; E = F (False) if E 2 = 0 or E 3 = 1

3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS864018/32/36T-300/250/200/167

First Write

First Read

Burst Write

Burst Read

Deselect R W

X S i m p l e S y n c h r o n o u s O p e r a t i o n

S i m p l e B u r s t S y n c h r o n o u s O p e r a t i o n

CR R

Notes:

1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

GS864018/32/36T-300/250/200/167

Simplified State Diagram

First Write

First Read

Burst Write

Burst Read

Deselect

R W

X CR

R CW CR

W CW

Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

https://www.wendangku.net/doc/3b13818101.html,e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS864018/32/36T-300/250/200/167

Simplified State Diagram with G

GS864018/32/36T-300/250/200/167

Absolute Maximum Ratings

(All voltages reference to V SS )

Symbol

Description

Value

Unit

V DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6

V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)

V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5W

T STG Storage Temperature –55 to 125o C T BIAS

Temperature Under Bias

–55 to 125

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply Voltage

V DDQ2

2.3

2.5

2.7

Notes:

1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

GS864018/32/36T-300/250/200/167

V DDQ3 Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V DD Input High Voltage V IH 2.0—V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.8V 1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage

V ILQ

–0.3

—

0.8

1,3

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.

V DDQ2 Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage

V ILQ

–0.3

—

0.3*V DD

1,3

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)

T A

–40

°C

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

GS864018/32/36T-300/250/200/167

20% tKC

V SS – 2.0 V

50%V SS V IH

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

V DD + 2.0 V

50%V DD

V IL

Capacitance

o C, f = 1 MH Z , V DD Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/O

V OUT = 0 V

Note:

These parameters are sample tested.AC Test Conditions

Parameter

Conditions

Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DDQ /2Output reference level

V DDQ /2Output load

Fig. 1

Notes:

1.Include scope and jig capacitance.

2.Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3.Device is deselected as defined by the Truth Table.

V DDQ/2

50?30pF *

Output Load 1

* Distributed Test Jig Capacitance

(T A = 25= 2.5 V)

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA ZZInput Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FTInput Current

I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL

–100 uA –1 uA 1 uA 1 uA Output Leakage Current (x36/x72)I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output Leakage Current (x18)

I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V

2.4 V —Output Low Voltage

V OL

I OL = 8 mA

—

0.4 V

GS864018/32/36T-300/250/200/167

Operating Currents

Parameter

Test Conditions

Mode

Symbol

-300

-250-200-167Unit

0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating Current

Device Selected; All other inputs ≥V IH o r ≤ V IL Output open

(x32/x36)

Pipeline I DD I DDQ 4206044060360503805031040330402703529035mA Flow Through I DD I DDQ 3003032030255252752523020250202202024020mA (x18)

Pipeline

I DD I DDQ 3703039030315253352527020290202402026020mA Flow Through I DD I DDQ 2701529015230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —

Pipeline

I SB 100120100120100120100120mA Flow Through I SB 100120100120100120100120mA Deselect Current

Device Deselected; All other inputs ≥ V IH or ≤ V IL

—

Pipeline I DD 150165140155130146125140mA Flow Through

I DD

135

150

125

140

120

135

120

135

GS864018/32/36T-300/250/200/167

Notes:

1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.

2.All parameters listed are worst case scenario.

AC Electrical Characteristics

Parameter Symbol -300-250-200-167Unit Min Max Min

Max Min

Max Pipeline

Clock Cycle Time tKC 3.3— 4.0— 5.0— 6.0—ns Clock to Output Valid

tKQ — 2.3— 2.5— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z

tLZ 1 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.1— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.2—0.4—0.5—ns Flow Through

Clock Cycle Time tKC 5.5— 6.5—7.5—8.0—ns Clock to Output Valid

tKQ — 5.5— 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z

tLZ 1 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.2— 1.5— 1.5— 1.5—ns Clock to Output in

High-Z tHZ 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.3— 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—ns ZZ hold time tZZH 21—1—1—1—ns ZZ recovery

tZZR

—

20—

GS864018/32/36T-300/250/200/167

Notes:

1.These parameters are sampled and are not 100% tested.

2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS864018/32/36T-300/250/200/167

Pipeline Mode Timing (SCD)

Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3Cont

Deselect

tHZ

tKQX tKQ

tLZ

tOHZ

tOE

Burst Read

tKC

tKL tKH Single Write Single Read

Q(A)

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Deselected with E1

E1 masks ADSP

E2 and E3 only sampled with ADSP and ADSC

ADSC initiated read

CK ADSP

ADSC

ADV

A0–An

Ba–Bd

E3G

DQa–DQd

GS864018/32/36T-300/250/200/167

Flow Through Mode Timing (SCD)

Begin Read A Cont

Cont Write B Read C Read C+1Read C+2Read C+3Read C Cont Deselect

tHZ

tKQX

tKQ tLZ

tH tS

tOHZ

tOE

tS tH

tS tH tS tH

tS tKC

tKL tKH

Q(A)

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

E2 and E3 only sampled with ADSC

ADSC initiated read

Deselected with E1

Fixed High

CK ADSP

ADSC

ADV

A0–An

Ba–Bd

E3G

DQa–DQd

GS864018/32/36T-300/250/200/167

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tZZR

tZZH

tZZS

Hold

Setup tKL

tKH

tKC

ADSP ADSC