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SX6530 datasheet v0.4

SX6530
FM Stereo Transmitter IC
1 General Description
The SX6530 FM stereo transmitter employs a digital stereo encoder and a fully integrated PLL modulator, exhibits low cost and low power with high performance, and it needs very few external components. The SX6530 has 20 pins, and supports both the whole 76~ 125 MHz band with a 3-wire SPI interface or a 2-wire I2C interface, or side band channel programming directly through a 4-wire parallel control interface. The SX6530 is available in a 3x3 mm 20-pin QFN package.
2 Features
? ? ? ? ? ? ? ? FM transmitter with wholly integrated PLL, stereo encoder and pre-emphasis filter Support 76~125 MHz band with a 3wire SPI or a 2-wire I2C interface Support 87.7 – 88.9 MHz and 106.7 – 107.9 MHz with 4-wire parallel control interface 7.6 MHz crystal 50us/75us pre-emphasis 2.5 ~ 5 V supply voltage Active current 14 mA 3x3 mm 20-pin QFN package
3 Chip Block Diagram
Figure 1 Chip Block Diagram
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SX6530
4 Pin Assignment
MODE 17 SEL XO 16 15 RST 14 XI SX6530 13 PWD 12 POUT 11 GND5VD 6 SCK 7 CSN 8 VDD5VA 9 GND5VA 10 VDD5VD D1 20 D2 LCH D3 RCH MOSI 1 2 3 4 5 D0 19
18
Figure 2 Pin assignment for QFN20 package (top view)
Table 1 pin assignment
Package Pin # 1 2 3 4 5 6 7 8 9
Name D2 LCH D3 RCH MOSI SCK CSN VDD5VA GND5VA
Type I I I I IO I I P G
Description Channel selection bit Left channel input Channel selection bit Right channel input SPI data input or I2C data IO, selected by MODE pin SPI clock input or I2C clock input, selected by MODE pin SPI enable Power for analog Ground for analog
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SX6530
10 11 12 13 14 15 16 17 18 19 20
VDD5VD GND5VD POUT PWD XI RST XO MODE SEL D0 D1
P G RF I I I O I I I I
Power for digital Ground for digital RF output Power down enable Crystal input Reset, active low Crystal output I2C or SPI interface selection Pre-emphasis time constant selection Channel selection bit Channel selection bit
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SX6530
5 Functional Description
5.1 Power supply
The SX6530 integrated a regulator which supplies power to the chip. The external supply voltage range is 2.5- 5 V.
5.4 Stereo encoder
The stereo encoder is based on signal processing to encode analog stereo audio input signal and generate a composite FM signal with MAIN, SUB and pilot signal from a 7.6 MHz oscillator.
5.2 Power down and reset
Set the RST pin to low will reset the SX6530 chip to initial state. Set the PWD pin to high will power down the S X6530 chip.
5.5 Channel number
The SX6530 can select different channel frequency through setting the high level or low level of the channel selection pins.
5.3 Pre-emphasis
Pre-emphasis time constant: 50us/75us, it can be selected through SEL pin (0: 50 us, 1: 75 us).
Table 2 [D3, D2, D1, D0] mapping to channel frequency
Channel selection bits 0 1 2 3 4 5 6 7
Channel Frequency (MHz) 87.7 87.9 88.1 88.3 88.5 88.7 88.9 From register
Channel selection bits 8 9 10 11 12 13 14 15
Channel Frequency (MHz) 106.7 106.9 107.1 107.3 107.5 107.7 107.9 From register
5.6 FM modulator
The FM transmitter uses direct frequency synthesis to radiate FM wave to the air by modulating the carrier signal with the composite signal.
5.7 Reference clock
The SX6530 accepts a 7.6 MHz reference clock to the XI, XO pins.
6 Programming interface
The SX6530 supports both 2-wire I2C (MODE=0) and 3-wire SPI (MODE=1) programming interface. The device ID of
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SX6530
SX6530 is 0x1D. Interface clock rate can be up to 20 MHz.
MOSI, SCK and CSN should be given low at power down state to save power.
Command
Data[Addr]
Data[Addr+1]
Data[Addr+N]
0.5TCLK
MOSI SCK
Addr[6:0] + R/W
D[15], D[14],
, D[0]
D[15:0]
D[15:0]
CSN
0.5TCLK
0.5TCLK
Figure 3 3-wire control interface timing diagram
Figure 4 2-wire control interface timing diagram
Table 3 Register mapping [Note 1]
Address （DEC） 00 01
Bit 15:0 15:0
R/W W/R W/R
Name FH FL
Default Value 0x02e2 0x86bd
Function MSB 16 bits of frequency setting LSB 16 bits of frequency setting Frequency = {FH, FL}*3.8/2^21 Default frequency is 87.7 MHz
02 15:4 3:0
W/R 0 POUT 7 Reserved Output power 0: -16 dBm, 1: -10 dBm 3: -5 dBm, 7: -2 dBm
03 15:13
W/R GAIN 1 Digital Gain 1 to 1.875, step 0.125
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SX6530
12
BYP_EM
0
Bypass pre-emphasis filter 0: Enable filter 1: Bypass filter
11 10 MONO
0 0
Reserved Mono and stereo selection 0: Stereo 1: Mono
9:4
AUD_DEV
2E (75 kHz) [Note 2] 3 (7.5 kHz)
Audio deviation adjust
3:0 Note:
PILOT_DEV
Pilot deviation adjust
1. Don’t write or read any register not listed in table above such as register with address greater than 3 2. -10 dBuV single channel audio input, with default digital gain
7 Design Specification
7.1 Recommended Operating Conditions
Table 4 Recommended Operating Conditions
Parameter Analog Supply Voltage Digital Supply Voltage Supply Current Audio input level Ambient Temperature
1
Symbol Min Typ Max Unit VA VD VIO IA VIN-A Tamb 2.5 2.5 2 20 -40 15 27 3.3 3.3 5 5 3.2 -10 15k 85 V V V mA dBV Hz ℃
Interface Voltage Range
Audio input frequency range fIN-A
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SX6530
7.2 DC Electrical Specification
Table 5 Absolute Maximum Ratings
Parameter Input Voltage
Symbol Min Typ Max Unit VIN -55 7 125 V ℃
Ambient Temperature Tamb
7.3 Transmitter Characteristics
Table 6 Transmitter Characteristics
Parameter Frequency range Output power 1 Pre-emphasis time constant Audio SINAD Stereo separation L/R channel balance Notes: 1: 50 ohm loading
Test Condition
Min 76 -16 -
50us, 75us Mono 22.5 kHz Deviation
Typ 50,75 61 36 +/- 0.5
Max Unit 125 MHz -2 dBm us dB dB dB
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SX6530
9 Final Package information
SX6530 uses the QFN 20-pin 3x3 mm package, with matt tin plating.
Figure 5 QFN 3x3 mm 20 Pin Package diagram
Table 7 QFN 3x3 mm 20 Pin Package dimensions
Parameter A A1 A3 D E b L D2 E2 e
Min 0.70 0.00 2.95 2.95 0.15 0.30 1.35 1.35
Typ 0.75 0.20 REF 3.00 3.00 0.20 0.40 1.50 1.50 0.40 REF
Max 0.80 0.05 3.05 3.05 0.25 0.50 1.60 1.60
Unit mm mm mm mm mm mm mm mm mm mm
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