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721055EGM1G07TB中文资料

Pin Assignment

Pin#Front Side Pin#

Back Side Pin#Front Side Pin#Back Side 1Vss 85Vss 43Vss 127Vss 2DQ086DQ3244OE2*128NC 3DQ187DQ3345RAS2*129NC 4DQ288DQ3446CAS2*130CAS6*5DQ389DQ3547CAS3*131CAS7*6Vcc 90Vcc 48WE2*132NC 7DQ491DQ3649Vcc 133Vcc 8DQ592DQ3750NC 134NC 9DQ693DQ3851NC 135NC 10DQ794DQ3952CB2136CB611DQ895DQ4053CB3137CB712Vss 96Vss 54Vss 138Vss 13DQ997DQ4155DQ16139DQ4814DQ1098DQ4256DQ17140DQ4915DQ1199DQ4357DQ18141DQ5016DQ12100DQ4458DQ19142DQ5117DQ13101DQ4559Vcc 143Vcc 18Vcc 102Vcc 60DQ20144DQ5219DQ14103DQ4661NC 145NC 20DQ15104DQ4762NC 146NC 21CB0105CB463NC 147NC 22CB1106CB564Vss 148Vss 23Vss 107Vss 65DQ21149DQ5324NC 108NC 66DQ22150DQ5425NC 109NC 67DQ23151DQ5526Vcc 110Vcc 68Vss 152Vss 27WE0*111NC 69DQ24153DQ5628CAS0*112CAS4*70DQ25154DQ5729CAS1*113CAS5*71DQ26155DQ5830RAS0*114NC 72DQ27156DQ5931OE0*115NC 73Vcc 157Vcc 32Vss 116Vss 74DQ28158DQ6033A0117A175DQ29159DQ6134A2118A376DQ30160DQ6235A4119A577DQ31161DQ6336A6120A778Vss 162Vss 37

A8121A979NC 163NC 38A10122NC 80NC 164NC 39NC 123NC 81NC 165SA040Vcc 124Vcc 82SDA 166SA141Vcc 125NC 83SCL 167SA242

126

Vcc

168

Vcc

* Active Low

Extended Data Out (EDO) DRAM DIMM

72105sEGM1G07TB 168 Pin 1Mx72 EDO DIMM Unbuffered, 1k Refresh, 3.3V with SPD Features

? JEDEC-Standard 168-pin Dual Inline Memory

Module (DIMM)? Unbuffered

? Supports Extended Data-out (EDO) access cycles ? Based on 1Mx16 and 1Mx4 DRAM ? Power Supply: 3.3V ± 0.3V ? 16ms, 1024-cycle refresh

? Supports RAS-Only-Refresh (ROR), CAS-before-RAS (CBR) refresh and Hidden refresh cycles ? Serial Presence Detect (SPD)

? LVTTL Compatible Inputs and Outputs ? One External Bank ? Gold PCB connector

General Description

The 64105sEGM1G07TB is a 1Mx72 bit, 7 chip,3.3V, 168 Pin DIMM module consisting of (4) 1Mx16(TSOP) DRAM, (2) 1Mx4 (TSOP) DRAM and (1)256x8 EEPROM for serial presence detect. The module is unbuffered and supports Extended Data Out (EDO)page mode access.

Valid Part Numbers

Part Number Access Time Supply Voltage 721055EGM1G07TB 50ns 3.3V 721056EGM1G07TB

60ns

3.3V

Block Diagram

SA0SA2

SA1

A0 - AN VCC

VSS X72 DRAM DIMM, 1 BANK with X16 DRAMs and X4 ECC

Pin Descriptions

Pin Name Function

RAS#Row Address Strobe RAS# is used to strobe the row address.

CAS#Column Address Strobe CAS# is used to strobe the column address.

WE#Write Enable WE# is used to control read/write cycles.

OE#Output Enable OE# is the input/output control for the DQ lines.

A#Address Lines Address lines are multiplexed to specify the row and column address. DQ0-DQ63Data Lines Data input/output lines.

CB0-CB7Check Bits Check bit input/output lines used for ECC.

Vdd Power Supply Power Supply 3.3V±0.3V

Vss Ground Ground

SDA, SCL SPD Data/Clock Lines Serial Presence Detect (SPD) EEPROM bus lines. These line provides

bi-directional data transfer over an I2C bus.

SA0 – SA2SPD Address Lines Serial Presence Detect (SPD) EEPROM address lines. These lines are

used to configure the SPD.

NC No Connection Line is not connected in DIMM.

Serial Presence Detect Matrix

Byte #Function

Description

Binary Hex

76543210MS-LS 0Define # of bytes written into EEPROM1000000080128 1Total # of bytes of SPD memory device0000100008256 2Fundamental memory type (EDO,SDRAM...)0000001002EDO 3# of row addresses000010100A10 4# of column addresses000010100A10 5# of module rows00000001011 6Data width (010*********)

7...Data width continued000000000000

8Voltage interface0000001103 3.3V 9tRAC (-60)001111003C60ns 9tRAC (-50)001100103250ns 10tCAC (-60)000011110F15ns 10tCAC (-50)000011010D13ns 11DIMM configuration type (non-parity,ECC…)0000001002ECC 12Refresh rate/type0000000000Normal (15.6μs) 13Primary SDRAM width000100001016 14Error checking SDRAM width00000100044 15-127Reserved00000000000

128-255Not Used00000000000

Absolute Maximum Ratings

Parameter Symbol Value Units

Voltage on any pin relative to Vss V in-0.5 to 4.6V

Short circuit output current I out50mA

Power dissipation Pt8W

Operating temperature T opr0 to +70°C

Storage temperature T st-55 to +125°C

NOTE: Permanent damage may occur if absolute maximum ratings are exceeded.

Device should be operated within recommended operating conditions only.

DC Characteristics (T A = 0 to 70C, Vcc = 3.3V ± 0.3V)

Parameter Symbol Min Typ Max Units Note Supply voltage Vss000V

Supply voltage Vcc 3.0 3.3 3.6V16 Input high voltage Vih 2.0-Vcc+0.3V16 Input low voltage Vil-0.5-0.8V16 Output high voltage Voh 2.4--V

Output low voltage Vol--0.8V

DC Current Consumption (T A = 0 to 70C, Vcc = 3.3V ± 0.3V)

Parameter Symbol Test Condition-50-60Unit Note Standby Current (TTL)I CC1(RAS# = CAS# = V IH)1212mA17 Standby Current (CMOS)I CC2All inputs = Vcc - 0.2V66mA17 Operating Current Random Read/Write I CC3RAS#, CAS#, address cycling. t RC = t RC[MIN]936756mA17, 18 Operating Current Fast Page Mode I CC4RAS# = V IL, CAS#, Address cycling. t PC = t PC[MIN]N/A N/A mA17, 18 Operating Current EDO Page Mode I CC5RAS# = V IL, CAS#, Address cycling. t PC = t PC[MIN]396288mA17, 18 Refresh Current: RAS#-Only I CC6RAS# cycling, CAS#=V IH; t RC = t RC[MIN]936756mA17 Refresh Current: CAS# before RAS#I CC7RAS#, CAS#, address cycling t RC = t RC[MIN]936756mA17

Capacitance (T A = 0 to 70C, Vcc = 3.3V ± 0.3V, Vss = 0V)

Parameter Symbol Typ Max Units Note

Input capacitance (Address)C I1-30pF

Input capacitance (WE#, OE#)C I2-28pF

Input/Output capacitance (Data)C I/O-7pF

Input capacitance (CAS#)C I3-28pF

Input/Output capacitance (SDA,SCL,SAm)-10pF

Input capacitance (RAS#)C14-28pF

AC Characteristics (T A = 0 to 70C, Vcc = 3.3V ± 0.3V, Vss = 0V)

Units Note Parameter Symbol

-50-60

Min Max Min Max

Access time from column address t AA2530ns3, 5, 14 Column address setup to CAS# precharge t ACH1215ns

Column address hold time (from RAS#)t AR4050ns

Column address setup time t ASC00ns

Row address setup time t ASR00ns

Access time from CAS#t CAC1517ns3, 4, 14 Column address hold time t CAH810ns

CAS# pulse width t CAS810 0001010 000ns

CAS# to output in Low-Z t CLZ33ns

Data output hold after CAS# LOW t COH33ns

CAS# precharge time t CP810ns

Access time from CAS# precharge t CPA2835ns

CAS# to RAS# precharge time t CRP55ns

CAS# hold time t CSH4050ns

WRITE command to CAS# lead time t CWL810ns

Data-in hold time t DH810ns11 Data-in setup time t DS00ns11 Output buffer turn-off delay t OFF012015ns

EDO Page-mode read or write cycle time t PC2025ns

Access time from RAS#t RAC5060ns2, 3 RAS# to column address delay time t RAD15251530ns9 Row-address hold time t RAH1010ns

RAS# pulse width t RAS, t RASP5010 0006010 000ns

Random read/write cycle time t RC84104ns

RAS# to CAS# delay time t RCD20352043ns8 Read command hold time t RCH00ns

Read command setup time t RCS00ns

Refresh Period (1024 cycles)t REF1616ms15 RAS# precharge time t RP3040ns

RAS# to CAS# precharge time t RPC55ns

READ command hold time t RRH00ns

RAS# hold time t RSH1317ns

WRITE command to RAS# lead time t RWL1315ns

Transition Time tτ250250ns7

AC Characteristics (T A = 0 to 70C, Vcc = 3.3V ± 0.3V, Vss = 0V)

Units Note Parameter Symbol

-50-60

Min Max Min Max

WRITE command hold time t WCH810ns

WRITE command hold time (RAS# referenced)t WCR3845ns

WE# command setup time t WCS00ns10 Output disable delay from WE#t WHZ012015ns

Write command pulse width t WP55ns

Notes

1.AC measurements assume t T = 5ns

2.Assumes that t RCD≤ t RCD (max.) and t RAD≥ t RAD (max.). If t RCD or t RAD is greater that the maximum recommended value shown in this table, t RAC

exceeds the value shown.

3.Measured with a load circuit equivilaent to 1 TTL load and 100pF.

4.Assumes that t RCD≥ t RCD (max.), t RAD≤ t RAD (max.).

5.Assumes that t RCD≤ t RCD (max.), t RAD≥ t RAD (max.).

6.t OFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.

7.Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vih and Vil.

8.Operation with the t RCD (max.) limit insures that t RAC (max.) can be met, t RCD (max.) is specified as a reference point only, if t RCD is greater that the

specified t RCD (max.) limit, then the access time is controlled exclusively by t CAC.

9.Operation with the t RAD (max.) limit insures that t RAC (max.) can be met, t RAD (max.) is specified as a reference point only, if t RAD is greater that the

specified t RAD (max.) limit, then access time is controlled exclusively by t AA.

10.Early write cycle only (t WCS≥ t WCS (min.))

11.These parameters are referenced to CAS* leading edge in an early write cycle.

12.An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS*

clock such as RAS* only refresh)

13.t RASC defines RAS* pulse width in fast page mode cycles.

14.Access time is determined by the longer of t AA or t CAC or t ACP

15.t REF defined is 1,024 refresh cycle.

16.All voltages referenced to Vss

17.Typical maximum current consumption levels

18.Column address changed once per cycle

t RAS

t RC t CRP

t RCD

t CAS

t RSH

t CSH t RRH

t ASR

t RAH

t RAD

t ACH

t CAH t ASC

t AR

t RCS

t RCH

t CLZ

t CAC t RAC t AA t OFF

ADDR

DQ CAS

RAS

ROW

COLUMN

ROW

VALID DATA

OPEN

READ CYCLE

DON'T CARE

UNDEFINED

t RP

t RAS

t RC t CRP

t RCD

t CAS

t RSH t CSH

t ASR

t RAH

t RAD

t ACH

t CAH t ASC t AR t WP

t WCH t WCR t RWL

ADDR

DQ CAS

ROW

COLUMN

ROW

VALID DATA

EARLY WRITE CYCLE

DON'T CARE UNDEFINED

t WCS

t CWL t DH

t DS

RASP

CRP

RCD

CSH

CAS

RSH

ASR

RAH

RAD

ASC

CAH

ASC

CAH

ASC

CAH

RCS

RCH

OFF

CLZ

CAC

CPA

COH

CAC

CPA

CLZ

CAC

RAC

ADDR

DON'T CARE

UNDEFINED ROW ROW

COLUMN

COLUMN COLUMN

VALID

DATA

VALID

DATA

VALID

DATA

EDO-PAGE-MODE READ CYCLE

ACH

CAH

RRH OPEN

OPEN

RASP

CRP

RCD

CSH

CAS

RSH

ASR

RAH

RAD

ASC

CAH

ASC

CAH

ASC

CAH

COH

CAC

RAC

ADDR

CAS

RAS

DON'T CARE

UNDEFINED ROW ROW

COLUMN (B)

COLUMN (A)COLUMN (N)

VALID Dout VALID Dout VALID Din

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE

ACH

RCH

WCS

WCH

RCS

WHZ

CPA

OPEN

RASP

CRP

RCD

CSH

CAS

RSH

ASR

RAH

RAD

ASC

CAH

ASC

CAH

ASC

CAH

CAC

WCR

ADDR

CAS

RAS

DON'T CARE

UNDEFINED ROW ROW

COLUMN

COLUMN COLUMN

VALID DATA VALID DATA VALID DATA

FAST/EDO-PAGE-MODE EARLY-WRITE CYCLE

ACH

WCH

CWL

WCS

WCH

CWL

WCS

WCH

CWL

WCS

RWL

CRP

RCD

CSH

CAS

ASR

RAH

RAD

ASC

CAH

ASC

ROW COLUMN COLUMN

RCS

RCH

WPZ

RCS

OPEN

CLZ

CAC

RAC

WHZ

OPEN

CLZ

DON'T CARE

UNDEFINED

VALID DATA

EDO READ CYCLE

( with /WE-controlled disable )

ADDR

CAS

RAS

t RP

t RAS

t RC

CRP

t RPC

t ASR

t RAH

ROW

OPEN

/RAS-ONLY REFRESH CYCLE

DON'T CARE UNDEFINED

ADDR

Q RAS

CASL / CASH

t RP

t RAS

t CP

t CHR

OPEN

DON'T CARE UNDEFINED

t RP

t RAS

t RPC t CSR

t RPC

t CSR

t CHR

t WRP t WRH

CAS

RAS

CBR REFRESH CYCLE

( Addresses = DON'T CARE )

Note: Drawing is for component location only, assembly may not have all components installed.