MAX807中文资料
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
________________________________________________________________Maxim Integrated Products
1
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19-0433; Rev 0; 9/95
_______________General Description
The MAX807 microprocessor (μP) supervisory circuit reduces the complexity and number of components needed to monitor power-supply and battery-control func-tions in μP systems. A 70μA supply current makes the MAX807 ideal for use in portable equipment, while a 2ns chip-enable propagation delay and 250mA output current capability (20mA in battery-backup mode) make it suit-able for larger, higher-performance equipment.
The MAX807 comes in 16-pin DIP and SO packages, and provides the following functions:
1)output is asserted dur-ing power-up, power-down, and brownout conditions,and is guaranteed to be in the correct state for V CC down to 1V.
2)Active-high RESET output.3)Manual-reset input.
4)Two-stage power-fail warning. A separate low-line comparator compares V CC to a threshold 52mV above the reset threshold. This low-line comparator is more accurate than those in previous μP supervisors.
5) Backup-battery switchover for CMOS RAM, real-time clocks, μPs, or other low-power logic.
6)Write protection of CMOS RAM or EEPROM.
7) 2.275V threshold detector—provides for power-fail warning and low-battery detection, or monitors a power supply other than +5V.
8)BATT OK status flag indicates that the backup-battery voltage is above 2.275V.
9)Watchdog-fault output—asserted if the watchdog input has not been toggled within a preset timeout period.
________________________Applications
Computers Controllers
Intelligent Instruments Critical μP Power Monitoring Portable/Battery-Powered Equipment
____________________________Features
o Precision 4.675V (MAX807L) or 4.425V (MAX807M), or 4.575V (MAX807N) Voltage Monitoring o 200ms Power OK / Reset Time Delay o and RESET Outputs o Independent Watchdog Timer o 1μA Standby Current
o Power Switching:
250mA in V CC Mode
20mA in Battery-Backup Mode
o On-Board Gating of Chip-Enable Signals:
2ns CE Gate Propagation Delay o MaxCap?and SuperCap?Compatible o Voltage Monitor for Power-Fail o Backup-Battery Monitor
o Guaranteed RESET Valid to V CC = 1V
o ±1.5% Low-line Threshold Accuracy 52mV above Reset Threshold
__________________Pin Configuration
Ordering Information and Typical Operating Circuit appear at end of data sheet.
SuperCap is a trademark of Baknor Industries. MaxCap is a trademark of The Carborundum Corp.
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 2
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,V
= 2.8V, V = 0V, T = T to T . Typical values are tested with V = 5V and T = +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Input Voltages (with respect to GND)
V CC ..........................................................................-0.3V to 6V V BATT .......................................................................-0.3V to 6V All Other Inputs......................................-0.3V to (V OUT + 0.3V)Input Current
V CC Peak ...........................................................................1.0A V CC Continuous.............................................................500mA I BATT Peak......................................................................250mA I BATT Continuous .............................................................50mA GND.................................................................................50mA All Other Inputs................................................................50mA
Continuous Power Dissipation (T A = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C)...........842mW Wide SO (derate 9.52mW/°C above +70°C).................762mW CERDIP (derate 10.00mW/°C above +70°C)................800mW Operating Temperature Ranges
MAX807_C_E.......................................................0°C to +70°C MAX807_E_E....................................................-40°C to +85°C MAX807_MJE .................................................-55°C to +125°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°C
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
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ELECTRICAL CHARACTERISTICS (continued)
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,V = 2.8V, V = 0V, T = T to T . Typical values are tested with V = 5V and T = +25°C, unless otherwise noted.)
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 4_______________________________________________________________________________________
Note 1:Either V CC or V BATT can go to 0V, if the other is greater than 2.0V.
Note 2:The supply current drawn by the MAX807 from the battery (excluding I OUT ) typically goes to 15μA when (V BATT - 0.1V)
< V CC < V BATT . In most applications, this is a brief period as V CC falls through this region (see Typical Operating Characteristics ).
Note 3:“+”= battery discharging current, “-”= battery charging current.
Note 4:WDI is internally connected to a voltage divider between V CC and GND. If unconnected, WDI is driven to 1.8V (typical),
disabling the watchdog function.
Note 5:Overdrive (V OD ) is measured from center of hysteresis band.
Note 6:The chip-enable resistance is tested with V CE IN = V CC /2, and I CE IN = 1mA.
Note 7:The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,V BATT = 2.8V, V PFI = 0V, T A = T MIN to T MAX . Typical values are tested with V CC = 5V and T A = +25°C, unless otherwise noted.)
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
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8060
-60-2060140V CC SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
6476M A X 807-01
TEMPERATURE (°C)V C C S U P P L Y C U R R E N T (μA )
20100-40401200
8072686266787470 3.02.52.01.51.00.50
-60-2060140
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
M A X 807-02
TEMPERATURE (°C)B A T T E R Y S U P P L Y C U R R E N T (μA )
20100-40401200806543210
-60-2060140
CHIP-ENABLE PROPAGATION DELAY
vs. TEMPERATURE
M A X 807-03
TEMPERATURE (°C)
P R O P A G A T I O N D E L A Y (n s )
20100-4040120080305
-60-2060140BATT-to-OUT ON-RESISTANCE
vs. TEMPERATURE
10
25
TEMPERATURE (°C)
B A T T -t o -O U T O N -R E S I S T A N
C E (?)
20100-40401200
8020
15
4.704.654.604.554.504.454.40
-60-2060140RESET THRESHOLD vs. TEMPERATURE
TEMPERATURE (°C)R E S E T T H R E S H O L D (V )20100-40401200
80 1.6
1.51.41.31.21.11.00.90.80.7
-60-2060140V CC -to-OUT ON-RESISTANCE
vs. TEMPERATURE
TEMPERATURE (°C)V C C -t o -O U T O N -R E S I S T A N C E (?)
20100-40401200
80 2.340
2.3202.3002.2802.2602.2402.2202.200
-60-2060140
PFI THRESHOLD
vs. TEMPERATURE (V PFI FALLING)
M A X 807-06
TEMPERATURE (°C)
P F I T H R E S H O L D (V )20100-4040120080280260240220200180160140
-60-2060140
RESET TIMEOUT PERIOD vs. TEMPERATURE (V CC RISING)
M A X 807-08
TEMPERATURE (°C)
R E S E T T I M E O U T P E R I O D (m s )
20100-40401200
800
1020304050607080
-60-2060140
LOW LINE -to-RESET THRESHOLD vs. TEMPERATURE (V CC FALLING)
M A X 807-09
TEMPERATURE (°C)
L O W L I N E -t o -R E S E T T H R E S H O L D (m V )
20100-40401200
80__________________________________________Typical Operating Characteristics
(V CC = 5V, V BATT = 2.8V, PFI = 0V, no load, T A = +25°C, unless otherwise noted.)
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 6_______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(V CC = 5V, V BATT = 2.8V, PFI = 0V, no load, T A = +25°C, unless otherwise noted.)
4.754.804.704.654.604.554.504.45 4.40
-60-2060140LOW LINE THRESHOLD
vs. TEMPERATURE (V CC RISING)
TEMPERATURE (°C)L O W L I N E T H R E S H O L D (V )
20100-40401200
800
510152025303540-60-2060140
LOW LINE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE (V CC FALLING)
TEMPERATURE (°C)
L O W L I N E C O M P A R A T O R P R O P . D E L A Y (μs )
20100-40401200
800
510152025303540
-60-2060
140RESET COMPARATOR PROPAGATION DELAY vs. TEMPERATURE (V CC FALLING)
TEMPERATURE (°C)
R E S E T C O M P A R A T O R P R O P . D E L A Y (μs )
20100-40401200
8002468101214162.5
2.6
2.7
2.8
2.9
3.0
BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE
M A X 807-13
V CC (V)
B A T T E R Y
C U R R E N T (μA )
1000
100
10
11
100
10
1000
V CC -to-OUT vs. OUTPUT CURRENT
I OUT (mA)
V C C -V O U T (m V )
50? DRIVER
2
46
80
50100
CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE
M A X 807-14
C LOA
D (pF)
P R O P A G A T I O N D E L A Y (n s
)
1000
100
10
1
10100
BATT-to-OUT vs. OUTPUT CURRENT
I OUT (mA)
B A T T -t o -O U T (m V )
1000
100
10
11
100
10
1000
MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE
RESET COMPARATOR OVERDRIVE (mV)
M A X I M U M T R A N S I E N T D U R A T I O N (μs )
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
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______________________________________________________________Pin Description
_______________Detailed Description
The MAX807 microprocessor (μP) supervisory circuit provides power-supply monitoring, backup-battery switchover, and program execution watchdog functions in μP systems (Figure 1). Use of BiCMOS technology results in an improved 1.5% reset-threshold precision,while keeping supply currents typically below 70μA.The MAX807 is intended for battery-powered applica-tions that require high reset-threshold precision, allow-ing a wide power-supply operating range while preventing the system from operating below its speci-fied voltage range.
RESET and RESET Outputs
The MAX807’s RESET output ensures that the μP pow-ers up in a known state, and prevents code execution errors during power-down and brownout conditions. It accomplishes this by resetting the μP, terminating pro-gram execution when V CC dips below the reset thresh-old or MR is pulled low. Each time RESET is asserted it stays low for the 200ms reset timeout period, which is set by an internal timer to ensure the μP has adequate time to return to an initial state. Any time V CC goes below the reset threshold before the reset timeout peri-od is completed, the internal timer restarts. The watch-dog timer can also initiate a reset if WDO is connected to MR. See the Watchdog Input section.
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 8
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Figure 1. Block Diagram
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________9
output is active low and implemented with a strong pull-down/relatively weak pull-up structure. It is guaranteed to be a logic low for 0V < V CC < V RST , pro-vided V BATT is greater than 2V. Without a backup bat-is guaranteed valid for V CC ≥1. It typically sinks 3.2mA at 0.1V saturation voltage in its active state.The RESET output is the inverse of the RESET output; it both sources and sinks current and cannot be wire-OR connected.
Manual Reset Input
Many μP-based products require manual-reset capabil-ity to allow an operator or test technician to initiate a tion of a reset in response to a logic low from a switch,WDO, or external circuitry. Reset remains asserted while MR is low, and for 200ms after MR returns high. MR has an internal 50μA to 200μA pull-up current, so it can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function;is dri-ven from long cables or if the device is used in a noisy to ground to provide additional noise immunity. As shown in Figure 3, diode-ORed connections can be used to allow manual resets from multiple sources. Figure 4shows the reset timing.
Watchdog Input
The watchdog circuit monitors the μP’s activity. If the μP does not toggle the watchdog input (WDI) within 1.6sec, WDO goes low. The internal 1.6sec timer is returns high when reset is asserted or when a transition (low-to-high or high-to-low) occurs is high. As long as reset is assert-ed, the timer remains cleared and does not count. As soon as reset is released, the timer starts counting (Figure 5). Supply current is typically reduced by 10μA when WDI is at a valid logic level.
Figure 2a. Timing Diagram, V CC Rising Figure 2b. Timing Diagram, V CC Falling
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 10
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Watchdog Output
WDO remains high if there is a transition or pulse at WDI during the watchdog timeout period. WDO goes low if no transition occurs at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when V CC is below the reset threshold or WDI is an open circuit. To generate a sys-tem reset on every watchdog fault, simply diode-OR connect WDO to MR (Figure 6). When a watchdog fault occurs in this mode, WDO goes low, which pulls MR low, causing a reset pulse to be issued. As soon as reset is asserted, the watchdog timer clears and WDO returns high. With WDO connected to MR, a continuous high or low on WDI will cause 200ms reset pulses to be issued every 1.6sec.
Chip-Enable Signal Gating
The MAX807 provides internal gating of chip-enable (CE) signals to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The MAX807 uses a series transmission gate from the Chip-Enable Input (CE IN) to the Chip-Enable Output (CE OUT) (Figure 1).
The 8ns max chip-enable propagation from CE IN to CE OUT enables the MAX807 to be used with most μPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET is asserted. During a power-down sequence when V CC passes the reset threshold, the CE transmission gate disables and CE IN becomes high impedance 28μs after reset is asserted (Figure 7). During a power-up sequence, CE IN remains high impedance (regardless of CE IN activity) until reset is deasserted following the reset-timeout period.
In the high-impedance mode, the leakage currents into this input are ±1μA max over temperature. In the low-impedance mode, the impedance of CE IN appears as a 75?resistor in series with the load at CE OUT.
The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on CE OUT
Figure 4. Manual-Reset Timing Diagram
Figure 5. Watchdog Timing Relationship Figure 6. Generating a Reset on Each Watchdog Fault
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________
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Load Capacitance graph in the Typical Operating Characteristics ). The CE propagation delay is produc-tion tested from the 50% point on CE IN to the 50%point on CE OUT using a 50?driver and 50pF of load capacitance (Figure 8). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equiv-alent to 75?in series with the source driving CE IN. In the disabled mode, the 75?transmission gate is off and CE OUT is actively pulled to the higher of V CC or V BATT . This source turns off when the transmission gate is enabled.
Low-Line Comparator
The low-line comparator monitors V CC with a threshold voltage typically 52mV above the reset threshold, with 13mV of hysteresis. Use LOW LINE to provide a non-maskable interrupt (NMI) to the μP when power begins to fall, to initiate an orderly software shutdown routine.In most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine once the low-line warning is encountered, and before reset asserts. If the system must contend with a more rapid V CC fall time—such as when the main battery is disconnected, a DC-DC con-verter shuts down, or a high-side switch is opened dur-ing normal operation—use capacitance on the V CC line to provide time to execute the shutdown routine (Figure 9). First calculate the worst-case time required for the system to perform its shutdown routine. Then, with the
and the minimum low-line to reset threshold (V LR(min)),calculate the amount of capacitance required to allow the shutdown routine to complete before reset is asserted:
C HOL
D = (I LOAD x t SHDN ) / V LR (min)
where t SHDN is the time required for the system to com-plete the shutdown routine, and includes the V CC to low-line propagation delay; and where I LOAD is the cur-rent being drained from the capacitor, V LR is the low-line to reset threshold.
Figure 8. CE Propagation Delay Test Circuit
M A X 807L /M /N
Power-Fail Comparator
PFI is the noninverting input to an uncommitted com-parator. If PFI is less than V PFT (2.265V), PFO goes low.The power-fail comparator is intended to monitor the preregulated input of the power supply, providing an early power-fail warning so software can conduct an orderly shutdown. It can also be used to monitor sup-plies other than 5V. Set the power-fail threshold with a resistor divider, as shown in Figure 10.
Power-Fail Input
PFI is the input to the power-fail comparator. The typical comparator delay is 14μs from V IL to V OL (power failing),and 32μs from V IH to V OH (power being restored). If unused, connect this input to ground.
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes below V PFT . It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above V PFT , PFO is actively pulled to V CC . Connecting PFI through a voltage divider to a preregulated supply allows PFO to generate an NMI as the preregulated power begins to fall (Figure 11b). If the preregulated supply is inaccessible, use LOW LINE LINE threshold is typically 52mV above the reset threshold (see Low-Line Comparator section).
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 12
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Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) V IN is Negative, b) V IN is Positive
Figure 11. a) If the preregulated supply is inaccessible, LOW LINE generates the NMI for the μP. b) Use PFO to generate the μP NMI if the preregulated supply is accessible.
Battery-Backup Mode
Battery backup preserves the contents of RAM in the event of a brownout or power failure. With a backup battery installed at BATT, the MAX807 automatically switches RAM to backup power when V CC falls. Two conditions are required for switchover to battery-back-up mode: 1) V CC must be below the reset threshold; 2)V CC must be below V BATT . Table 1 lists the status of inputs and outputs during battery-backup mode.
Backup-Battery Input
The BATT input is similar to V CC , except the PMOS switch is much smaller. This input is designed to con-duct up to 20mA to OUT during battery backup. The on-resistance of the PMOS switch is approximately 13?. Figure 12 shows the two series pass elements between the BATT input and OUT that facilitates UL approval. V BATT can exceed V CC during normal opera-tion without causing a reset.
Output Supply Voltage
The output supply (OUT) transfers power from V CC or BATT to the μP, RAM, and other external circuitry. At the maximum source current of 250mA, V OUT will typi-cally be 260mV below V CC . Decouple this terminal with a 0.1μF capacitor.
BATT ON Output
The battery on (BATT ON) output indicates the status of the internal battery switchover comparator, which con-trols the internal V CC and BATT switches. For V CC greater than V BATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.4V. In bat-tery-backup mode, this output sources approximately 5mA. Use BATT ON to indicate battery switchover sta-tus, or to supply gate or base drive for an external pass transistor for higher current applications (see Typical Operating Circuit ).
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________
13
Figure 12. V CC and BATT-to-OUT Switch
Table 1. Input and Output Status in Battery-Backup Mode
M A X 807L /M /N
BATT OK Output
The BATT OK comparator monitors the backup battery voltage, comparing it with a 2.265V reference (V CC ≥4V). BATT OK remains high as long as the backup bat-tery voltage remains above 2.265V, signaling that the backup battery has sufficient voltage to maintain the memory of static RAM. When the battery voltage drops below 2.265V, the BATT OK output drops low, signaling that the backup battery needs to be changed.
__________Applications Information
The MAX807 is not short-circuit protected. Shorting OUT to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. If long leads connect to the IC’s inputs, ensure that these lines are free from ringing and other condi-tions that would forward bias the IC’s protection diodes.There are two distinct modes of operation:
1)Normal Operating Mode, with all circuitry powered up. Typical supply current from V CC is 70μA, while only leakage currents flow from the battery.
2)Battery-Backup Mode, where V CC is below V BATT
and V RST . The supply current from the battery is typ-ically less than 1μA.
Using SuperCaps? or
MaxCaps? with the MAX807
BATT has the same operating voltage range as V CC , and the battery-switchover threshold voltage is typically V BATT when V CC is decreasing or V BATT + 0.06V when V CC is increasing. This hysteresis allows use of a
SuperCap (e.g., order of 0.47F) and a simple charging circuit as a backup source (Figure 13). Since V BATT can exceed V CC while V CC is above the reset threshold,there are no special precautions when using these μP supervisors with a SuperCap.
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows the MAX807 CE loop to be bypassed. To do this, con-nect CE IN to ground, pull up CE OUT to OUT, and connect CE OUT to the CE input of each memory device (Figure 14). The CE input of each part then con-nects directly to the chip-select logic, which does not have to be gated by the MAX807.
Adding Hysteresis to the Power-Fail Comparator
The power-fail comparator has a typical input hystere-sis of 20mV. This is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (Figure 10).
Figure 15 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 2.265V when V IN falls to the desired trip point (V TRIP ). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The cur-rent through R1 and R2 should be at least 1μA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k ?to prevent it from loading down the PFO pin. Capacitor C1adds additional noise rejection.
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy 14
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Figure 13. SuperCap or MaxCap on BATT
Figure 14. Alternate CE Gating
Backup-Battery Replacement
The backup battery may be disconnected while V CC is above the reset threshold, provided BATT is bypassed with a 0.1μF capacitor to ground. No precautions are necessary to avoid spurious reset pulses.
Negative-Going V CC Transients
While issuing resets to the μP during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going V CC transients (glitches). It is usually undesirable to reset the μP when V CC experiences only small glitches.
The Typical Operating Characteristics show Maximum Transient Duration vs. Reset Comparator Overdrive, for which reset pulses are not generated. The graph was produced using negative-going V CC pulses, starting at 5V and ending below the reset threshold by the magni-tude indicated (reset comparator overdrive). The graph shows the maximum pulse width that a negative-going V CC transient may typically have without causing a reset pulse to be issued. As the amplitude of the tran-sient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases.
Typically, a V CC transient that goes 40mV below the reset threshold and lasts for 3μs or less will not cause a reset pulse to be issued.
A 0.1μF bypass capacitor mounted close to the V CC pin provides additional transient immunity.
Watchdog Software Considerations
To help the watchdog timer keep a closer watch on soft-ware execution, you can use the method of setting and resetting the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck”loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out.Figure 16 shows an example flow diagram where the I/O driving the watchdog input is set high at the begin-ning of the program, set low at the beginning of every subroutine or loop, then set high again when the pro-gram returns to the beginning. If the program should “hang” in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.
Maximum V CC Fall Time
The V CC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/μs. A standard rule for filter capacitance on most regulators is on the order of 100μF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial V CC fall rate is just the inverse or 1A / 100μF = 0.01V/μs. The V CC fall rate decreases with time as V CC falls exponen-tially, which more than satisfies the maximum fall-time requirement.
MAX807L/M/N
Full-Featured μP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________
15
Figure 15. Adding Hysteresis to the Power-Fail Comparator
Figure 16. Watchdog Flow Diagram
M A X 807L /M /N
Full-Featured μP Supervisory Circuit with ±1.5% Reset Accuracy Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600?1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
______________Ordering Information
? This part offers a choice of reset threshold voltage. From the table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
__________Typical Operating Circuit
___________________Chip Information
TRANSISTOR COUNT: 984