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AD12501中文资料

12 Bit, 500MSPS A/D

Converter Preliminary Technical Data

AD12501

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

Up to 500 MSPS sample rate SNR of 63 dBFS @70 MHz SFDR of 70 dBFS @70 MHz VSWR of 1:1.5

Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential encode signal LVDS output levels

Twos complement output data

APPLICATIONS

Communications test equipment Radar and satellite subsystems

Phased array antennas—digital beam Multi-channel, multimode receivers Secure communications

Wireless and wired broadband communications Wideband carrier frequency systems

GENERAL DESCRIPTION

The AD12501 is a 12-bit analog-to-digital converter (ADC) with a transformer-coupled analog input driving amplifiers providing gain, and digital post-processing for enhanced SFDR. The product operates at up to 500 MSPS conversion rate with

outstanding dynamic performance in wideband carrier systems. The AD12501 requires 3.7 V analog, 3.3 V digital, and 1.5 V digital supplies, and provides a flexible encode signal that can be differential or single-ended. No external reference is required.

The AD12501 package style is an enclosed 2.9" × 2.6" × 0.6" module. Performance is rated over a 0°C to 60°C case temperature range.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate up to 500 MSPS.

2. Input signal conditioning with optimized dynamic

performance to 225 MHz. 3. Additional performance options available (sample rates up

to 525MSPS or 2nd Nyquist zone operation); contact factory. 4. Proprietary Advanced Filter Bank (AFB?) digital post-processing from V Corp Technologies, Inc.

AD12501Preliminary Technical Data

SPECIFICATIONS

DC SPECIFICATIONS

V A = 3.7V, VC = 3.3 V, VD = 1.5 V, encode = 500 MSPS, 0°C ≤ T CASE ≤ 60°C, unless otherwise noted.

1 Tested using input frequency of 70 MHz. See Figure 17

2 All ac specifications tested by driving ENC single-ended.

3 Refer to Table 5 for logic convention on all logic inputs.

4 Digital output logic levels: VC = 3.3 V, C LOAD = 8 pF. 3.3 V LVDS, R1 = 100 Ω.

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Preliminary Technical Data

AD12501

Rev. PrB| Page 3 of 7

AC SPECIFICATIONS 1

V A = 3.7 V , VC = 3.3 V , VD = 1.5 V , encode = 500 MSPS, 0°C ≤ T CASE ≤ 60°C, unless otherwise noted. Table 2.

AD12501-500KWS Parameter Case Temp Test Level Min Typ Max Unit

DYNAMIC PERFORMANCE 2

SNR

Analog Input 10 MHz Full I 64 dBFS @ ?1.0 dBFS 70 MHz Full I 63.5 dBFS 128 MHz Full I 63 dBFS 225 MHz Full I 62.5 dBFS SINAD 3 Analog Input 10 MHz Full I 63.5 dBFS @ ?1.0 dBFS 70 MHz Full I 63 dBFS 128 MHz Full I 62.5 dBFS 225 MHz Full I 61 dBFS

Spurious-Free Dynamic Range 3

Analog Input 10 MHz Full I 80 dBFS @ ?1.0 dBFS 70 MHz Full I 84 dBFS 128 MHz Full I 76 dBFS 225 MHz Full I 71 dBFS

Image Spur 4

Analog Input 10 MHz Full I 75 dBFS @ ?1.0 dBFS 70 MHz Full I 70 dBFS 128 MHz Full I 68 dBFS 225 MHz Full I 60 dBFS

Offset Spur 4

Analog Input @ ?1.0 dBFS 60°C V 65 dBFS Two-Tone IMD 5 F1, F2 @ ?6 dBFS 60°C V ?75 dBc SWITCHING SPECIFICATIONS

Conversion Rate 6

Full I V 495 500 505 MSPS

Encode Pulse Width High (t EH )1

60°C V 1 ns

Encode Pulse Width Low (t EL )1

60°C V 1 ns DIGITAL OUTPUT PARAMETERS Valid Time (t V ) Full IV TBD ns Propagation Delay (t PD ) 60°C V TBD ns Rise Time (t R ) (20% to 80%) 60°C V TBD ns Fall Time (t F ) (20% to 80%) 60°C V TBD ns DR Propagation Delay (t EDR ) 60°C V TBD ns Data to DR Skew (t EDR ? t PD ) 60°C V TBD ns

Pipeline Latency 7

Full I V TBD Cycles

Aperture Delay (t A ) 60°C V TBD ns

Aperture Uncertainty (Jitter, t J ) 60°C V TBD ps rms

1 All ac specifications tested with a single-ended, 2.0 V p-p encode.

Dynamic performance guaranteed for analog input frequencies of 1 MHz to 225 MHz. 3

Not including image spur. 4

The image spur is at f s /2 – A IN ; the offset spur is at f s /2. 5

F1 = 70 MHz, F2 = 73 MHz. 6

Parts are tested with 500 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design for encode 500 MSPS ±1%. 7

Pipeline latency is exactly TBD cycles.

AD12501

Preliminary Technical Data

Rev.PrB | Page 4 of 7

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Value VA to AGND 5 V VC to DGND 4 V VD to DGND 1.65 V

Analog Input Voltage 6 V (dc)

Analog Input Power TBD dBm (ac)

Encode Input Voltage 6 V (dc)

Encode Input Power

12 dBm (ac) Logic Inputs and Outputs to DGND 5 V

Storage Temperature Range, Ambient ?65°C to +150°C Operating Temperature

0°C to 60°C

EXPLANATION OF TEST LEVELS

Level Description I 100% production tested. II 100% production tested at 25°C and sample tested at

specified temperatures.

III Sample tested only. IV Parameter is guaranteed by design and characterization

testing.

V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design

and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy E S D. Therefore, proper ES D precautions should be taken to avoid performance degradation or loss of functionality.

Preliminary Technical Data

AD12501

Rev. PrB| Page 5 of 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A D 12401-005

BOTTOM VIEW

LEFT SIDE VIEW

AIN

ENC

1INTEGRAL GROUND PLANE CONNECTIONS. SECTION A = DGND, PINS 121–124. SECTION B = DGND, PINS 125–128.

SECTION C = AGND, PINS 129–132.

NOTES

1. FOR MATING HALF, USE SAMTEC, INC. PART NO. QSE-60-01-L-D-A-K.ENC

END VIEW

TOP VIEW

PIN 1

AIN

ENC

PIN 120

PIN 2

PIN 40

PIN 1PIN 119

PIN 80

PIN 79

PIN 39

Figure 2. Pin Configuration

AD12501 Preliminary Technical Data

Rev.PrB | Page 6 of 7

Preliminary Technical Data

AD12501

Rev. PrB| Page 7 of 7

Internal ground plane connections: Section A = DGND, Pins 121 to 124; Section B = DGND, Pins 125 to 128; Section C = AGND, Pins 129 to 132.

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