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Improvement of power supply rejection ratio of LDO deteriorated by reducing power consumption

Improvement of Power Supply Rejection Ratio

of LDO Deteriorated

By Reducing Power Consumption

Socheat HENG and Cong-Kha PHAM

Department of Electronic Engineering,

The University of Electro-Communications

Tokyo,JAPAN

Email:socheat@vlsilab.ee.uec.ac.jp;pham@ee.uec.ac.jp

Abstract—In this work,the bulk-gate controlled circuit to improve the power supply ripple ratio(PSRR)of a Low Dropout Regulator(LDO)which deteriorates due to lowering power consumption is proposed.Designing with0.25μm CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though1/10of the power consumption is reduced compare to the conventional circuit.It is con?rmed that about40[dB]at10[Hz]frequency and20[dB]at1[kHz]frequency of PSRR are together improved.

I.I NTRODUCTION

When the operation voltage of electronic devices is supplied by a DC-DC converter,it is impossible to avoid the ripple noise voltage comes along the power supply line.For the communications devices such as mobile phones which have the transmission and reception circuit which operates at a high frequency,the ripple noise of the power supply line has a bad in?uence on the stability of the transmission frequency. The instability of the transmission frequency will result in a deteriorated voice or communication quality.Hence,it is necessary to reduce the ripple noise voltage as much as possible.

To reduce a ripple noise voltage,needless to say,it was required to maintain the response speed of the error ampli?er. This is the main reason that makes the bias current of the error ampli?er cannot be reduced.As a result,a low power LDO having a high PSRR performance can not be realized with a conventional LDO structure.

In this paper,we proposed a bulk-gate controlled circuit applied to the input transistors of the error ampli?er of a LDO to achieve the high PSRR performance.With the proposed circuit,although the operation current of the error ampli?er is dramatically reduced,it is possible to remove the big ripple noise and improve the PSRR performance of the LDO.More over,the proposed circuit is composed of a few elements which is suitable for LSI design and implementation.

II.R ELATIONSHIP BETWEEN PSRR AND POWER

CONSUMPTION

Fig.1shows the structure of a conventional LDO.In this simplest kind of structure,the power supply rejection

ratio

Fig.1.Basic Low Dropout Regulator Circuit. (PSRR)can be determined by three regions of frequency. They are the PSRR at DC and a low frequency P SRR DC, the PSRR at a moderate frequency P SRR MF and the PSRR at a high frequency P SRR HF.In this work,we focus only on the improvement of P SRR DC and P SRR MF which are generally demanded by most of applications.It means that the improvement of the PSRR at a frequency range of several[Hz] to about10[KHz].The de?nition of the PSRR at a low and moderate frequencies can be summarized as follows[1]. The?rst region of the PSRR(DC and low frequency)is intimately related to the open-loop gain of the system and expressed by the following equation.

P SRR DC～

A ol?dcβ

(1)

Where,A ol?dc is the open-loop gain of the system andβis de?ned by R2/(R1+R2).

The second region of the PSRR at a moderate frequencies is intimately related to the open-loop gain of the system and the bandwidth of the ampli?er.It is,thus,expressed by the following equation.

P SRR MF～

BW A

(A ol?dcβ)

UGF

(2)

Where,BW A is the bandwidth and UGF is the unity-gain frequency of the error ampli?er.

From Equations(1)and(2),we can?nd that the PSRR of each region can be improved by using a high loop gain and wide bandwidth error ampli?er.However,it is a very hard work for achieving this kind of ampli?er,That is,to achieve a high loop gain ampli?er,it needs to increase the number output stages.And,this will not only increase the power consumption of the LDO but also result in a narrow bandwidth and a complicated phase compensation.A narrow bandwidth also means the slow response time of the LDO. Hence,more bias current will be need while it con?icts to our purpose of providing a low power consumption.

In this paper,we proposed a cancel circuit which is achieved by controlling the bulk-gate voltage of the input transistor for the error ampli?er.This method will provide us do not need to consider about the open-loop gain of the bandwidth of the error ampli?er as well as the unity gain frequency.

III.PSRR C HARACTERISTIC I MPROVEMENT T ECHNIQUE A.Fundamental Principle

The power supply rejection measures the LDO’s ability to suppress the power supply noise from its output.Assuming the contribution of the supply noise due to the bandgap reference is negligible and by using the methodology as shown in[2], the small signal variations of V OUT due to the supply noise V DD is given by the following equation[3].

V OUT V DD =

???

V OA

V DD

Aβ

g mp r dsp

Aβ

???

???(3)

Where,A is the gain of error ampli?er,g mp is the tran-conductance of the power MOSFET,r dsp is the ON resistance of the power MOSFET and V OA is the error ampli?er output voltage.

From Equation(3),the only way to improve the PSRR without considering the gain or the bandwidth of the error ampli?er is to make the value of V OA/V DD to be near to the value of1.That is,the error ampli?er output voltage V OA needs to be close to the supply voltage V DD,i.e.,having the error ampli?er output voltage V OA tracks with the supply voltage V DD at the source terminal of the power MOSFET.In a word,in this work,we proposed a circuit which can track the error ampli?er output voltage V OA with the variation of the supply voltage V DD,then a high PSRR without increasing the power consumption of the whole circuit can be expected.B.Proposed Circuit and PSRR Improvement

Fig.2shows the conventional LDO which employing the proposed circuit.The proposed circuit is composed only of three elements of transistor MK,resistor RK and capacitor CK.The operation of the proposed circuit is described in following.

Generally,the channel-length modulation of a MOSFET is well-known as the following equation.

ID=

μn C ox

(V GS?V T H)2(1+λV DS)(4) From the circuit shown in Fig.2,the drain voltage of the transistor MK can be expressed as follow.

V MK D=RK×

μn C ox

(V GS?V T H)2(1+λV DS)(5) When the transistor MK is designed to operates in saturation region,the variation of the drain voltage V MK D of the transistor MK to the supply voltage V DD is simpli?ed as follows.

ΔV MK D=kλΔV DD(6) k=RK×

μn C ox

(V GS?V T H)2(7) Let’s we do the same consideration for the input transistor M4of the error ampli?er.And,when the supply voltage V DD varies, e.g.,from low to high,with Equation(6), the bulk-gate voltage of transistor M4will increase.This results in decreasing the threshold voltage of the transistor M4due to the body effect of the MOSFET.Generally,the error ampli?er works to balance the reference voltage V REF and the feedback voltage V F B of the feedback network.For a constant reference voltage V REF,when the threshold voltage of the transistor M4becomes lower,the current?ows through transistors M4and M1will increase.Since the transistor M2 is connected in current mirror to the transistor M1,the current ?ows through transistors M2and M3will also increase. This results in increasing of the error ampli?er output voltage V OA.Totally,the error ampli?er output voltage V OA

which

Fig.2.Proposed Circuit.

Fig.3.Line regulation vs V DD change.

can track the supply voltage V DD can be achieved when the supply voltage V DD varies.With the same manner,when the supply voltage V DD moves from a high voltage to a low voltage,the error ampli?er output voltage V OA will decrease according to the V DD.

To cope with the channel-length modulation characteristic of the MOSFET,the channel size(W/L)of the transistor M4is adjusted for obtaining the variation voltageΔV MK D which matches with the requirement of the variation of the error ampli?er output voltage V OA.However,this effect can only demonstrates its performance in DC and a low frequency region.For achieving a high PSRR in a moderate frequency region,the capacitor CK in parallel to the transistor MK is added.Therefore,the variation voltageΔV MK D in a moderate frequency region can be expressed as follow.

ΔV MK D～

ΔV DD

RK+

jωCK

RK(8)

With the capacitor CK,the improvement of the PSRR in the frequency range of several[Hz]to about10[KHz]can be achieved.

As shown in Fig.2,the bulk votage of the differential input transistor M3has not driven by the drain voltage V MK D of the transistor MK.If the bulk votage of the differential input transistor M3is driven by the drain voltage V MK D of the transistor MK,the threshold voltage of the transistor M3will low down when the supply voltage V DD moves from a low voltage to a high voltage.At the same V REF value,the drain current of the transistor M3will increase, and the error ampli?er output voltage V OA will move down which againsts our requirement to have the error ampli?er output voltage V OA tracks the supply voltage V DD.Moving down of the error ampli?er output voltage V OA will result in increasing of the output voltage V OUT and will worsen the line regulation of the LDO as well.

IV.S IMULATION R ESULTS

The simulation of LDO with the proposed circuit adapted is done with the following conditions.The feedback

re-

Fig.4.Improvement of PSRR

Characteristic.

Fig.5.Frequency Characteristic.

sistances are set to R1=R2=1.5[MΩ],the reference volt-age V REF=0.6[V],and the output voltage V OUT=1.2[V]. The supply voltage V DD is set to V OUT+1[V]with the ripple voltage V rip=200[mV].The load current is as-sumed as ILOAD=50[mA]and the input-output de-coupling capacitor are CIN=COUT=1[μF](ESR=0[Ω]).And, the size of each element in the proposed circuit are de-signed as RK=250[KΩ],CK=8.2[pF],W MK=59[μm],and L MK=4[μm].

Fig.3shows the line regulation of the LDO when the supply voltage V DD changes from1.2[V]to3.3[V].With the effect of the proposed circuit,a75%improvement of the line regulation was con?rmed.The improvement of the line regulation gave the high PSRR at a low frequency region.Fig. 4shows the improvement of PSRR characteristic,in which, curves(1)and(2)show the PSRR characteristic when the bias current of the error ampli?er is set to18[μA]and to1/10 of the conventional one which is1.8[μA].The deterioration of the PSRR of about10[dB]at1[KHz]frequency was

con?rmed.However,the PSRR of the LDO after adapted with the proposed circuit was much more improved as can be seen in the curve(3)of Fig.4.At DC and a low frequency(10[Hz]), the PSRR was40[dB]improved.From the same curve,the PSRR at a moderate frequency(1[KHz])was also20[dB] improved even thought the bias current was kept to1/10of the conventional one.

In addition,the deterioration of the bandwidth of the error ampli?er by lowering its bias current is shown curves(1)and (3)in Fig.5.The immutability of the frequency characteristic after adapted the proposed circuit is shown in curves(2)and (4)of Fig.5.As a result,the proposed circuit provides only the improvement of the PSRR characteristic but without giving any bad in?uences to the stability of the LDO.Furthermore, the consumption current of the error ampli?er is only1.8[μA] and the proposed circuit is only about0.05[μA].

V.C ONCLUSION

The bulk gate-controlled circuit for the low-dropout voltage regulator(LDO)to improve the PSRR characteristic has been described.From the simulation results,it was con?rmed that the low power LDO can be achieved with a high PSRR characteristic.Also,about40[dB]at10[Hz]frequency and 20[dB]at1[kHz]frequency of PSRR are together improved while the consumption current of the error ampli?er is only 1.8[μA],and is about0.05[μA]for the proposed circuit.The proposed circuit can be built up with only few elements which is the merit of LSI design and implementation.

R EFERENCES

[1]V.Gupta,G.A.Rincon-Mora and P.Raha,“Analysis and Design of

Monolithic,High PSR,Linear Regulators for SoC Applications”,IEEE International SOC Conference,pp.311-315,Sep.2004.

[2]M.S.J.Steyart and W.MN.C.Sansen,”Power supply rejection ratio in

operational transconductance ampli?ers”,IEEE Trans.Circuits Syst., vol.37,pp.1077-1084,1990.

[3]S.K.Hoon,S.Chen,F.Maloberti,J.Chen and B.Aravind,“A Low

Noise,High Power Supply Rejection Low Dropout Regulator for Wireless System-on-Chip,”IEEE2005Custom Integrated Circuits Conference,pp.

759-762,Sep.2005.