降压PFC
UCC29910A
https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011
降压PFC控制器
查询样品:UCC29910A
特性说明
?降压功率因数校正用于在整个线路输入电压范围内对于需要高功率因数(>0.9)并希望满足IEC 实现高效率61000-3-2规范要求的设计人员，UCC29910A降压功?低离线启动电流，并采用了旨在实现快速启动及软率因数校正(PFC)控制器在通用线路输入电压范围内起动的SmartStart算法。提供了相对平坦的高效性能。固有的浪涌电流限制功?可兼容依靠AC线路的阻性或传输晶体管馈电型启能基于一种降压拓扑，可免除增设额外组件的需要。
动方式
凭借84V的典型总线电压，该拓扑非常适用于低电压?针对待机和轻负载条件的低功耗SmartBurst模式应力下游稳压/隔离功率链路，例如：受控于
?用于PFC控制及过流保护的电流检测输入UCC29900的半桥段，（德州仪器文献编
?线路检测欠压闭锁(UVLO)号：SLUS923).这种组合所产生的共模噪声很低，从?用于外部启动耗尽型FET的检测及驱动控制而降低了滤波要求并实现了异常高的转换效率。
?闭锁故障输入引脚
UCC29910A拥有AC线路欠压闭锁(UVLO)及旨在实应用
现快速启动的受控软起动功能。通过运用旨在实现同
类最佳之无负载及轻负载性能的高级电源管理算法，提?高效率AC-DC适配器
升了轻负载效率。
?扁平和高密度适配器
简化的应用示意图Array
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
UCC29910A
ZHCS258A–MAY2011–REVISED https://www.wendangku.net/doc/3618600854.html, 这些装置包含有限的内置ESD保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。
订购信息
器件型号封装PACKING
UCC29910APW Plastic,14-Pin TSSOP(PW)90-Pc.Tube
UCC29910APWR Plastic,14-Pin TSSOP(PW)2000-Pc.卷带封装
最大绝对额定值
超过自然通风条件下的工作温度范围（除非另有说明）(1)(2)(3)
数值单位
4.1
V DD电源电压
-0.3V Voltage:All pins?0.3to VDD+0.3
T A Operating free air temperature,(4)
?40to105
T J Operational junction temperature,(4)
°C T STG Storage temperature(4)?40to105
Lead temperature(10seconds)260
(1)These are stress limits.Stress beyond these limits may cause permanent damage to the device.Functional operation of the device at
these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied.Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
(2)All voltages are with respect to VSS.
(3)All currents are positive into the terminal,negative out of the terminal.
(4)Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
THERMAL INFORMATION
UCC29910A
THERMAL METRIC(1)TSSOP(PW)UNITS
14PINS
θJA Junction-to-ambient thermal resistance(2)101.5
θJCtop Junction-to-case(top)thermal resistance(3)48.9
θJB Junction-to-board thermal resistance(4)43.9°C/W
ψJT Junction-to-top characterization parameter(5) 1.2
ψJB Junction-to-board characterization parameter(6)43.3
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific
JEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011
建议的应用条件
over operating free-air temperature range,all the voltages refer to the VSS pin(unless otherwise noted)
最小值标称值最大值单位
T A Operating free air temperature?40105°C VDD Input Voltage 3.0 3.6
V All Inputs0VDD
电气特性
超过自然通风条件下的工作温度范围（除非另有说明）
参数测试条件最小值典型值最大值单位Supply Current
I VDD Operating current V DD=3.3V58mA Voltage Monitoring(1)
V NM VBULK nominal Normal mode(2)PFCDRV=100kHz 1.042 1.048 1.054V
V BH VLINESNS start-up VB(min) V BL VLINESNS brownout Normal mode(2)243249255mVRMS V LM VLINESNS max Normal mode(2)925931937 V B(max VBIASSNS max VLINESNS>V BH907913919 )mV V B(min)VBIASSNS min VLINESNS>V BH451457463 FAULT Input t f Latch Time(3)Normal mode(2),FAULT pin goes<0.8V100μs Positive going input threshold V IT+ 1.45 2.5 voltage Negative going input threshold V IT-0.8 1.85V voltage Input voltage hysteresis VIT+- V HYS0.31 VIT- PFCDRV section f SW开关频率Normal mode(2)94100106kHz At PFCDRV pin,normal mode(2),VLINESNS=V BH, D最大值Max duty cycle89%90%91% VBULK=1.025V VDD- I O=-1.5mA VDD 0.25V High level output voltage at V OH PFCDRV pin VDD- I O=-6mA VDD V 0.6V I O=1.5mA00.25 Low Level Output Voltage at V OL PFCDRV pin I =6mA00.6 O BIASCTRL Output Low level output voltage at Start-up mode(4),VBIASSNS increasing and< V BC00.25 BIASCTRL pin V B(max),I O=1.5mA V High level output voltage at Start-up mode(4),VBIASSNS decreasing and>VDD- VDD BIASCTRL pin V B(min),I O=-1.5mA0.25V (1)VBULK,VLINESNS and VBIASSNS voltage thresholds are based on VREFIN=1.500V.These will change proportionally as VREFIN changes.Input bias current at these pins is±50nA max. (2)Normal mode entered when VDD present,V REFIN=1.500V,VLINESNS increased from0to V BH increased from0to V B(max) (3)FAULT inputs shorter than t f cause a non-latched shutdown.FAULT inputs longer than t f cause a latched shutdown. (4)Start-up mode entered when VDD present,VLINESNS increased from0to V BH V B(max) VDD VSS VBULK CS LINESNS CS REFIN NC FAULT BIASSNS TST NC BIASCTRL PFCDRV UCC29910A ZHCS258A –MAY 2011–REVISED JUNE https://www.wendangku.net/doc/3618600854.html, 器件信息 终端功能 终端 I/O 说明名称 编号Provides power to the device;should be decoupled with ceramic capacitor (1μF),connected VDD 1-directly across pins 1-14.VBULK 2I Voltage sensing of the bulk capacitor.CS 3I Current sense input for PFC stage.LINESNS 4I Rectified AC line sense input.CS 5I Current sense input for PFC stage.REFIN 6I Reference input for internal comparators/error amplifier.NC 7-NC,this pin is not used,and should be left open.故障 8I Fault input for over-voltage or over-load protection.BIASSNS 9I Sense input for the bias rail for startup control.TST 10I This pin should be connected directly to VDD.NC 11-No connection should be made to this pin.BIASCTRL 12O Control output for the external startup FET for startup control.PFCDRV 13O Drive for PFC FET.VSS 14-Ground for internal circuitry. UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 Detailed Pin Description Pin1–VDD:This pin supplies power to the device.A minimum supply voltage level of3.0V and maximum of 3.6V is recommended. Pin2–VBULK:The output voltage level,V BULK is sensed on this pin.The HV bulk sensing network should be scaled so that the desired output voltage produces V NM at this pin.The Thevenin impedance at this pin should be below20kΩ,with appropriate capacitance provided for noise filtering. 注 The V BULK scaling and LINESNS scaling must maintain a ratio of close to4:1to ensure optimum operation of the SmartStart algorithm. Pin3–CS:This pin senses the current in the PFC stage.Both CS pins must be connected to the current sense signal and it is not permissible to leave one floating.The CS pins are intended to sense average low side PFC FET current directly.A150-mΩcurrent sense resistor value is optimal for powers of90W,with appropriate scaling for higher power levels.The recommended feed impedance level is approximately100Ω,and a capacitor of1μF is also recommended to act as a filter on the input current and to minimise noise pickup.A smaller value capacitor may result in possible current loop instability.A larger cap value may result in poor Power Factor(PF) due to excessive current signal phase shift.UCC29910A does not provide cycle-by-cycle inductor current limiting.An external circuit is needed if this type of protection is required. Pin4–LINESNS:This pin senses the rectified line voltage.The internal reference for this pin is internally scaled to?of the VBULK reference. 注 The LINESNS scaling and VBULK scaling must maintain a ratio of close to1:4to ensure optimum operation of the SmartStart algorithm. A peak of high-line voltage(typically373-V for264-VAC input)should be scaled to correspond to1.158V DC at this pin.A pin feed impedance of less than20kΩis recommended along with a filter capacitor of at least2.2nF for noise filtering.The RMS voltage at this pin must be greater than VBH before PFCDRV can start switching. The PFCDRV will go low if the RMS voltage drops below the brownout level V BL(21ms timeout).The controller will not start if VLINESNS exceeds VLM,(VBULK=0V). Pin5–CS:See pin3description above.This pin senses the current in the PFC stage,pins3and5must be connected together. Pin6–REFIN:This pin must be connected to an external accurate1.500V reference source,https://www.wendangku.net/doc/3618600854.html,ing a suitable shunt regulator with voltage setting resistors such as TLVH431A.The reference voltage must be established within100ms after VDD reaches3.0V. Pin7–NC:This pin is not used,and should be left open. VSS PFCDRV CS FAULT VDD CS VBULK BIASSNS BIASCTRL NC REFIN LINESNS TST NC UCC29910A ZHCS258A –MAY 2011–REVISED JUNE https://www.wendangku.net/doc/3618600854.html, Pin 8–FAULT:This pin when pulled low causes PFCDRV and BIASCTRL to go low,typically within 10us.After a 100us delay the FAULT input is sampled again.If the FAULT has cleared high,the UCC29910A goes into SmartStart mode.If the FAULT input is still low the device enters a latched shutdown state. Pin 9–BIASSNS:This pin is used to sense the PFC stage bias rail (normally in the 8V to 12V range to drive the PFC power MOSFET)during start-up to allow control of the external start-up FET.The voltage at this pin must be greater than V B(max)before PFCDRV switching commences.If the voltage drops below V B(min)the BIASCTRL output goes low,which can enable an external start-up FET. Pin 10–TST:This pin provides no user function.It must be connected to VDD. Pin 11–NC:This pin is for internal use only,and must be normally left open. Pin 12–BIASCTRL:This pin allows control of an external start-up FET. Pin 13–PFCDRV:This pin is used to drive the low-side PFC FET indirectly.This pin should be connected to a level-shifting gate driver to provide the required drive signal amplitude for typical high voltage power FETs.For this drive signal,D 最大值is limited to 90%duty cycle. Pin 14–VSS:This pin is the common ground connection for the device. UCC29910A Functional Block Diagram UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 应用信息 The UCC29910A controls a Buck PFC stage and is particularly suited to AC/DC applications in the power range from65W to130W.A fully characterised reference design using the UCC29910A PFC controller and the UCC29900Integral Cycle Controller is available on request.The design is for a90W PSU intended for laptop adapter applications.It comprises a Buck PFC front end using the UCC29910A to convert line power to a nominal84VDC.A UCC29900controls the conversion of this bulk voltage to a nominal19.25V output using a half bridge output power stage.The paragraphs following give some details on how the UCC29910A has been used in this application.Additional guidelines for both the UCC29910A and UCC29900are available on request. POR A Power On Reset function operates at turn-on. Start Up Bias Control This block controls the BIASCTRL output which may be used to control an external depletion mode start-up FET during the start-up phase and also while the UCC29910A is operating in SmartBurst Light Load mode(explained below).After POR the BIASCTRL output is held low until the voltage at the BIASSNS pin reaches V B(max)at which point BIASCTRL is driven high which turns the external FET off and the start-up phase is initiated.The UCC29910A continues to monitor the voltage at the BIASSNS pin and if it drops below V B(min)BIASCTRL goes low again,turning the start-up FET on again.At the end of the start-up phase the UCC29910A enters normal mode operation and BIASCTRL pin is held high.In normal mode,auxiliary windings maintain the V CCA rail(see 图5).When the UCC29910A is operating in SmartBurst light-load mode there is a possibility that these auxiliary windings can no longer supply enough current to support the bias supply within acceptable limits.The start-up bias control block prevents the bias rail from collapsing by setting the BIASCTRL pin low if VBIASSNS drops below V B(min).This signal may be used to turn on the external start-up FET on,thereby supplying added current to the bias rail.If VBIASSNS increases above V BLO(495mV approx.)BIASCTRL is set low again.The bias rail is therefore controlled between acceptable limits. Brown_Out Detection and Filter,Latch Reset Detect If the RMS voltage at the LINESNS pin drops below V BL for more than21ms(approx)the controller latches off. In this condition,the PFCDRV pin is low.The UCC29910A recovers from this state if the RMS voltage at the LINESNS pin falls below the reset level(V RS=218-mV RMS)for at least120ms and then increases to at least V BH.When this happens the UCC29910A enters its start-up mode after a10-s timeout.Power cycling is not needed for recovery after a brown_out event. Smart Start,Soft Start,Burst Control This module controls the gate control logic during the start-up phase. 振荡器 The internal oscillator runs at a fixed100kHz. UCC29910A ZHCS258A–MAY2011–REVISED https://www.wendangku.net/doc/3618600854.html, Control system The UCC29910A uses an average current mode control loop to regulate the output voltage,this eliminates the need for slope compensation.The two inputs to this control loop are the voltages at the VBULK and CS(Current Sense)pins. Voltage Loop–PI Error Amp The output of the PI(Proportional Integral)Error Amplifier is proportional to the difference between the voltages at the VBULK pin and the REFIN pins.The integral term in the amplifier drives the steady state error to zero but, in common with virtually all PFC controllers the control loop bandwidth is very low–approximately10Hz in this case. Current Sense The CS pins allow the UCC29910A to sense the average current in the power stage.The current sense signal is subtracted from the demand signal from the error amplifier and the result is used to set the PFCDRV duty cycle. PWM Generator The PWM Generator generates a duty cycle signal which is fed into the gate control logic.The duty cycle commanded is proportional to the demand signal from the control loop. Light Load Detect/Burst Mode Control As the load on the power stage decreases the standing losses due to,for example,the drive power needed to effect switching of the main power MOSFET,becomes an increasingly important proportion of the whole.The UCC29910A includes a SmartBurst light-load mode which significantly reduces these standing losses.In Normal Mode operation the UCC29910A continuously switches the power MOSFET,in light load the power MOSFET is switched in a burst mode.Power losses are reduced very significantly between bursts because there is no switching activity in the power train.During the burst,the power train is efficiently operated at close to full power. The average power transferred from input to output is controlled by modulating the interval between bursts. Gate Control Logic The Gate Control Logic block takes the inputs from a number of sources and outputs the PFCDRV signal. The fault latch output disables the gate control logic and sets the PFCDRV to low. The BULK OV clamp forces the PFCDRV output low if the voltage at the VBULK pin exceeds107%of V NM. The Start-up burst signal determines the PFCDRV on and off times during the start-up phase before the PWM generator becomes active. The PFC duty cycle signal sets the PFCDRV output duty cycle demand in normal mode.A line dependent D最小值and a90%D最大值limit are applied. The light load detect burst mode control block controls operation during light load mode and entry to and exit from this mode. UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 BULK OV Clamp The low bandwidth of the normal control loop prevents it from controlling an increase in VBULK due for example, to a large step reduction in the load on the VBULK output.This clamp activates within120μs if the voltage at the VBULK pin exceeds107%of V NM.When activated,it blanks the gate control logic output and the PFCDRV pin is held low.This clamp is non-latching so it releases once VBULK falls below trip level,i.e.,107%of VNM.For a short duration BULK OV clamp event,recovery will be back to the operating mode in place at the beginning of the event(usually normal mode).If VBULK stays above the clamp level for long enough,the conditions for entry into light load mode may be satisfied and recovery will be into light load mode. 参考书籍 All of the measurement functions within the UCC29910A use the REFIN pin for their reference voltage,these include(V NM，V BH，V BL，V LM，V B(max)，V B(min)和V CS).The specifications are written on the assumption that the reference voltage is1.500V and variations in this will proportionally affect the accuracy of measurements.The REFIN pin should be bypassed to V SS to reduce noise.A100-nF capacitor connected between pin6and pin14 is recommended,this part should be placed as close as possible to the controller and connected with minimum length tracks. Fault Latch This latch is activated by pulling the FAULT pin to V SS.When activated the current PWM cycle is terminated, PFCDRV is held Low and BIASCTRL is set low.The controller enters SmartStart mode if the FAULT input clears high in less than t f(100μs).If the FAULT input persists for longer than t f the controller enters a latched shutdown mode The latched state is cleared if the LINESNS pin is held below215mV RMS for120ms.The controller will re-start after a10-s delay,providing LINESNS has recovered to at least V BH.Alternatively cycling chip power off then on will also clear the latched state.Connecting a1-nF capacitor between the FAULT pin and VSS is recommended to reduce the risk of nuisance tripping. PFC Drive A power MOSFET driver,such as an NPN and PNP transistor or a UCC27324will normally be required to convert the PFCDRV output from the UCC29910A to the current and voltage levels typically needed to ensure correct power MOSFET operation. -V PRI HV UCC29910A ZHCS258A –MAY 2011–REVISED JUNE https://www.wendangku.net/doc/3618600854.html, Buck PFC Power Stage The PFC stage converts the incoming rectified line voltage to a DC voltage on the output capacitors,power transfer happening during the times when the line voltage is greater than the output voltage.The resulting conduction angle is a function of both the incoming line and output voltages.In the reference design mentioned above,the output voltage is set to 84VDC.This is low enough to allow conduction angles sufficient to achieve a PF (Power Factor)of at least 0.9over an input voltage range from 90VAC to 264VAC.Other output voltage levels may be set by altering the voltage sensing network at the VBULK pin.A 4:1ratio between the VBULK and LINESNS scaling ensures optimum operation of the SmartStart algorithm,so if the VBULK scaling is altered significantly,then the LINESNS scaling should be altered too.A high efficiency second stage,controlled by a UCC29900,can then down-convert to a nominal output of 19.25V using a transformer with a simple 4:1turns ratio,or to any other desired output voltage.The basic Buck PFC power stage is shown in 图1.This low-side switched buck stage has the same performance as the more usual high-side switched buck converter.It features easy power FET drive,at the expense of requiring output sense through a PNP level shift transistor,Q9.The incoming AC line is fed through a rectifier and filter stages,not shown here.The resulting unipolar voltage (V HV ) is then fed into the power stage.The MOSFET is switched at a constant 100kHz and the freewheeling diode function is provided by D1.The output voltage (V BULK )is developed across the two large capacitors,C2and C21. 图1.Buck Power Stage (simplified) 图2.Illustrative Line Current and Voltage UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 The buck converter operates off a rectified sinusoid and there are periodic dead times when the input voltage is lower than the output.During these times no power can be transferred to the output and the input current is nominally zero.图2shows the line current,I AC,falling to zero when V AC is less than V BULK.The associated conduction angle increases as the RMS line voltage increases and the current waveform changes from low line to high line.The input current is skewed a little towards the beginning of the conduction cycle because V BULK is at its lowest value at this time so conduction starts at a lower voltage than it finishes.This effect may be seen in 图3和图4.These waveforms are taken from a90-W buck PFC reference design,both meet the harmonics requirements set out in EN61000-3-2and their PF is greater than90%. 图3.115V,60Hz,Full Load,0.5A/div 图4.230V,50Hz,Full Load,0.5A/div UCC29910A ZHCS258A–MAY2011–REVISED https://www.wendangku.net/doc/3618600854.html, Start-Up With External FET Conventional start-up schemes utilising either resistive or enhancement mode MOSFET feeds incur line dependant static power losses.To avoid these power losses and to obtain an optimum turn-on time an external depletion mode FET may be used图5和图6.The V HV node is connected to the rectified incoming line.Q12is a depletion mode FET which will start charging C45as soon as line power is connected.Initially U1is inactive and BIASCTRL is low.The VDD_3V rail will begin to increase as U10starts to conduct.The POR(Power On Reset)sequence of U1will begin once this rail gets to about1.7V and will execute while the VDD_3V rail is being established.The BIASCTRL pin will go high when BIASSNS reaches the V B(max)级别上验证其电路。If VLINESNS is then>V BH,U1begins to pulse the PFCDRV pin,which starts the process of charging the bulk capacitors at the output of the buck PFC power stage.The PFCDRV current is drawn from C45,which starts to discharge.If the voltage at the BIASSNS pin falls below V B(min)then PFC switching is disabled and Q12is turned on to re-charge C45.With the given component values the V B(max)level corresponds to12V and a V B(min)level of 6V at the V CCA rail.The user sets the V B(max)和V B(min)levels depending on the characteristics of any alternative components used by adjusting R84. TLVH431ACDBZR UDG-11108 图5.Simplified Schematic UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 图6.Start-Up Sequence Waveforms(Ch1(Y),PFCDRV,Ch2(R),V CCA,Ch3(B),DUT V O) UCC29910A ZHCS258A–MAY2011–REVISED https://www.wendangku.net/doc/3618600854.html, SmartStart,V BULK Ramp-Up Once V CCA has reached12V and Q12has been turned off,and VLINESNS>V BH,the PFCDRV output of U1 becomes active and begins driving the main power MOSFET.The SmartStart algorithm increases V BULK,the voltage across C2and C21,as rapidly as possible.This is done by transferring the maximum amount of energy possible during each pulse set.The UCC29910A requires that the inductor has a Volt-sec product withstand rating of600Vμs.In fact any inductor suitable for application in a buck PFC stage will already meet this requirement in order to carry the full-load currents involved without saturating,therefore the Volt-sec rating will not result in any additional constraints on the inductor design.However it is more convenient to think in terms of applied Volt-sec product rather than the peak-inductor current. The UCC29910A’s SmartStart algorithm generates a series of pulses for the switching MOSFET which apply a constant Volt-sec product to the inductor during the on and off intervals.This ensures that the inductor current is ramped up as high as possible while the MOSFET is on and then decays to zero during the off time.In fact,T OFF is extended to110%of nominal which provides margin to ensure the inductor current ramps back to zero.The UCC29910A measures the instantaneous line voltage and the output voltage(V HV和V BULK输入图1).The voltage applied to the inductor when Q1is on is then found by subtracting these two values.It then calculates an appropriate T ON corresponding to a600V xμs product.T OFF is calculated in a similar fashion except that the inductor voltage during the off time is the voltage on the capacitors C2and C21(V BULK)plus the forward voltage drop in D1which is assumed to be0.6V.Inductor current is controlled on a cycle-by-cycle basis by constraining the T ON and T OFF values so that the inductor Volt-sec product is never exceeded.The initial T OFF intervals are typically 1.1ms long because the bulk capacitor voltage is still very low.As V BULK increases,the current ramp-down rate increases so that the required T OFF reduces,allowing the pulses to occur more frequently.In addition,as V BULK rises,the voltage across the PFC inductor during T ON will drop,so the on-time is adjusted to maintain a constant PFC inductor volt-secs product. During ramp-up the UCC29910A monitors the voltage at the BIASSNS pin and if it falls below V B(MIN)the ramp-up operation is terminated and the BIASCTRL pin goes low.In the reference design the minimum bias voltage will be approximately6V.When BIASCTRL goes low,Q12is turned on again and C45will begin charging back up towards12V.The ramp-up phase is then re-started.A maximum of10such restarts is allowed before the UCC29910A goes into a latched shutdown mode.Line power cycling is necessary for recovery from this mode. Typically,the capacitor voltage increases monotonically until the voltage at the VBULK pin reaches1.024V.This is slightly lower than V NM and in the circuit of图1corresponds to a V BULK across C2and C21of82V.The UCC29910A then switches to Normal Mode operation.This approach allows the fastest possible start-up time. In order to save standby power at no load,once the start-up phase is complete,and V BULK is being regulated (either by the normal mode voltage regulation loop,or the SmartBurst light-load mode),the BIASCTRL pin is driven high.This turns the start-up fet off which eliminates the power loss in the start-up current path.While in SmartBurst mode the voltage at the BIASSNS input is monitored.If the voltage at this pin drops below V B(min) then the start-up fet is turned back on to recharge the capacitors on the V CCA rail.In this way and with the component values shown,the V CCA rail is maintained above6V. UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A–MAY2011–REVISED JUNE2011 Normal Mode Operation In normal mode,the VBULK pin is controlled at V NM.Due to the slow voltage loop,and low gain at100/120Hz, the voltage loop PI error amp output will be essentially a fixed demand.If the power stage stays in Discontinuous Conduction Mode(DCM)throughout the half-cycle,then peak current will be proportional to(VHV-V BULK)over the half cycle and I AVG is approximately proportional to I PEAK.If the power stage transitions into Continuous Conduction Mode(CCM)during the line cycle,the current loop,responding to the average current,keeps the peak current flatter,so the line current doesn’t quite follow(V IN-V O)anymore but average line current is approx proportional to(VHV-V BULK)over the half-cycle.The overall effect is shown in the current waveforms in图3和图4. The line voltage is used by the control loop to set dynamic D最小值and D最大值values. Transient Response and V BULK Regulation When the UCC29910A is regulating in normal mode,the VBULK pin will be at V NM.An AC ripple at twice line frequency will be superimposed on this as the PFC stage drives current into the bulk capacitors.The amplitude of this ripple will be a function of line frequency,capacitance value and load current.Due to the necessary low control loop bandwidth V BULK will reduce in response to a step load increase.If the load step is large enough to cause the V BULK pin to reduce to less than0.992V the loop response is temporarily speeded up until this voltage has been increased back up to1.043V at which point the original loop response is restored. SmartBurst Mode(light load) As load current reduces the UCC29910A will continue to regulate the voltage at the VBULK pin at V NM.It will do this by reducing the PWMDRV waveform duty cycle,except that any pulses which are commanded to be less than D最小值will be masked and not delivered to the PWMDRV output.The proportion of cycles thus dropped is counted over a10-ms window and if it exceeds10%the UCC29910A changes its operating mode to SmartBurst mode. In SmartBurst mode the UCC29910A enters a low power consumption mode to minimize wasted power and improve light-load efficiency.Every1ms(approximately)it samples the voltages at the LINESNS and VBULK pins.If the voltage at VBULK is still within a target window of1.087V to1.074V no action is taken.The applied load will eventually cause the bus voltage to drop below this window and a burst of pulses are then output at the PFCDRV pin.These drive the PFC FET and thereby recharge the PFC bus capacitance.The most efficient transfer of power is achieved by minimizing the number of switching events,thus minimizing switching and gate drive losses.The line voltage sample is used to set the maximum safe duty cycle for the PFCDRV pulses while keeping the inductor current discontinuous,based on an inductor rating of600Vμs.The pulse duty cycle is ramped from D最小值to this maximum value.At the end of the burst,the pulse duty cycle is ramped back to D最小 值.Ramping the duty cycle in this manner avoids the sudden application of high power pulses to the power train which may cause excessive EMI and unwanted audio noise generation.A full SmartBurst pulse will last for2 ms–including the ramp-up time but excluding the ramp-down time. The SmartBurst pulse train is terminated if the voltage at the VBULK pin reaches the peak value of the allowed window,1.087V or if it exceeds2ms in length.There is a5-ms minimum time between the start of successive SmartBurst pulse trains. The max burst length and minimum burst repetition interval ensure that as load is increased,at some point the burst rate will become insufficient to maintain V BULK.Once the voltage falls below the normal mode setpoint V NM at the VBULK pin the controller reverts to normal regulation mode. ()2BULK PFC IN(pk )BULK SW IN(pk )IN(pk )V 1L V V 2f I V ??=-?÷?÷′′è?()()()IN(avg)START IN(pk)IN(pk)START START START P 1sin() I 1112V cos sin 422′p -q =′′′p -′q ′q ′ -′q ( ))2PFC 31L 160V 84V 94.9H 210010Hz 1.033A =-=m ′′′UCC29910A ZHCS258A –MAY 2011–REVISED JUNE https://www.wendangku.net/doc/3618600854.html, PFC Inductor Value The PFC inductor is designed for an inductance value that ensures DCM operation at high line (i.e.>160V AC ), right up to full-peak load.With an appropriate value of inductance,operation at low line should then result in CCM operation over most of the conduction angle at full load.The inductance required is given by: (1)where:(2) And πis the stage conversion efficiency,θSTART is the phase angle (in radians)at which conduction starts,where the instantaneous line voltage equals the bulk voltage.For a 100-W converter with an 84-V BULK DC output we evaluate the equation at 160V as follows. (3) Compared to the Boost PFC,much smaller values of PFC inductance can typically be used in the buck,because the voltage differential that needs to be supported across the inductor is lower.Practical inductance values that have been used in various designs have ranged from ~150μH at 50W,to ~80μH to 100μH at 90W to 130W. LOAD cond _%BUS 2BUS BUS(%)AC P C V V 2f ′q =′D ′′BUS 2900.570.965C 628F 840.12250′==m ′′′()HOLDUP LOAD BUS 2 2BUS(min)BUS(min_reg)T 2P C V V ′′=-()() BUS 22900.00320.965C 381F 840.9570′′==m ′-UCC29910A https://www.wendangku.net/doc/3618600854.html, ZHCS258A –MAY 2011–REVISED JUNE 2011 Bulk Capacitor Choice The value of bulk capacitance required is dictated by requirements on the allowable ripple voltage and hold-up time.In applications where hold-up time is not the main factor,then the capacitors should be sized for approximately 12%peak-to-peak ripple as follows: (4) For a typical 90-W adapter using buck PFC,the required bus capacitance for ±6%maximum ripple at 90VAC/50 Hz (12%total ripple)and at 84VDC bus,assuming 96.5%efficiency of the second stage,would be: (5) where: ?P LOAD :load power drawn (usually by the second regulation/isolation stage) ?C BUS :bus capacitance ?θCOND_%:conduction angle at AC line of interest (as decimal percentage of total cycle,e.g.50%conduction angle expressed as 0.5) ?f AC :AC line frequency The capacitance required to achieve a specific hold up time may be calculated as follows: (6) For example,in order to achieve 3-ms holdup,with nominal bus voltage of 84VDC,±5%maximum bus ripple, and 70-VDC minimum bus regulation level for the second stage,the required bus capacitance would be calculated as follows for a 90-W load,assuming 96.5%second stage efficiency: (7) 参考 1.2009/10Power Supply Design Seminar -SEM1900Topic 4,Power Factor Correction Using the Buck Topology –Efficiency Benefits and Practical Design Considerations 修订历史记录 Changes from Original (May 2011)to Revision A Page ? Added 新说明........................................................................................................................................................................1? Added an updated description for the TST pin.....................................................................................................................4? Added an updated description for the TST pin.....................................................................................................................6?Changed UCC29910A Functional Block Diagram . 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant UCC29910APWR TSSOP PW 142000 330.012.4 6.9 5.6 1.68.012.0Q1 LTC3780高频率同步四开关升降压式控制器 LTC3780是一个高性能升降压开关调整器的控制IC。其工作时输出电压可以高于，低于或等于输入电压。采用恒定频率，电流型方式实现。工作频率锁定在400KHZ，输入电压从4V-30V，最高可达36V。输入电压输出电压范围在工作模型间无缝对接。因此LTC3780是汽车、通讯及电池系统中理想的控制IC。 控制器的工作模型取决于FCB端子状态，对于升压式工作，FCB端选作跳跃式工作，断续式工作及强制连续型工作，而在降压式工作时，FCB端选作总量跨越周期式，断续型或强制连续型、跳跃式和跨越周期式工作，给出高转换效率（轻载时），而强制连续型及断续型则工作在恒定频率之下。 故障保护由输出过压比较器及内部折返电流限制给出。还有一个POWER GOOD输出端在输出达到设定值的±7.5%以内时给出指示。 该IC共24PIN引脚，各脚功能如下： ①PGOOD（pin1）开路漏极逻辑电平输出PGOOD，在输出电压未达到±7.5%以内时，会 拉到GND电平。 ②SS（pin2）软起动，减少输入功率源浪涌电流，推荐接6.8nf的电容。 ③SENSE+（pin3）输入电流检测及反转电流检测比较器。I TH端电压并加入SENSE-及 SENSE+之间的失调。它用于设置电流纹波阈值。 ④SENSE-（pin4）同上 ⑤I TH（pin5）电流控制阈值及误差放大器补偿点。电流比较器阈值随控制电压增加，电压 范围从0V—2.4V。 ⑥V OSENSE（pin6）误差放大器反馈输入端，该端接到误差放大器输入至外电阻分压器，此 分压器从输出电压处取得。 ⑦SGND信号地，所有小信号补偿元件等都接此处，然后再去接功率地。 ⑧RUN（pin8）Run控制输入，强制Run端在1.5V以下，IC将关断开关调整器电路，这 里有一个100K电阻放在Run和SGND之间，此端电压不得超过6V。 ⑨FCB（pin9）强制连续型工作控制端，此端电压低于0.8V为连续电流型工作，浮动时为 跨越式升压或跳跃周期降压式工作，将其接INTVcc，则为恒频断续型工作。 ⑩PLLFLTR（pin10）锁相环低通滤波器，此端可分别用AC或DC电压源驱动，以改变内部振荡器频率。 ?PLLIN（pin11）外同步输入 ?STBYMD（pin12）LDO控制端 ?BOOST2（pin13）BOOST1（PIN24）升压浮动驱动电源端 ?TG2（pin14）TG1（pin15）顶部MOS栅驱动。 ?SW1（pin15）SW2（pin17）两开关结点端 ?BG2（pin16）BG1（pin18）两底部MOS栅驱动 ?PGND（pin17）此端与两底部功率MOS的源尽量近地接在一起。 ?INTVcc（pin19）内部6V稳压器输出，它用于驱动控制电路，要至少加4.7uf电容去耦合。 ?EXTVcc（pin20）外部Vcc的输入端，当EXTVcc超过5.7V时，内部开关接到INTVcc 并关断内部Vcc。 ?Vin（pin21）主输入电源的正电压端，同一RC滤波器接至GND EXPOSED PAD 接后SGND 并接PCB的地。 ○21EXPOSED PAD 接至SGND，并接PCB的地。 ＰＦＣ开关电源功率因数校正原理 ＰＦＣ开关电源功率因数校正原理 一、什么是功率因数补偿，什么是功率因数校正： 功率因数的定义为有功功率与视在功率的比值． 功率因素补偿:这项技术主要是针对因具有感性负载的交流用电器具的电压和电流不同相(图1)而引起的供电效率低下,提出的改进方法(由于感性负载的电流滞后所加电压,电压和电流的相位不同,使供电线路的负担加重,导致供电线路效率下降,这就要求在感性用电器具上并联一个性质相反的电抗元件.用以调整该用电器具的电压、电流相位特性.例如:当时要求所使用的40W日光灯必须并联一个4.75μF的电容器).用电容器并联在感性负载的两端,利用电容上电流超前电压的特性,用以补偿电感上电流滞后电压的特性,使总的特性接近于阻性,从而改善效率低下的方法叫做功率因数补偿(交流电的功率因数可以用电源电压与负载电流两者相位角的余弦函数值cosφ表示)。 图1 在具有感性负载中供电线路中电压和电流的波形 常规开关电源功率因数低是由于开关电源都是在整流后,用一个大容量的滤波电容使输出电压平滑,因此负载特性呈现容性.这就造成了交流220V在整流后,由于滤波电容的充、放电作用,在其两端的直流电压上出现略呈锯齿波的纹波.滤波电容上电压的最小值远非为零,与其最大值(纹波峰值)相差并不多. 图2 全波整流电压和AC输入电流波形 因为根据整流二极管的单向导电性,只有在AC线路电压瞬时值高于滤波电容上的电压时,整流二极管才会因正向偏置而导通,而当AC输入电压瞬时值低于滤波电容上的电压时,整流二极管因反向偏置而截止.也就是说,在AC线路电压的每个半周期内,只是在其峰值附近,二极管才会导通.虽然AC输入电压仍大体保持正弦波波形,但AC输入电流却呈高幅值的尖峰脉冲,如图2所示.这种严重失真的电流波形含有大量的谐波成份,引起线路功率因数严重下降. 在正半个周期内(180o),整流二极管的导通角大大小于180o,甚至只有30o～70o.由于要保证负载功率的要求,在极窄的导通角期间,会产生极大的导通电流,使供电电路中的供电电流呈脉冲状态.它不仅降低了供电的效率,更为严重的是,它在供电线路容量不足或电路负载较大时,会产生严重的交流电压波形畸变(图3),并产生多次谐波,从而干扰了其它用电器具的正常工作(这就是电磁干扰－EMI和电磁兼容－EMC问题)。 图3 正常供电电压波形和接入容性负载后电压波形畸变 二、怎样进行功率因数校正： 1、功率因数校正:(PFC) 我们目前使用的电视机,由于采用了高效的开关电源,而开关电源内部电源输入部分,无一例外的采用了二极管全波整流及滤波电路,如图4A所示,其电压和电流波形如图4B所示。 降压式DC/DC电路的MOS管选择 同步整流降压式DC/DC转换器都采用控制器和外接功率MOSFET的结构。控制器生产商会在数据资料中给出参数齐全的应用电路，但用户的使用条件经常与典型应用电路不同，要根据实际情况改变功率MOSFET的参数。 对功率MOSFET的要求 同步整流降压式DC/DC转换器的输入及输出部分电路如图1所示，它是由带驱动MOSFET的控制器及外接开关管(Q1)及同步整流管(Q2)等组成。目前，Q1和Q2都采用N沟道功率MOSFET，因为它们能满足DC/DC转换器在输入电压、开关频率、输出电流及减少损耗上的要求。 图1 同步整流降压式DC/DC转换器的输入及输出部分电路简图 开关管与同步整流管的工作条件不同，其损耗也不一样。开关管有传导损耗(或称导通损耗)和栅极驱动损耗(或称开关损耗)，而同步整流管只有传导损耗。 传导损耗是由MOSFET的导通电阻R DS(on)造成的，其损耗与i2D、R DS(on)及占空比大小有关，要减少传导损耗需要选用R DS(on)小的功率MOSFET。新型MOSFET的R DS(on)在V GS=10V时约 10mΩ左右，有一些新产品在V GS=10V时可做到R DS(on)约2～3mΩ。 栅极驱动损耗是在开关管导通及关断瞬间，在一定的栅源电压V GS下，对MOSFET的极间电容(如图2所示)进行充电(建立V GS电压，使MOSFET导通)和放电(让V GS=0，使MOSFET关断)造成的损耗。此损耗与MOSFET的输入电容C iss或反馈电容C rss、栅极驱动电压V GS及开关频率f sw成比例。要减小此损耗，就要选择C iss或C rss小、阈值电压V GS(th)低的功率MOSFET。 一、什么是PFC？ PFC是电脑电源中的一个非常重要的参数，全称是电脑功率因素，简称为PFC，等于“视在功率乘以功率因素”，即：功率因素=实际功率/视在功率 功率因素：功率因数表征着电脑电源输出有功功率的能力。 功率是能量的传输率的度量，在直流电路中它是电压V和电流A和乘积。在交流系统里则要复杂些：即有部分交流电流在负载里循环不传输电能，它称为电抗电流或谐波电流，它使视在功率( 电压Volt乘电流Amps)大于实际功率。视在功率和实际功率的不等引出了功率因素，功率因素等于实际功率与视在功率的比值。 视在功率：即交流电压和交流电流的乘积，用公式表示为：S=UI。 上式中，S是额定输出功率，单位是VA（伏安），U是额定输出电压，单位是V，如220V、380V等；I是额定输出电流，单位是A。视在功率包括两部分：有功功率（P）和无功功率（Q），有功功率是指直接做功的部分。比如使灯发亮，使电机转动，使电子电路工作等。因为这个功率做功后都变成了热量，可以直接被人们感觉到，所以有些人就产生一个错觉，即把有功功率当成了视在功率，孰不知有功功率只是视在 功率的一部分，用式表示：P=SCOS0θ=UICOSθ＝UI?F上式中，P是有功功率，单位是W（瓦），F=COSθ被称为功率因数，而θ是在非线性负载时电压电流不同相时的相位差。无功功率是储藏在电路中但不直接做功的那部分功率，用式表示：Q=Ssinθ=UIsinθ。上式中，Q为无功功率，单位是var（乏）。 对于计算机和其它一切靠直流电压工作的电子电路，离开无功功率是根本无法工作的。一般用户都认为计算机之类的设备只需要有功功率，而不需要无功功率。既然无功功率不做功，要它何用！于是他们当然就认为功率因数为１的电源最好。因为它能给出最大输出功率。然而，实际情况并非如此。假如有一台计算机，当交流市电输入后进行整流，就得到脉动直流电压，若不将脉动电压进行任何工，就直接提供给计算机电路，毫无疑问，电路根本无法正常工作。虽然这时计算机的功率因数接近于１，可这又有何用呢。为了让计算机电路能正常工作，必须向其提供平滑了的直流电压。这个“平滑”工作必须由接在计算机电源整流器后面的滤波电容器C来完成。这个滤波器就像一个水库，电容器里面必须储存足够数量的电荷，在整流半波之间的空白时，使电路上的工作电压仍不间断，能保持正常电平。换句话说，即使在两个脉动半波之间无输入电能时，UC的电压电平也无显著的变化，这个功能是靠电容器内的储能来实现的，储存在电容器内的这部分能量就是无功功率。所以说，计算机是靠无功功率的支持，才能保证电路正确运用有功功率实现正常运行的。 2MHz、DC 准确的同步降压型DC/DC 控制器 近日（2010 年11 月 3 日）–凌力尔特公司(Linear Technology Corporation) 推出高频控制接通时间的同步DC/DC 控制器LTC3833，该器件具有差分输出电压检测和时钟同步功能。通过在瞬态事件时提高工作频 率，受控的接通时间、谷值电流模式架构强制了一个非常快的瞬态响应，从 而允许LTC3833 仅在少数几个周期内就能从大的负载阶跃中恢复。其 4.5V 至38V 的输入电压范围涵盖种类繁多的应用，包括大多数中间总线电压应用。强大的内置N 沟道MOSFET 栅极驱动器允许使用大功率外部MOSFET，以在输出电压范围为0.6V 至 5.5V 的应用中实现高达25A 的大负载电流，从而非常适合用于满足负载点应用的需求。 LTC3833 的差分放大器对正和负端提供真正远端输出电压取样，从而可不 受走线、通孔及互连IR 损耗(高达±500mV)的影响，实现准确度很高的 调节。非常短的20ns 最短接通时间在高频工作时允许使用高降压比电源。 工作频率可在200kHz 至2MHz 范围内选择，或者可同步至一个外部时钟。通过检测输出电感器(DCR) 两端的压降来监视输出电流，以实现最高 效率，或通过使用一个检测电阻器来监视输出电流。其他特点包括一个内置 的偏压LDO、软启动或跟踪、可调电流限制、过压保护、折返电流限制以及 外部VCC 控制。 LTC3833 提供卓越的总差分调节准确度，而且规定补偿所有误差源，包括 电压、负载和差分检测。LTC3833 的总差分输出电压准确度在25°C时为±0.25%，在0oC至85oC时为±0.67%，而在-40°C至125°C的整个工作结温范围内为±1%。LTC3833 采用耐热增强型3mm x 4mm QFN-20 封装或 高压同步降压型DC/DC 控制器LT 凌力尔特公司(Linear Technology CorporaTIon) 推出高压同步降压型DC/DC 控制器LTC3891，该器件在备用模式时仅消耗50uA，而输出处于稳定状态。4V 至60V 的输入电源范围可保护该器件免受高压瞬态影响、在汽车冷车发动时连续工作、以及涵盖种类繁多的输入电源和多种电池化学组成。在输出电流高达20A、效率高达95% 的情况下，输出电压可在0.8V 至24V 的范围内设定，从而使该器件非常适用于12V、24V 或48V 汽车、重型设备、工业控制、机器人以及电信等应用。 ? LTC3891 具有强大的1.1Ω内置MOSFET 栅极驱动器。它以50kHz 至900kHz 的可选固定频率工作，并可用其锁相环(PLL) 同步至75kHz 至850kHz 的外部时钟。用户可在轻负载时选择连续、脉冲跳跃和低纹波突发模式(Burst Mode) 工作。其电流模式架构提供非常容易的环路补偿、快速瞬态响应和卓越的电压调节。输出电流检测通过测量输出电感器(DCR) 两端的压降来完成，以实现最高效率，或者利用一个可选检测电阻器来进行输出电流检测。电流折返限制MOSFET 在过载情况下产生的热量。其他特点包括了很短的95ns 最短接通时间以在高效率时实现高降压比、高达99% 的占空比以实现低压差输出、一个内部LDO 从输入电压或EXTVCC 向栅极驱动器供电、以及一个电源良好信号。本文来自电子发烧友网(elecfans ) ? LTC3891 采用20 引脚3mm x 4mm QFN 和20 引线TSSOP 耐热增强型封装。该器件有 3 种工作结温级版本，分别为-40 至125°C 的扩展和工业温度级版本、-40°C 至150°C 的高温汽车级版本、以及-55°C 至 降压控制器的使用 本文介绍了降压升压电源设计中降压控制器的使用。 电子电路通常都工作在正稳压输出电压下，而这些电压一般都是由降压稳压器来提供的。如果同时还需要负输出电压，那么在降压—升压拓扑中就可以配置相同的降压控制器。负输出电压降压—升压有时称之为负反向，其工作占空比为50%，可提供相当于输入电压但极性相反的输出电压。其可以随着输入电压的波动调节占空比，以“降压”或“升压”输出电压来维持稳压。 图1 显示了一款精简型降压—升压电路，以及电感上出现的开关电压。这样一来该电路与标准降压转换器的相似性就会顿时明朗起来。实际上，除了输出电压和接地相反以外，它和降压转换器完全一样。这种布局也可用于同步降压转换器。这就是与降压或同步降压转换器端相类似的地方，因为该电路的运行与降压转换器不同。 图1 降压—升压电感要求平衡其伏特-微秒乘积 FET 开关时出现在电感上的电压不同于降压转换器的电压。正如在降压转换器中一样，平衡伏特-微秒(V-μs) 乘积以防止电感饱和是非常必要的。当FET 为开启时（如图1 所示的ton 间隔），全部输入电压被施加至电感。这种电感“点”侧上的正电压会引起电流斜坡上升，这就带来电感的开启时间V-μs 乘积。FET 关闭(toff) 期间，电感的电压极性必须倒转以维持电流，从而拉动点侧为负极。电感电流斜坡下降，并流经负载和输出电容，再经二极管返回。电感关闭时V-μs 乘积必须等于开启时V-μs 乘积。由于Vin 和Vout 不变，因此很容易便可得出占空比(D) 的表达式：D=Vout/(Vout " Vin)。这种控制电路通过计算出正确的占空比来维持输出电压稳压。上述表达式和图1 所示波形均假设运行在连续导电模式下。 降压—升压电感必须工作在比输出负载电流更高的电流下。其被定义为IL = I 同步NVDC降压/升压电池充电控制器BQ25713的 解决方案 BQ25713/BQ25713B可通过USB适配器、高电压USB PD源和传统适配器等各种输入源为电池充电。此器件是一款同步NVDC降压/升压电池充电控制器，可为空间受限的1至4节电池充电应用提供所含元件数较少的高效解决方案。 通过NVDC配置，可将系统电压稳定在电池电压水平，但无法将其降至低于系统最低电压。即便在电池完全放电或被取出时，系统也仍会继续工作。当负载功率超过输入源额定值时，电池会进入补电模式并防止系统崩溃。 在加电期间，充电器基于输入源和电池状况，将转换器设置为降压、升压或降压/升压配置。充电器自动在降压、升压、降压/升压配置间转换，无需主机控制。 同步NVDC降压/升压电池充电控制器BQ25713的解决方案 在无输入源的情况下，BQ25713/BQ25713B 可支持适用于1到4节电池的USB On-the-Go（OTG）功能，从而在 VBUS上生成具有8mV分辨率的3V至20.8V可调电压。OTG输出电压压摆率是可配置的，这符合USB PD 3.0 PPS规范。 当仅通过电池为系统供电且 USB OTG端口未连接任何外部负载时，BQ25713/BQ25713B支持Vmin主动保护（VAP）特性，借助该特性，该器件会从电池向VBUS处充电，从而将部分能量存储在输入解耦电容器中。在系统峰值功率尖峰期间，大量电流从电池流出，导致从电池到系统的阻抗上出现较大压降。存储在输入电容器中的能量会为系统补电，从而防止系统电压下降到最低系统电压之下进而导致系统崩溃。该Vmin主动保护（VAP）特性旨在SOC高功率需求期间吸收系统功率峰值，Intel 强烈建议为具有1至2节电池的平台配备此特性。 BQ25713/BQ25713B会监控适配器电流、电池电流和系统功率。灵活编 4KW PFC 相关电容电感计算 1. 输入电容计算 参阅IR1153应用规格书2000W PFC 计算如下： 因为()()2L IN RMS MAX IN I sw IN RMS MIN I C k f r V π?=??? ，所以需要先求()IN RMS MAX I ，参阅IR1153应用 规格书2000W PFC 计算如下： 当P OUT =4000W 时，() ()400043480.92 O MAX IN MAX MIN P W P W η===； 因为一般需要对市电220VAC （﹣10%，+15%）变动范围内的PFC 运行情况进行确认是否存在异常，即198V~254VAC ，所以()198IN RMS MIN V V =。假设当PFC 在4000W 负载情况下运行功率因数cos φ为0.998，则： () ()()400022()0.921980.998 O MAX IN RMS MAX MIN IN RMS MIN P W I A V PF V η===??； ()()2231.1IN PEAK MAX IN RMS MAX I A A ===； 综上所述，高频输入电容计算如下所示： ()()2235% 3.12222.29%198L IN RMS MAX IN I sw IN RMS MIN I A C k uF f r V kHz V ππ?==?=??????； 所以一个标准的3.3uF 或者2.2uF ，630V 的聚酯（薄膜）电容可以选用。 2. 输出电容计算 参阅IR1153应用规格书2000W PFC 计算如下： 由计算公式：()22() 2O OUT MIN O O MIN P t C V V ???=- ，当P OUT =4000W 时，对于50Hz 的市电来讲， 20t ms ?=,380O V V =,()285O MIN V V =？,将各个参数代入得： ()2224000201601602533(380)(285)1444008122563175 OUT MIN W ms C uF V V ??====--，增加20%余量：() 25333166.25110.2 OUT MIN OUT TOL C uF C uF C ===-?-； 所以4个680uF /450V 的电容并联使用达2720uF 可以满足4000W PFC 的需要。 简述什么是PFC，PFC稳压开关电源是什么 PFC的英文全称为Power Factor CorrecTIon，意思是功率因数校正，功率因数指的是有效功率与总耗电量（视在功率）之间的关系，也就是有效功率除以总耗电量（视在功率）的比值。基本上功率因数可以衡量电力被有效利用的程度，当功率因数值越大，代表其电力利用率越高。 什么是PFC？PFC是电脑电源中的一个非常重要的参数，全称是电脑功率因素，简称为PFC，等于视在功率乘以功率因素，即：功率因素=实际功率/视在功率 功率因素：功率因数表征着电脑电源输出有功功率的能力。功率是能量的传输率的度量，在直流电路中它是电压V和电流A和乘积。在交流系统里则要复杂些：即有部分交流电流在负载里循环不传输电能，它称为电抗电流或谐波电流，它使视在功率（电压V olt乘电流Amps）大于实际功率。视在功率和实际功率的不等引出了功率因素，功率因素等于实际功率与视在功率的比值。 视在功率：即交流电压和交流电流的乘积，用公式表示为：S=UI。上式中，S是额定输出功率，单位是V A（伏安），U是额定输出电压，单位是V，如220V、380V等；I是额定输出电流，单位是A。视在功率包括两部分：有功功率（P）和无功功率（Q），有功功率是指直接做功的部分。比如使灯发亮，使电机转动，使电子电路工作等。因为这个功率做功后都变成了热量，可以直接被人们感觉到，所以有些人就产生一个错觉，即把有功功率当成了视在功率，孰不知有功功率只是视在功率的一部分，用式表示：P=SCOS0=UICOS ＝UIF上式中，P是有功功率，单位是W（瓦），F=COS 被称为功率因数，而是在非线性负载时电压电流不同相时的相位差。无功功率是储藏在电路中但不直接做功的那部分功率，用式表示：Q=Ssin=UIsin。上式中，Q为无功功率，单位是var（乏）。对于计算机和其它一切靠直流电压工作的电子电路，离开无功功率是根本无法工作的。一般用户都认为计算机之类的设备只需要有功功率，而不需要无功功率。既然无功功率不做功，要它何用！于是他们当然就认为功率因数为１的电源最好。因为它能给出最大输出功率。然而，实际情况并非如此。假如有一台计算机，当交流市电输入后进行整流，就得 论文题目：家用电器稳压电源 --PFC部分设计 学生姓名： 所在院系：机电学院 所学专业：应用电子技术教育 导师姓名： 完成时间：2009年5月20日 摘要 随着信息技术的普及推广，电力用户对电能质量的要求日益提高，其中最基本的一条是电压的稳定和较的高功率因数。设计了基于UC3854芯片的一种有源电路功率因数校正电路方案。本文介绍了有源功率因数校正电路（APFC）的工作原理、电路分类，着重分析了电路的选择和设计。该系统采用平均电流模型，它通过脉宽调制输出的一连串脉冲信号来控制电路中开关晶体管的导通与截止，从而将输入电流与输出电压的相位重新调整到同相的状态，最终达到稳压和功率因数校正的目的。 关键词：交流稳压，功率因数校正PFC，UC3854 Regulated power supply design of household appliances --PFC Circuit Design Abstract With the rapid increase of industry and domestic consumption of electric power, power quality began to attract more and more attention. One of the basic rule of power quality and high power factor the stability of voltage. design based on UC3854 chip an active circuit power factor correction circuit program.This article introduce the active power factor correction (APFC) working principle, classification of circuit. focused on an analysis of the selection and design of circuits.The circuit model using the average current through the series of PWM output pulse signal to control circuit switching transistor turn-on and cut-off, so that the output voltage and input current phase of re-adjusted to the same state, and ultimately achieve the pre-regulator and the purpose of power factor correction. Key words: The AC constant voltage, Power factor correction PFC,U C3854 PFC和PWM开关电源控制器 Micro Linear公司的8引脚封装功率因数校正（PFC）和脉冲宽度调制（PWM）电源控制器ML4803，为设计低输入电流谐波畸变的高品质开关电源（SMPS）提供一切所必需的功能，使其元件数量明显减少，成本降低。 根据IEC1000-3-2规范要求，SMPS必须采取谐波抑制措施。Bi-CMOS ML4803采用多项专利技术，将PFC与PWM控制器二合一集成到同一芯片上，并使二者同步化，把引脚由原先的至少16个减少到8个，成为目前引脚最少的PFC和PWM混合型IC。 ML4803采用先进的AC输入电流整形技术，内含平均电流（或峰值）升压型前沿P FC。ML4803的PFC控制器，由新发明的单引脚误差放大器、电流限制比较器、Vcc过压保护（OVP）比较器、欠压锁定（UVLO）电路、基准电压（VREF）、控制逻辑及驱动输出级电路等部分组成；ML4803的高效后沿电流型PWM控制器，主要包括PWM比较器、DC电流限制比较器与PFC公用的振荡器、控制逻辑及驱动输出级等电路。图1为ML4803的内部结构方框图。 ML4803-1的PFC与PWM控制器工作频率均为67kHz，而ML4802的PWM工作频率为PFC的2倍，即134kHz。ML4803的Vcc被箝位在17.5±0.8V，Vcc启动电流仅150μA，工作电流为2mA，欠压封锁门限为12±0.5V（滞后2.9±0.5V）。 ML4803的PFC控制器VEAO引脚为DC-DC升压变换器单引脚电压误差放大器输入，通过电压反馈环路强迫PFC输出调整到设定的DC电压值。当AC输入电压范围为85～256 V时，PFC升压变换器能输出恒定的±85V的DC电压。ISENSE引脚为电流感测输入，通过IC内电流限制比较器，迫使AC输入电流正比于AC输入电压的瞬时变化轨迹，保持正弦波波形，且与AC输入电压趋于同相位，因而可使系统功率因数达到0.99以上，几乎接近于1。PFC电路同时还执行峰值电流限制和过压保护功能，从而提高了系统的可靠性。 ML4803采用了Micro Linear公司的同步前沿/后沿（LETE）调制专利技术，可使PF C级输出纹波减小30%，从而可使用较小容量的电容，并能明显提高SMPS的效率。 ML4803可用作设计PCS、工作台、服务器和外部设备等高功率因数、低输入电流谐波失真的高品质SMPS。图2为用ML4803作为PFC与PWM控制器的典型应用电路。该S MPB适用于国际通用AC供电线路，AC输入电压范围从85V到270V，而无需选择开关。其输出功率为240W，DC输出电压是12V，线路功率因数高于0.99。 在图2中，置于桥式整流器BRI和电解电容C1之间的电感元件L2、开关Q2与Q5、升压二极管CR1及U1（ML4803）的PFC控制器等，组成有源PFC升压式预调整器。R3为电流感测电阻，其电流检测信号经R4和U1引脚3监控；PFC变换器的DC输出电压经R1 3、R12分压采样，通过U1引脚4监控，从而在AC输入端产生正弦电流波形，并在C1两端产生385V的DC输出电压。R24、R26、C11和R31等为U1的Vcc启动元件。当PFC 电路运行之后，L2的次级绕组则感生高频电压，并经CR8，CR15整流和C9、C21、C11等滤波，输出DC电压加至U1引脚Vcc，为U1提供工作电压和电流。U1引脚1输出驱动PF 开关电源功率因素校正（PFC）及其工作原理 郝铭 什么是功率因数补偿，什么是功率因数校正： 功率因数补偿：在上世纪五十年代，已经针对具有感性负载的交流用电器具的电压和电流不同相（图1）从而引起的供电效率低下提出了改进方法（由于感性负载的电流滞后所加电压，由于电压和电流的相位不同使供电线路的负担加重导致供电线路效率下降，这就要求在感性用电器具上并联一个电容器用以调整其该用电器具的电压、电流相位特性，例如：当时要求所使用的40W日光灯必须并联一个4.75μF的电容器）。用电容器并连在感性负载，利用其电容上电流超前电压的特性用以补偿电感上电流滞后电压的特性来使总的特性接近于阻性，从而改善效率低下的方法叫功率因数补偿（交流电的功率因数可以用电源电压与负载电流两者相位角的余弦函数值cosφ表示）。 图1 在具有感性负载中供电线路中电压和电流的波形 而在上世纪80年代起，用电器具大量的采用效率高的开关电源，由于开关电源都是在整流后用一个大容量的滤波电容，使该用电器具的负载特性呈现容性，这就造成了交流220V在对该用电器具供电时，由于滤波电容的充、放电作用，在其两端的直流电压出现略呈锯齿波的纹波。滤波电容上电压的最小值远非为零，与其最大值(纹波峰值)相差并不多。根据整流二极管的单向导电性，只有在AC 线路电压瞬时值高于滤波电容上的电压时，整流二极管才会因正向偏置而导通，而当AC输入电压瞬时值低于滤波电容上的电压时，整流二极管因反向偏置而截止。也就是说，在AC线路电压的每个半周期内，只是在其峰值附近，二极管才会导通。虽然AC输入电压仍大体保持正弦波波形，但AC输入电流却呈高幅值的尖峰脉冲，如图2所示。这种严重失真的电流波形含有大量的谐波成份，引起线路功率因数严重下降。 3C认证与电源PFC 最近需要用到220V转12V/10A的电源板，需要放置到产品里面，了解到这个如果产品要过3C认证的话，需要用到PFC电路，而用不用PFC电路是对成本有影响的。网上找到一个TI的关于PFC的介绍，觉得不错，总结如下。 什么是PFC？ PFC的英文全称为“Power Factor Correction”，意思是“功率因数校正”，功率因数指的是有效功率与总耗电量（视在功率）之间的关系，也就是有效功率除以总耗电量（视在功率）的比值。基本上功率因数可以衡量电力被有效利用的程度，当功率因数值越大，代表其电力利用率越高。 主动PFC的功率因数大概都在0.90以上，被动PFC在0.70-0.80，无PFC是0.5-0.6左右 什么时候需要用到PFC？ 3C要求电源输入功率大于75瓦要测谐波电流.对PFC没有强制要求,但大功率电源前极不加PFC,谐波电流很难通过。 为什么要用PFC？ 抑制高次谐波 输出稳压调压 AC-DC电路，其实从我们在上图这个电路里面可以看出，电网进来的是50Hz或60Hz 的交流电，就是直接把它整流滤波成直流就好。 如上图，二极管整流桥之后接了一个电容，右图红色的正弦波为电网进来的电压波形Vac，黑色的Vc为电容两端的电压，红色Iac为电网的输入电流，为什么是锯齿状的呢？ AC输入的电源电压的时候，低于输出Vc 这个电压，实际上是没有电流往里面流的，等到这个电压开始超越后面电压的时候，通过这个二极管，就是直接给电容器大电流的灌封，所以电流瞬间就提升到很高，那么直接就灌进去了，灌进去之后随着电压继续往上涨，这个电容充电电压往上拉的时候，电流就会往下降了，那么达到最高电压点的时候，正弦波最高电压点等于充电充满了，那么下来就掉下来就没有电流了，所以必然会形成一个类似这样的三角形的锯齿波这样的东西。 对于电源适配器后级使用者来说，这个三角形的锯齿波其实并没什么影响，那为什么要加这个PFC电路呢？ 率 PFC 计 Design of active high power PFC 1. PFC 电感(L)计算公式 1.1电路形式及输入数椐 C的基本电路形式如图1，并定义电感输入端电压为Vi ，电感输出电压为 VOUT 或记为V0。 假定：1/ PFC输出功率POUT＝2200 w 2/ MOC管开关频率FSW＝50Khz 3/ PFC电感输出电压VOUT=380V 并简称Vo 4/ PFC 电感最小输入电压VIN(mim)＝90V (有效值) 5/ PFC 电感最大输入电压为VIN(max)＝260V(有效值) 6/ 最大温升50℃ 7/ 电感效率为η1 =99% 8/ 整个调节装置效率为η2 =95% 1.2 PFC 电感L及输入电流Iin的计算公式 1.2.1电感基本表达式 根据电磁感应定律 VL=L×di/dt，当S导通时Vi=VL=Ldi/dt， L=Vi×dt/di (1) Vi是整流桥正输出电压也是PFC输入端电压， 当S关闭时 Vi=-L×di/dt+VO ，V0是PFC输出端电压。 L=(VO-Vi)×dt/di (2) 导通时dt=tON 关闭时dt=tOFF 1.2.2 导出占空比D与Vi和VO的关系 ∵式(1)，(2)相等且△i都一样，得到： Vi×ton＝(V0－Vi)×tOFF Vi×ton＋Vi×tOFF＝VO ×tOFF 即Vi×T＝VO ×tOFF tOFF/T＝Vi/Vo ∵ D被定义为tON/T 则 tOFF/T＝(T－ton)/T＝1－D ∴D＝1－tOFF/T＝1－Vi/ VO=(VO－Vi)/VO 1.2.3导出由(PFC输入端未经滤波的)交流电压和PFC输出的直流电压所描述的电感表达式。 ∵Vi＝√2×Vin(AC)min； T＝1/F 由(1)知：L＝(Vi×ton)/△I＝［Vi×(D×T)］/ △I 又D＝(VO－Vi)/VO ，得到 L＝［(Vi×T）/△I］×D ＝［(Vi×T)/ △I］×(VO－Vi)/VO ＝［Vi×(VO－Vi)］/ △I·F·VO ＝［√2×Vin(AC)min·(V0－√2×Vin(AC)min)］/△I·F·V0 ＝［√2×Vin(AC)min.(1－√2×Vin(AC)min/V0)］/△I.F (3) 式中F单位Hz，L单位是享利。若×10-6就变成微享(μH)。 式(3) 就是临界电感的计算式。美国Metglas和南韩YuYu公司均使用该计算式计算临界电感。 1.2.4输入电流表达式 ∵PIn max＝VIn(rms)min×IIn(rms)max [电脑学堂]宇飞和你分享PFC ：不懂准被忽悠细说主动PFC电源为谁省电[图文必看] [复制链接] 宇飞电脑 无欲则钢有 容乃大电脑 问题加QQ： 1587478200 ?收听TA ?发消息 电梯直达 1楼 发表于 2010-2-18 19:46 |只看该作者|倒序浏览 ( w8 w$ u% ~/ Z% T( H: P 8 s3 l0 B& |( \8 s1 @+ q 随着全球用户对节能减排意识日益重视，消费者对DIY机的电源要求也渐渐变得苛刻，宇飞见到消费者对电源制品的重视感到非常 欣慰，但是消费者对一些选购上的细节并不了解，只冲着“主动PFC 电源”、“80PLUS电源”的噱头去购买，无知的您准会被忽悠。 d2 v8 @( y) D 主流电源分两类 ! ~4 C* @- r; l0 d8 y( I* q 我们要明明白白地消费，必须先了解购买目标的特性，主流电源主要分为两个类，一类是主流中低端产品惯用的被动PFC设计，而另 一类则是主打节能技术或者高端产品标配的主动PFC设计。 中低端主流的被动PFC设计方案 节能电源主流的主动PFC方案（主动PFC芯片CM6800G） 以往很多消费者购买电源，都会以重量来判定电源特性，重量较重的话就是被动PFC设计，而重量较轻就是主动PFC设计，其实这种选购方法存在一个误区，因为市面上还有一种劣质电源是无PFC设计的，既没有被动PFC电感，也没有主动PFC电路。这种无PFC的产品重量轻盈，而且价格便宜，贪小便宜的消费者错把这种无PFC的电源当成主动PFC来用，虽然购入价便宜，但是超低的转换效率以及不完善的保护电路，不仅会导致每月电费增加不少，还会危及人身安全。 小知识：何为PFC ？？PFC的英文全称为“Power Factor Correction”，意思是“功率因数校正”，功率因数指的是有效功率与总耗电量(视在功率)之间的关系，也就是有效功率除以总耗电量(视在功率)的比值。基本上功率因素可以衡量电力被有效利用的程度，当功率因素值越大，代表其电力利用率越高。计算机开关电源是一种电容输入型电路，其电流和电压之间的相位差会造成交换功率的损失，此时便 需要PFC电路提高功率因数。目前的PFC有两种，一种为被动式PFC（也 开关电源功率因素校正（PFC）及其工作原理------郝 铭 https://www.wendangku.net/doc/3618600854.html,/zuixin/145/LTC3780高频率同步器开关升降压式控制器 - 世纪电源网
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什么是功率因数补偿，什么是功率因数校正： 什么是功率因数补偿，什么是功率因数校正： 功率因数补偿：在上世纪五十年代，已经针对具有感性负载的交流用电器具的电压和电流不同相（图 1）从而引起的供电效率低下提出了改进方法（由于感性负载的电流滞后所加电压，由于电压和电流的相 位不同使供电线路的负担加重导致供电线路效率下降，这就要求在感性用电器具上并联一个电容器用以调 整其该用电器具的电压、电流相位特性，例如：当时要求所使用的 40W 日光灯必须并联一个 4.75μF 的 电容器）。用电容器并连在感性负载，利用其电容上电流超前电压的特性用以补偿电感上电流滞后电压的 特性来使总的特性接近于阻性，从而改善效率低下的方法叫功率因数补偿（交流电的功率因数可以用电源 电压与负载电流两者相位角的余弦函数值 cosφ 表示）。
图1 在具有感性负载中供电线路中电压和电流的波形,而在上世纪 80 年代起，用电器具大量的采用效率高 的开关电源，由于开关电源都是在整流后用一个大容量的滤波电容，使该用电器具的负载特性呈现容性， 这就造成了交流 220V 在对该用电器具供电时，由于滤波电容的充、放电作用，在其两端的直流电压出现 略呈锯齿波的纹波。滤波电容上电压的最小值远非为零，与其最大值(纹波峰值)相差并不多。根据整流二 极管的单向导电性，只有在 AC 线路电压瞬时值高于滤波电容上的电压时，整流二极管才会因正向偏置而 导通，而当 AC 输入电压瞬时值低于滤波电容上的电压时，整流二极管因反向偏置而截止。也就是说，在 AC 线路电压的每个半周期内，只是在其峰值附近，二极管才会导通。虽然 AC 输入电压仍大体保持正弦 波波形，但 AC 输入电流却呈高幅值的尖峰脉冲，如图 2 所示。这种严重失真的电流波形含有大量的谐波 成份，引起线路功率因数严重下降。 在正半个周期内（1800），整流二极管的导通角大大的小于 1800 甚至只有 300－700，由于要保证 负载功率的要求，在极窄的导通角期间会产生极大的导通电流，使供电电路中的供电电流呈脉冲状态，它 不仅降低了供电的效率，更为严重的是它在供电线路容量不足，或电路负载较大时会产生严重的交流电压 的波形畸变（图 3），并产生多次谐波，从而，干扰了其它用电器具的正常工作（这就是电磁干扰－EMI 和电磁兼容－EMC 问题）。