当前位置：文档库 › CDCUA877ZQLR;CDCUA877ZQLT;中文规格书,Datasheet资料

CDCUA877ZQLR;CDCUA877ZQLT;中文规格书,Datasheet资料

https://www.wendangku.net/doc/4b573057.html,

FEATURES

DESCRIPTION

CDCUA877

SCAS769A–AUGUST2006–REVISED JUNE2007

1.8-V PHASE LOCK LOOP CLOCK DRIVER

?Distributes One Differential Clock Input to Ten

Differential Outputs

? 1.8-V/1.9-V Phase Lock Loop Clock Driver for

Double Data Rate(DDR II)Applications?52-BallμBGA(MicroStar Junior?BGA,

0,65-mm pitch)

?Spread Spectrum Clock Compatible

?External Feedback Pins(FBIN,FBIN)are Used ?Operating Frequency:125MHz to410MHz

to Synchronize the Outputs to the Input ?Application Frequency:160MHz to410MHz

Clockst

?Low Current Consumption:<200mA Typ

?Meets or Exceeds CUA877/CAU878

?Low Jitter(Cycle-Cycle):±40ps Specification PLL Standard for

?Low Output Skew:35ps PC2-3200/4300/5300/6400o

?Stabilization Time<6μs?Fail-Safe Inputs

The CDCUA877is a high-performance,low-jitter,low-skew,zero-delay buffer that distributes a differential clock input pair(CK,CK)to ten differential pairs of clock outputs(Yn,Yn)and to one differential pair of feedback clock outputs(FBOUT,FBOUT).The clock outputs are controlled by the input clocks(CK,CK),the feedback clocks (FBIN,FBIN),the LVCMOS control pins(OE,OS),and the analog power input(AV DD).When OE is low,the clock outputs,except FBOUT/FBOUT,are disabled while the internal PLL continues to maintain its locked-in frequency.OS(output select)is a program pin that must be tied to GND or V DD.When OS is high,OE functions as previously described.When OS and OE are both low,OE has no affect on Y7/Y7,they are free running. When AV DD is grounded,the PLL is turned off and bypassed for test purposes.

When both clock inputs(CK,CK)are logic low,the device enters in a low power mode.An input logic detection circuit on the differential inputs,independent from input buffers,detects the logic low level and performs in a low power state where all outputs,the feedback,and the PLL are off.When the clock inputs transition from being logic low to being differential signals,the PLL turns back on,the inputs and the outputs are enabled,and the PLL obtains phase lock between the feedback clock pair(FBIN,FBIN)and the clock input pair(CK,CK)within the specified stabilization time.

The CDCUA877is able to track spread spectrum clocking(SSC)for reduced EMI.This device operates from –40°C to85°C).

AVAILABLE OPTIONS

T A52-Ball BGA(1)

–40°C to85°C CDCUA877ZQL

(1)For the most current package and ordering information,see the

Package Option Addendum at the end of this document,or see the

TI website at https://www.wendangku.net/doc/4b573057.html,.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.Copyright?2006–2007,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

https://www.wendangku.net/doc/4b573057.html,

CDCUA877

SCAS769A–AUGUST 2006–REVISED JUNE 2007

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

CDCUA877

SCAS769A–AUGUST2006–REVISED JUNE2007 Table1.Terminal Functions

NAME BGA MLF I/O DESCRIPTION

AGND G17Analog ground

AV DD H18Analog power

CK E14I Clock input with a(10k?to100k?)pulldown resistor

CK F15I Complementary clock input with a(10k?to100k?)pulldown resistor

FBIN E627I Feedback clock input

FBIN F626I Complementary feedback clock input

FBOUT H624O Feedback clock output

FBOUT G625O Complementary feedback clock output

OE F522I Output enable(asynchronous)

OS D521I Output select(tied to GND or VDD)

GND B2,B3,B4,10Ground

B5,C2,C5,

H2,H5,J2,J3,

J4,J5

V DDQ D2,D3,D4,1,6,9,15,20,Logic and output power

E2,E5,F2,23,28,31,36

G2,G3,G4,

Y[0:9]A2,A1,D1,38,39,3,11,14,O Clock outputs

J1,K3,A5,A6,34,33,29,19,16

D6,J6,K4

Y[0:9]A3,B1,C1,37,40,2,12,13,O Complementary clock outputs

K1,K2,A4,35,32,30,18,17

B6,C6,K6,K5

Table2.Function Table

INPUTS OUTPUTS PLL AV DD OE OS CK CK Y Y FBOUT FBOUT

GND H X L H L L H Bypassed/Off GND H X H L H H L Bypassed/Off GND L H L H L Z L Z L H Bypassed/Off GND L L H L L Z L Z H L Bypassed/Off

Y7Active Y7Active

1.8V Nomnal L H L H L Z L Z L H On

1.8V Nomnal L L H L L Z L Z H L On

Y7Active Y7Active

1.8V Nomnal H X L H L H L H On

1.8V Nomnal H X H L H L H L On

1.8V Nomnal X X L L L Z L Z L Z L Z Off

X X X H H Reserved

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

ABSOLUTE MAXIMUM RATINGS

CDCUA877

SCAS769A–AUGUST 2006–REVISED JUNE 2007

Figure 1.Logic Diagram (Positive Logic)

over operating free-air temperature range (unless otherwise noted)(1)

VALUE

UNIT V DDQ Supply voltage range –0.5to 2.5V A VDD V I Input voltage range (2)(3)

–0.5to V DDQ +0.5V V O Output voltage range

(2)(3)

–0.5to V DDQ +0.5

V I IK Input clamp current,(V I <0or V I >V DDQ )±50mA I OK Output clamp voltage,(V O <0or V O >V DDQ )±50mA I O Continuous output current,(V O =0to V DDQ )±50mA I DDC Continuous current through each V DDQ or GND ±100

mA No airflow 151.9R θJA Thermal resistance,junction-to-ambient (4)Airllflow 150ft/min 146.1K/W R θJC Thermal resistance,junction-to-case (4)No airflow

102.4T STG Storage temperature range

–65to 150

°C

(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)This value is limited to 2.5V maximum.

(4)

The package thermal impedance is calculated in accordance with JESD51and JEDEC2S1P (high-k board).

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

RECOMMENDED OPERATING CONDITIONS

CDCUA877 SCAS769A–AUGUST

2006–REVISED JUNE2007 (1)The PLL is turned off and bypassed for test purposes when AV DD is grounded.During this test mode,V DDQ remains within the

recommended operating conditions and no timing parameters are ensured.

(2)V ID is the magnitude of the difference between the input level on CK and the input level on CK,see Figure10for definition.The CK and

CK V IH and V IL limits define the dc low and high levels for the logic detect state.

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

CDCUA877

SCAS769A–AUGUST 2006–REVISED JUNE 2007

over recommended operating free-air temperature range

AV DD ,PARAMETER

TEST CONDITIONS MIN

TYP MAX

UNIT V DDG V IK Input (cl inputs)

I I =–18mA 1.7V –1.2

V I OH =-100＝A

1.7V to 1.9V

VDDQ –0.2V OH

High-level output voltage

I OH =–9mA

1.7V

1.1

I OL =100μA 0.1V OL

Low-level output voltage

V I OL =9mA

1.7V 0.6

I O(DL)Low-level output current,disabled V O(DL)=100mV,OE =L

1.7V 100μA V OD Differential output voltage (1)

1.7V 0.5

CK,CK

1.9V ±250I I Input current

μA

OE,OS,FBIN, 1.9V

±10FBIN

I DD(L

CK and CK =L

1.9V

500

Supply current,static (I DDQ +I ADD )

μA D)

CK and CK =410MHz,All outputs are open

1.9V 225

(not connected to a PCB)Supply current,dynamic (I DDQ +I ADD )I DD

(see (2)for C PD calculation)

All outputs are loaded with 2pF and 120-?termination resistor, 1.9V 225mA

CK and CK =410MHz CK,CK V I =V DD or GND 1.8V 23C I Input capacitance pF FBIN,FBIN V I =V DD or GND 1.8V 2

3CK,CK V I =V DD or GND 1.8V 0.25Change in input C I(Δ)pF

current

FBIN,FBIN

V I =V DD or GND

1.8V

0.25

(1)V OD is the magnitude of the difference between the true and complimentary outputs.See Figure 10for a definition.

(2)

Total I DD =I DDQ +I ADD =f CK ×C PD ×V DDQ ,solving for C PD =(I DDQ +I ADD )/(f CK ×V DDQ )CK the input frequency,V DDQ is the power supply,and C PD is the power dissipation capacitance.

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT Clock frequency (operating)(1)(2)AV DD ,V DD =1.8V ±0.1V 125410MHz f CK Clock frequency (application)

(1)(3)

AV DD ,V DD =1.8V ±0.1V 160410MHz t DC Duty cycle,input clock AV DD ,V DD =1.8V ±0.1V 40%

60%t L Stabilization time (4)

AV DD ,V DD =1.8V ±0.1V

μs

(1)The PLL must be able to handle spread spectrum induced skew.

(2)Operating clock frequency indicates a range over which the PLL must be able to lock,but in which it is not required to meet the other timing parameters (used for low speed system debug).

(3)Application clock frequency indicates a range over which the PLL must meet all timing parameters.

(4)

Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,within the value specified by the static phase offset t (φ),after power up.During normal operation,the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state,enter the power-down mode,and later return to active operation.CK and CK may be left floating after they have been driven low for one complete clock cycle.

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

SWITCHING CHARACTERISTICS

CDCUA877 SCAS769A–AUGUST2006–REVISED JUNE2007

over recommended operating free-air temperature range(unless otherwise noted)(1)

(1)There are two different terminations that are used with the following tests.The load/board in Figure2is used to measure the input and

output differential-pair cross voltage only.The load/board in Figure3is used to measure all For consistency,equal length cables must be used.

(2)This parameter is assured by design and characterization.

(3)Phase static offset time does not include jitter.

(4)For full frequency range of160MHz to410MHz.

(5)Period jitter,half-period jitter specifications are separate specifications that must be met independently of each other.

(6)In the frequency range of271MHz to410MHz,the minimum and maximum values of t jit(per)and t(φ)dyn and the maximum value for t sk(o)

must not exceed the corresponding minimum and maximum values of the160MHz to270MHz range.In addition,the sum of the specified values for|t jit(per)|,|t(φ)dyn|,and t sk(o)must meet the requirements for theΣt(su)and the sum of the specified values for|t(φ)dyn| and t sk(o)must meet the requirements for theΣt(h).

(7)The output slew rate is determined from the IBIS model into the load shown in Figure4.

(8)To eliminate the impact of input slew rates on static phase offset,the input reference clock input CK and CK and feedback

clock inputs FBIN and FBIN are recommended to be nearly equal.The2.5-V/ns skew rates are shown as a recommended target.

Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2DIMM application.

(9)Output differential-pair cross voltage specified at the DRAM clock input or the test load.

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html, CDCUA877

SCAS769A–AUGUST2006–REVISED JUNE2007

Figure2.Output Load Test Circuit1(Using High-Impedance Probe)

Figure3.Output Load Test Circuit2(Using SMA Coaxial Cable)

Figure4.IBIS Model Output Load

8Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

t c(n)

c(n+1)

t (

CDCUA877

SCAS769A–AUGUST 2006–REVISED JUNE 2007

Figure 5.Cycle-To-Cycle Period Jitter

Figure 6.Static Phase Offset

Figure 7.Output Skew

Submit Documentation Feedback

https://www.wendangku.net/doc/4b573057.html,

(n)

(half period)n(half period)n

CDCUA877

SCAS769A–AUGUST2006–REVISED JUNE2007

Figure8.Period Jitter

Figure9.Half-Period Jitter

Figure10.Input and Output Slew Rates

10Submit Documentation Feedback

分销商库存信息:

CDCUA877ZQLR CDCUA877ZQLT