DS-AVT6203A_v1d1

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AVT6203A EPD Controller Hardware Manual

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1 Revision History

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2 Index

1 Revision History ......................................................................................................................................................... 22 Index .. (33)

Introduction ............................................................................................................................................................ 103.1 Summary .................................................................................................................................................. 103.2 AVT6203A Reference System

(104)

Function List ............................................................................................................................................................ 104.1 16-Bits CPU Interface （INTEL80） .......................................................................................................... 104.2 Source driver and Gate driver Interface .................................................................................................. 104.3 SDRAM Integration ................................................................................................................................... 114.4 Power Control Interface ........................................................................................................................... 114.5 Temperature Sensor Interface ................................................................................................................. 114.6 SPI FLASH Interface .................................................................................................................................. 114.7 Clock ......................................................................................................................................................... 114.8

Display Function

....................................................................................................................................... 115 Function Description .. (126)

System Pins ............................................................................................................................................................. 136.1 System Diagram ....................................................................................................................................... 136.2 Pin Description ......................................................................................................................................... 146.2.1 Top View ................................................................................................................................................... 146.2.2 System Clock Interface ............................................................................................................................. 156.2.3 Host Interface ........................................................................................................................................... 156.2.4 SPI Flash Interface .................................................................................................................................... 156.2.5 I2C Interface ............................................................................................................................................. 156.2.6 Source Driver Interface ............................................................................................................................ 166.2.7 Gate Driver Interface ................................................................................................................................ 166.2.8 Power Control Interface ........................................................................................................................... 166.2.9 Power Interface ........................................................................................................................................ 166.2.10

GPIO Interface

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7

Power Supply .......................................................................................................................................................... 187.1

Recommend Power Condition

................................................................................................................. 188 Interface Timing ...................................................................................................................................................... 198.1 Reset Timing ............................................................................................................................................. 198.2 Host Interface Timing ............................................................................................................................... 198.2.1 16-bit Host Write Timing (Intel 80) .......................................................................................................... 198.2.2 16-bit Host Read Timing (Intel 80) ........................................................................................................... 208.3 Panel Interface ......................................................................................................................................... 218.3.1 Setting Diagram ........................................................................................................................................ 218.3.2 Frame Rate Calculation ............................................................................................................................ 228.4

Power Pin Interface

.................................................................................................................................. 229 Clock ........................................................................................................................................................................ 239.1 Clock description ...................................................................................................................................... 239.2 Power Manager ........................................................................................................................................ 249.2.1 Power Mode Description ......................................................................................................................... 249.2.2 Power Mode Convert Diagram ................................................................................................................. 249.2.3

Power Mode Convert:

.............................................................................................................................. 2510 Command List ......................................................................................................................................................... 2710.1 Commands Description ............................................................................................................................ 2810.1.1 INIT_CMD_SET ......................................................................................................................................... 2810.1.2 INIT_PLL_STBY .......................................................................................................................................... 2810.1.3 RUN_SYS ................................................................................................................................................... 2810.1.4 STBY .......................................................................................................................................................... 2910.1.5 SLP ............................................................................................................................................................ 2910.1.6 INIT_SYS_RUN .......................................................................................................................................... 2910.1.7 INIT_SYS_STBY .......................................................................................................................................... 2910.1.8 INIT_SDRAM ............................................................................................................................................. 2910.1.9 INIT_DSPE_CFG

........................................................................................................................................ 3010.1.10

INIT_DSPE_TMG

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10.1.13 WR_REG ............................................................................................................................................ 3010.1.14 RD_SFW ............................................................................................................................................ 3110.1.15 WR_SFW ........................................................................................................................................... 3110.1.16 END_SFW .......................................................................................................................................... 3110.1.17 BST_RD_SDR ..................................................................................................................................... 3110.1.18 BST_WR_SDR .................................................................................................................................... 3110.1.19 BST_END_SDR ................................................................................................................................... 3210.1.20 LD_IMG ............................................................................................................................................. 3210.1.21 LD_IMG_AREA .................................................................................................................................. 3210.1.22 LD_IMG_END .................................................................................................................................... 3210.1.23 LD_IMG_WAIT .................................................................................................................................. 3210.1.24 LD_IMG_SETADR .............................................................................................................................. 3310.1.25 LD_IMG_DSPEADR ............................................................................................................................ 3310.1.26 WAIT_DSPE_TRG .............................................................................................................................. 3310.1.27 WAIT_DSPE_FREND .......................................................................................................................... 3310.1.28 WAIT_DSPE_LUTFREE ....................................................................................................................... 3310.1.29 WAIT_DSPE_MLUTFREE .................................................................................................................... 3410.1.30 RD_WFM_INFO ................................................................................................................................. 3410.1.31 UPD_INIT .......................................................................................................................................... 3410.1.32 UPD_FULL ......................................................................................................................................... 3410.1.33 UPD_FULL_AREA ............................................................................................................................... 3510.1.34 UPD_PART ......................................................................................................................................... 3510.1.35 UPD_PART_AREA .............................................................................................................................. 3510.1.36 UPD_GDRV_CLR ................................................................................................................................ 3510.1.37 UPD_SET_IMGADR ........................................................................................................................... 3510.1.38 DITHER_SET_ADR ............................................................................................................................. 3610.1.39

DITHER_AREA

................................................................................................................................... 3611 Register

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11.2.1

System Configuration Register

................................................................................................................. 3811.2.1.1 [0000h]Revision Code Register ................................................................................................ 3811.2.1.2 [0002h]Product Code Register ................................................................................................. 3811.2.1.3 [0006h]Power Save Mode Register .......................................................................................... 3811.2.1.4 [0008h] Software Reset Register .............................................................................................. 3911.2.1.5

[000Ah]System Statue Register ................................................................................................ 3911.2.2 Clock configuration Register

.................................................................................................................... 4011.2.2.1 [0010h] PLL Configuration Registers 0 ..................................................................................... 4011.2.2.2 [0012h] PLL Configuration 1 .................................................................................................... 4011.2.2.3 [0014h] PLL Configuration 2 .................................................................................................... 4111.2.2.4 [0016h] Clock Configuration Register ...................................................................................... 4111.2.2.5 [0018h] Pixel Clock Configuration Register .............................................................................. 4111.2.2.6

[001Ah] I2C Thermal Sensor Clock Configuration .................................................................... 4211.2.3 Memory Load Configuration Register

...................................................................................................... 4211.2.3.1 [0020h] Memory Load Configuration Register ........................................................................ 4211.2.4 Driver Strength Configuration Register .................................................................................................... 4311.2.4.1 [0030h] Interface Driver Strength Configuration Register ....................................................... 4311.2.5

SDRAM Configuration Register

................................................................................................................ 4411.2.5.1 [0100h] SDRAM Configuration Register ................................................................................... 4411.2.5.2 [0102h] SDRAM Initial Register ................................................................................................ 4511.2.5.3 [0104h] SDRAM State Trigger Register .................................................................................... 4511.2.5.4 [0106h] SDRAM Refresh Clock Configuration Register ............................................................ 4611.2.5.5 [0108h] SDRAM Read Data Delay Select Register .................................................................... 4611.2.5.6 [010Ah] SDRAM Extended Mode Configuration Register ........................................................ 4711.2.5.7

[010Ch] SDRAM Controller Software Reset Register ............................................................... 4811.2.6 HOST Memory Configuration Register

..................................................................................................... 4811.2.6.1 [0140h] Host Memory Access Configuration and Status Register ........................................... 4811.2.6.2 [0142h] Host Memory Access Triggers Register ....................................................................... 4911.2.6.3 [0144h] Host Raw Memory Access Address Register 0 ............................................................ 5011.2.6.4 [0146H] Host Raw Memory Access Address Register 1 ........................................................... 5011.2.6.5 [0148h] Host Raw Memory Access Count Register 0 ............................................................... 5011.2.6.6 [014Ah] Host Raw Memory Access Count Register 1 .............................................................. 5011.2.6.7 [014Ch] Packed Pixel Rectangular X-Start Register .................................................................. 5111.2.6.8 [014Eh] Packed Pixel Rectangular Y-Start Register ................................................................... 5111.2.6.9 [0150h] Packed Pixel Rectangular Width Register ................................................................... 5111.2.6.10 [0152h] Packed Pixel Rectangular Height Register ................................................................... 5211.2.6.11 [0154h] Host Memory Access Port Register ............................................................................ 5211.2.6.12

[0158h] Host Raw Memory FIFO Level Register

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11.2.6.14 [01A0h] Overlap Arithmetic Configuration Register ................................................................ 5311.2.7 SPI Flash Configuration Register

.............................................................................................................. 5411.2.7.1 [0200h] SPI Flash Read Data .................................................................................................... 5411.2.7.2 [0202h] SPI Flash Data Output Enable ..................................................................................... 5411.2.7.3 [0204h] SPI Flash Chip Select Control Register ........................................................................ 5411.2.7.4 [0206h] SPI Flash Chip Select Control Register ........................................................................ 5511.2.7.5

[0208h] SPI Flash Chip Select Control Register ........................................................................ 5611.2.8 I2C Configuration Register

....................................................................................................................... 5611.2.8.1 [0210h] I2C Thermal Sensor Configuration Register ................................................................ 5611.2.8.2 [0212h] I2C Thermal Sensor Status Register ............................................................................ 5611.2.8.3 [0214h] I2C Thermal Sensor Read Trigger Register .................................................................. 5711.2.8.4 [0216h] I2C Thermal Sensor Temperature Value Register ....................................................... 5811.2.8.5 [0218h] I2C Transmit Value Register ........................................................................................ 5811.2.8.6

[021Ah] I2C Receive Data Register ........................................................................................... 5811.2.9 Power Pin Configuration Register

............................................................................................................ 5911.2.9.1 [0230h] Power Pin Control Register ......................................................................................... 5911.2.9.2 [0232h] Power Pin Configuration Register ............................................................................... 5911.2.9.3 [0234h] Power0 Pin To Power1 Pin Timing Delay Register ...................................................... 6011.2.9.4 [0236h] Power1 Pin To Power2 Pin Timing Delay Register ...................................................... 6011.2.9.5

[0238h] Power Pin Timing Delay 2-3 Register .......................................................................... 6111.2.10 Interrupt Configuration Register

...................................................................................................... 6111.2.10.1 [0240h] Interrupt Raw Status register ..................................................................................... 6111.2.10.2 [0242h] Interrupt Masked Status Register ............................................................................... 6211.2.10.3

[0244h] Interrupt Control Register .......................................................................................... 6311.2.11 GPIO Configuration Register

............................................................................................................. 6411.2.11.1 [0250h] GPIO Configuration Register ....................................................................................... 6411.2.11.2 [0252h] GPIO Status/Control Register ..................................................................................... 6411.2.11.3 [0254h] GPIO Interrupt Enable Register .................................................................................. 6511.2.11.4 [0256h] GPIO Interrupt Status Register ................................................................................... 6511.2.11.5

[0258h] GPIO Sleep Mode Output Control Register ................................................................ 6611.2.12 Command RAM Configuration Register

........................................................................................... 6711.2.12.1 [0290h] Command RAM Controller Configuration Register .................................................... 6711.2.12.2 [0292h] Command RAM Controller Address Register .............................................................. 6711.2.12.3

[0294h] Command RAM Controller Access Port Register ........................................................ 6811.2.13 Display Timing Configuration Register

............................................................................................. 6811.2.13.1 [0300h] Frame Data Length Register ....................................................................................... 6811.2.13.2 [0302h] Frame Sync. Length Register ...................................................................................... 6811.2.13.3 [0304h] Frame Begin/End Length Register .............................................................................. 6811.2.13.4 [0306h] Line Data Length Register ........................................................................................... 6911.2.13.5

[0308h] Line Sync. Length Register

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11.2.14 Source Driver Configuration Register

............................................................................................... 7011.2.14.1 [030Ch] Source Drive Configuration Register .......................................................................... 7011.2.14.2

[030Eh] Source Drive Configuration Register ........................................................................... 7111.2.15 Display Buffer Configuration Register

.............................................................................................. 7211.2.15.1 [0310h] Image Buffer Start Register 0 ..................................................................................... 7211.2.15.2 [0312h] Image Buffer Start Register 1 ..................................................................................... 7211.2.15.3 [0314h] Update Buffer Start Register 0 .................................................................................... 7211.2.15.4

[0316h] Update Buffer Start Register 1 .................................................................................... 7211.2.16 General Configuration Register

........................................................................................................ 7311.2.16.1 [0320h] Temperature Device Select Register ........................................................................... 7311.2.16.2 [0322h] Temperature Value Register ....................................................................................... 7311.2.16.3 [032Ch] General Configuration Register .................................................................................. 7311.2.16.4

[032Eh] LUT Mask Register ...................................................................................................... 7411.2.17 Update Buffer Configuration Register

.............................................................................................. 7411.2.17.1 [0330h] Update Buffer Configuration Register ........................................................................ 7411.2.17.2 [0332h] Update Buffer Pixel Set Value Register ....................................................................... 7511.2.17.3

[0334h] Display Engine Control/Trigger Register ..................................................................... 7511.2.18 LUT Status Register

........................................................................................................................... 7611.2.18.1 [0336h] LUT STATUS Register 0 ................................................................................................ 7611.2.18.2

[0338h] Display Engine Busy Status Register ........................................................................... 7711.2.19 Interrupt Register

............................................................................................................................. 7711.2.19.1 [033Ah] Display Engine Interrupt Raw Status Register ............................................................ 7711.2.19.2 [033Ch] Display Engine Interrupt Masked Status Register ....................................................... 7911.2.19.3

[033Eh] Display Engine Interrupt Enable Register ................................................................... 8111.2.20 Display Engine Configuration Register

............................................................................................. 8211.2.20.1 [0340h] Area Update Pixel Rectangular X-Start Register ......................................................... 8211.2.20.2 [0342h] Area Update Pixel Rectangular Y-Start Register .......................................................... 8211.2.20.3 [0344h] Area Update Pixel Rectangular X-End Position/Horizontal Size .................................. 8311.2.20.4 [0346h] Area Update Pixel Rectangular Y-End Position/Vertical Size ....................................... 8311.2.20.5 [0348h] Host Pixel Rectangular X-start Position ...................................................................... 8311.2.20.6 [034Ah] Host Pixel Rectangular Y-start Position ...................................................................... 8411.2.20.7 [034Ch] Host Pixel Rectangular X-end Position ........................................................................ 8411.2.20.8

[034Eh] Host Pixel Rectangular Y-End Position ........................................................................ 8411.2.21 SPI Flash Start Address Configuration Register

................................................................................ 8511.2.21.1 [0350h] Waveform Header Serial Flash Waveform Register 0 ................................................. 8511.2.21.2

[0352h] Waveform Header Serial Flash Waveform Register 1 ................................................. 8511.2.22 Advanced Display Configuration Register

........................................................................................ 8511.2.22.1 [0370h] Source Driver Advanced Timing Configuration Register ............................................. 8511.2.22.2

[0372h] Gate Driver Advanced Timing Configuration Register

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11.2.23 AUO Configuration Registers

............................................................................................................ 8611.2.23.1 [0380h] XDIO Pulse Width Configuration Register .................................................................. 8611.2.23.2 [0382h] LD Delay Configuration Register ................................................................................. 8611.2.23.3 [0384h] LD Pulse Width Configuration Register ...................................................................... 8711.2.23.4 [0386h] YCLK Delay Configuration Register ............................................................................. 8711.2.23.5 [0388h] YCLK Pulse Width Configuration Register ................................................................... 8711.2.23.6 [038Ah] YOE Delay Configuration Register .............................................................................. 8811.2.23.7 [038Ch] YOE Pulse Width Configuration Register .................................................................... 8811.2.23.8 [038Eh] YDIO Delay Configuration Register ............................................................................. 8811.2.23.9 [0390h] YDIO Pulse Width Configuration Register .................................................................. 8911.2.23.10

[0392h] AUO Enable and Polarity Control Register .................................................................. 8911.2.24 Dithering Configuration Registers

.................................................................................................... 9011.2.24.1 [0400h] Dithering Configuration Register ................................................................................ 9011.2.24.2 [0402h] Dithering Status Register ............................................................................................ 9011.2.24.3 [040Ah] Dithering Interrupt Raw Status Register .................................................................... 9011.2.24.4 [040Ch] Dithering Interrupt Masked Status Register ............................................................... 9111.2.24.5 [040Eh] Dithering Interrupt Enable Register ............................................................................ 9111.2.24.6 [0410h] Dithering Pixel Rectangular X-Start Register .............................................................. 9211.2.24.7 [0412h] Dithering Pixel Rectangular Y-Start Register ............................................................... 9211.2.24.8 [0414h] Dithering Pixel Rectangular X-End/Horizontal Size Register ....................................... 9211.2.24.9 [0416h] Dithering Pixel Rectangular Y-End/Vertical Size Register ............................................ 9311.2.24.10 [0420h] Dithering Buffer Start Address Register 0 ................................................................... 9311.2.24.11

[0422h] Dithering Buffer Start Address Register 1 ................................................................... 9311.2.25 Instruction Parameter Configuration Register

................................................................................. 9311.2.25.1

[0800h] Instruction Parameter Write Port Register

................................................................. 9312 Mechanical Data

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3 Introduction

3.1 Summary

A VT6203 EPD controller provides customers a low cost, high efficiency monolithic solution for EPD. The controller can reduce CPU’s runtime for displaying and has glueless interface to popular Gate drivers and Source Drivers. It supports 16 regions to update simultaneously and accelerates touch pen, scroll bar and other on-screen user interactive applications. This monolithic solution also provides customized interface for power management unit of the system.

3.2 AVT6203A Reference System

4 Function List

4.1 16-Bits CPU Interface （INTEL80）

● Support 16-Bits I80 interface

● Support register access and SDRAM operation by commands ● Support Packed data and raw data of image transfer

4.2 Source driver and Gate driver Interface

● Glueless interface to AUO, PVI, LG, OED panels ● Configurable timing for source and gate driver

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4.3 SDRAM Integration

● Integrate 4Mbyte Mobile SDRAM ● Support 128MHz clock

4.4 Power Control Interface

● Five power control pins with timing configuration for on/off control

4.5 Temperature Sensor Interface

● Support temperature senor of I2C interface, like LM75

4.6 SPI FLASH Interface

● Integrate 4Mbit SPI Flash

● SPI Flash contents: Waveform, Instruction code and Boot setting ● Support high speed Mode

4.7 Clock

● Support CLKI and oscillator for clock input ● Configurable clock frequency by on chip PLL

4.8 Display Function

● Support full image and part image update ● Support 15 waveform modes ● Support 16 LUT pipeline update ●

Support image rotation

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5 Function Description

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6 System Pins

6.1 System Diagram

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6.2 Pin Description

6.2.1 Top View

A B C D E F G H J K L M N P

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6.2.2 System Clock Interface

*If CLKI is clock input, OSCI must be pull-high or pull-low.

6.2.3 Host Interface

6.2.4 SPI Flash Interface

6.2.5 I2C Interface

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6.2.6 Source Driver Interface

6.2.7 Gate Driver Interface

6.2.8 Power Control Interface

6.2.9 Power Interface

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6.2.10 GPIO Interface

6.2.11 Others Pins

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7 Power Supply

7.1 Recommend Power Condition

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8 Interface Timing

8.1

Reset Timing

RESET_L

8.2 Host Interface Timing

8.2.1

16-bit Host Write Timing (Intel 80)

HD/C

HCS_L

HWE_L

HRD_L

HDB[15:0]

HRDY

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8.2.2

16-bit Host Read Timing (Intel 80)

HD/C

HCS_L

HRD_L

HWE_L

HDB[15:0]

HRDY