VN5050AJ-E_08中文资料

February 2008 Rev 61/31

VN5050AJ-E

Single channel high side driver with analog current sense for automotive applications

Features

■

General features

–

Inrush current active management by power limitation

–Very low stand-by current – 3.0V CMOS compatible input

–Optimized electromagnetic emission –Very low electromagnetic susceptibility –In compliance with the 2002/95/EC European directive ■

Diagnostic functions

–Proportional load current sense

–High current sense precision for wide range currents

–Current sense disable

–Thermal shutdown indication –Very low current sense leakage

■

Protection

–Undervoltage shut-down –Overvoltage clamp –Load current limitation

–Self limiting of fast thermal transients

–Protection against loss of ground and loss of V CC

–Thermal shut down

–Reverse battery protection ( see Application schematic )

–Electrostatic discharge protection

Application

■All types of resistive, inductive and capacitive loads

■

Suitable as LED driver

Description

The VN5050AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).

This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open.

When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition.Output current limitation protects the device in overload condition. In case of long overload

duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

Max supply voltage V CC 41 V Operating voltage range V CC 4.5 to 36V Max On-State resistance R ON 50 m ?Current limitation (typ)I LIMH 16.5 A Off state supply current

I S

2 μA

PowerSSO-12

Table 1.

Device summary

Package Order codes

Tube

Tape and Reel PowerSSO-12

VN5050AJ-E

VN5050AJTR-E

https://www.wendangku.net/doc/441988584.html,

Contents VN5050AJ-E

Contents

1Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

3.1.2Solution 2: diode (D GND) in the ground line . . . . . . . . . . . . . . . . . . . . . . 22

3.2Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1PowerSSO-12? thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1ECOP ACK? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VN5050AJ-E List of tables List of tables

Table 1.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2.Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3.Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6.Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7.Switching (V CC=13V, T j=25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8.Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9.Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10.Current sense (8V

3/31

List of figures VN5050AJ-E List of figures

Figure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4.Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6.Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7.Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8.I OUT/I SENSE Vs. I OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9.Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13.Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15.Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16.Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17.On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18.On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20.Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21.ILIMH Vs. Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 22.Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23.CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24.CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25.CS_DIS low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26.Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 27.Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 28.PowerSSO-12? PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 29.Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24 Figure 30.PowerSSO-12? thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25 Figure 31.Thermal fitting model of a single channel HSD in PowerSSO-12? . . . . . . . . . . . . . . . . . 25 Figure 32.PowerSSO-12? package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 33.PowerSSO-12? tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 34.PowerSSO-12? tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31

VN5050AJ-E Block diagram and pin description

5/31

1 Block diagram and pin description

Table 2.

Pin function

Name Function

V CC

Battery connection.OUTPUT Power output.

GND Ground connection. Must be reverse battery protected by an external diode/resistor network.

INPUT

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.

CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.

CS_DIS

Active high CMOS compatible pin, to disable the current sense pin.

Block diagram and pin description VN5050AJ-E

6/31

Note:The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are

connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,

these pins should be left unconnected.

Table 3.Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C.Output Input CS_DIS Floating N.R.X X X X

To ground Through 1k? resistor X N.R.(1) 1.Not recommended.Through 10k?

resistor

Through

10k? resistor

VN5050AJ-E Electrical specifications

7/31

2 Electrical specifications

Figure 3.

Current and voltage conventions

Note:

V F = V OUT - V CC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

I S

I GND V CC

V CC

V SENSE

OUTPUT

I OUT

CURRENT SENSE

I SENSE

INPUT

I IN

V IN

V OUT

GND

CS_DIS I CSD V CSD

V F

Table 4.

Absolute maximum ratings

Symbol Parameter

Value Unit V CC DC supply voltage 41V -V CC Reverse DC supply voltage 0.3V - I GND DC reverse ground pin current 200mA I OUT DC output current

Internally limited A - I OUT Reverse DC output current 30A I IN DC input current

-1 to 10mA I CSD

DC current sense disable input current

-1 to 10mA -I CSENSE DC reverse CS pin current 200mA V CSENSE Current sense maximum voltage V CC -41+V CC V V E MAX

Maximum switching energy (single pulse)

(L= 3mH; R L =0?; V bat =13.5V; T jstart =150oC; I OUT = I limL (Typ.) )

104

mJ

Electrical specifications

VN5050AJ-E

8/31

2.2 Thermal data

V ESD

Electrostatic discharge (Human Body Model: R=1.5k ?; C=100pF)- INPUT

- CURRENT SENSE - CS_DIS - OUTPUT - V CC

40002000400050005000V V V V V V ESD Charge device model (CDM-AEC-Q100-011)750V T j Junction operating temperature -40 to 150°C T stg

Storage temperature

-55 to 150

°C

Table 4.

Absolute maximum ratings (continued)

Symbol

Parameter

Value Unit Table 5.

Thermal data

Symbol

Parameter

Max value

Unit R thj-case Thermal resistance junction-case (MAX) 2.7

°C/W

R thj-amb Thermal resistance junction-ambient (MAX)

See Figure 29. °C/W

VN5050AJ-E Electrical specifications

9/31

2.3 Electrical characteristics

Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless

otherwise specified.

Table 6.

Power section

Symbol Parameter Test conditions

Min.Typ.Max.Unit V CC Operating supply voltage 4.5

1336V V USD Undervoltage shutdown

3.5

4.5

V V USDhyst

Undervoltage

shutdown hysteresis 0.5

V R ON On state resistance I OUT = 2A; T j =25°C I OUT = 2A; T j =150°C

I OUT = 2A; V CC =5V; T j =25°C 5010065m ?m ?m ?V clamp Clamp voltage I S = 20mA

41

4652V I S

Supply current

Off State; V CC =13V; T j =25°C; V IN =V OUT =V SENSE =V CSD =0V

On State; V CC =13V; V IN =5V; I OUT =0A 2(1)1.51.PowerMOS leakage included.

5(1)3μA mA I L(off)Off state output current V IN =V OUT =0V; V CC =13V; T j =25°C V IN =V OUT =0V; V CC =13V; T j =125°C 000.01

35μA V F

Output - V CC diode voltage

-I OUT = 2A; T j = 150°C

0.7V

Table 7.

Switching (V CC =13V, T j =25°C)

Symbol Parameter

Test conditions Min.

Typ.Max.Unit

t d(on)T urn-on delay time R L = 6.5? (see Figure 7.)20μs t d(off)

T urn-off delay time

R L = 6.5? (see Figure 7.)40μs (dV OUT /dt)on T urn-on voltage slope R L = 6.5?See Figure 20V /μs (dV OUT /dt)off T urn-off voltage slope

R L = 6.5?

See Figure 22V /μs W ON Switching energy losses

during tw on

R L = 6.5? (see Figure 7.)

0.20mJ W OFF

Switching energy losses

during tw off

R L = 6.5? (see Figure 7.)

0.3

mJ

Electrical specifications VN5050AJ-E

10/31Table 8.Logic input

Symbol Parameter Test conditions Min.Typ.Max.Unit V IL Input low level voltage0.9V

I IL Low level input current V IN= 0.9V1μA

V IH Input high level voltage 2.1V

I IH High level input current V IN= 2.1V10μA

V I(hyst)Input hysteresis voltage0.25V V ICL Input clamp voltage

I IN= 1mA

I IN= -1mA

5.5

-0.7

7V

V V CSDL CS_DIS low level voltage0.9V

I CSDL Low level CS_DIS current V CSD= 0.9V1μA

V CSDH CS_DIS high level voltage 2.1V

I CSDH High level CS_DIS current V CSD= 2.1V10μA V CSD(hyst)CS_DIS hysteresis voltage0.25V V CSCL CS_DIS clamp voltage

I CSD= 1mA

I CSD= -1mA

5.5

-0.7

7V

V Table 9.Protection and diagnostics(1)

1.To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles.

Symbol Parameter Test conditions Min.Typ.Max.Unit

I limH

DC Short circuit

current

V CC = 13V

5V

1216.523

23

A

A

I limL

Short circuit current

during thermal cycling

V CC=13V T R

Shutdown

temperature

150175200°C T R Reset temperature T RS + 1T RS + 5°C T RS

Thermal reset of

STA TUS

135°C T HYST

Thermal hysteresis

(T TSD-T R)

7°C V DEMAG

Turn-off output voltage

clamp

I OUT= 2A; V IN= 0; L= 6mH V CC-41V CC-46V CC-52V

V ON

Output voltage drop

limitation

I OUT= 0.1A;

T j= -40°C...+150°C

(see Figure 5.)

25mV

VN5050AJ-E

Electrical specifications

11/31

Table 10.

Current sense (8V

Symbol Parameter Test conditions

Min.Typ.Max.Unit K 0

I OUT /I SENSE

I OUT = 0.05A; V SENSE =0.5V; V CSD =0V;T j = -40°C...150°C

110024403480K 1I OUT /I SENSE

I OUT =1A; V SENSE =0.5V; V CSD =0V; T j = -40°C...150°C

I OUT = 1A; V SENSE = 0.5V; V CSD = 0V;T j = 25°C...150°C

160016302030203025802430

dK 1/K 1(1)

Current sense ratio

drift

I OUT =1A; V SENSE = 0.5V;

V CSD =0V;T J =-40 °C to 150 °C

-10+10%

K 2I OUT /I SENSE

I OUT = 2A; V SENSE = 4V; V CSD = 0V; T j = -40°C...150°C

I OUT = 2A; V SENSE = 4V; V CSD = 0V; T j = 25°C...150°C

177018002000200023102200

dK 2/K 2(1)

Current sense ratio

drift

I OUT = 2 A; V SENSE = 4 V;

V CSD = 0V;T J = -40 °C to 150 °C

-6+6%

K 3I OUT /I SENSE

I OUT = 4A; V SENSE = 4V; V CSD = 0V; T j = -40°C...150°C

I OUT = 4A; V SENSE = 4V; V CSD = 0V;T j = 25°C...150°C

186018701970197021402120

dK 3/K 3

(1)

Current sense ratio

drift

I OUT = 4 A; V SENSE = 4 V;

V CSD =0V;

T J =-40 °C to 150 °C

-3+3%

I SENSE0

Analog sense leakage current

I OUT = 0A; V SENSE =0V;

V CSD = 5V; V IN =0V; T j = -40°C...150°C V CSD = 0V; V IN =5V; T j = -40°C...150°C I OUT = 2A; V SENSE = 0V;

V CSD = 5V; V IN =5V; T j = -40°C...150°C

000121μA μA

μA I OL Openload ON state current detection threshold

V IN = 5V , I SENSE = 5 μA 4

20

mA

V SENSE

Max analog sense output voltage I OUT =2A; V CSD =0V 5

V

V SENSEH Analog sense output voltage in overtemperature condition V CC =13V; R SENSE =10K ?

9V

I SENSEH Analog sense output current in overtemperature condition

V CC =13V , V SENSE =5V

8mA

Electrical specifications VN5050AJ-E

12/31Figure 4.Current sense delay characteristics

Figure 5.Output voltage drop limitation

t DSENSE1H

Delay response

time from falling

edge of CS_DIS pin

V SENSE<4V, 0.5A

I SENSE=90% of I SENSEmax

(see Figure 4.)

50100μs t DSENSE1L

Delay response

time from rising

edge of CS_DIS pin

V SENSE<4V, 0.5A

I SENSE=10% of I SENSEmax

(see Figure 4.)

520μs t DSENSE2H

Delay response

time from rising

edge of INPUT pin

V SENSE<4V, 0.5A

I SENSE=90% of I SENSE max

(see Figure 4.)

80250μs ?t DSENSE2H

Delay response

time between rising

edge of output

current and rising

edge of current

sense

V SENSE<4V,

I SENSE =90% of I SENSEMAX,

I OUT=90% of I OUTMAX

I OUTMAX=2A (see Figure6)

65μs t DSENSE2L

Delay response

time from falling

edge of INPUT pin

V SENSE<4V, 0.5A

I SENSE=10% of I SENSE max

(see Figure 4.)

100250μs 1.Parameter guaranteed by design; it is not tested.

Table 10.Current sense (8V

Symbol Parameter Test conditions Min.Typ.Max.Unit SENSE CURRENT

INPUT

LOAD CURRENT

CS_DIS

t DSENSE2H t

DSENSE2L

t DSENSE1L t DSENSE1H

V on

I out

V cc-V out

T j=150o C T

j=25

o C

T j=-40o C

V on/R on(T)

VN5050AJ-E

Electrical specifications

13/31

Figure 6.

Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

Figure 7.Switching characteristics

V IN

I OUT

I SENSE

I OUTMAX

I SENSEMAX 90% I SENSEMAX

90% I OUTMAX

?t DSENSE2H

t

t

t

V OUT

dV OUT /dt (on)

t r

80%

10%

t f

dV OUT /dt (off)

t d(off)

t d(on)

INPUT

t

t

90%

t Won t Woff

Electrical specifications VN5050AJ-E

14/31

Note:Parameter guaranteed by design; it is not tested.

VN5050AJ-E

Electrical specifications

15/31

Table 11.

Truth table

Conditions Input Output Sense (V CSD =0V)(1)

1.If the V CSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents

and external circuit.

Normal operation L H L H 0Nominal

Overtemperature L H L L 0V SENSEH

Undervoltage L H L L 00

Short circuit to GND (R sc ≤ 10 m ?)L H H L L L 0

0 if T j < T TSD

V SENSEH if T j > T TSD

Short circuit to V CC L H H H 0< Nominal

Negative output voltage clamp

L

L

Electrical specifications VN5050AJ-E

16/31Table 12.Electrical transient requirements

ISO 7637-2:

2004(E)

Test pulse

Test levels Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and

Impedance III IV

1-75V-100V5000 pulses0.5 s 5 s 2 ms, 10 ?2a+37V+50V5000 pulses0.2 s 5 s50 μs, 2 ?3a-100V-150V1h90 ms100 ms0.1 μs, 50 ?3b+75V+100V1h90 ms100 ms0.1 μs, 50 ?4-6V-7V1pulse

100 ms, 0.01

?5b(2)+65V+87V 1 pulse400 ms, 2?

ISO 7637-2:

2004(E)

Test pulse

Test level results(1)

1.The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.

III IV

1C C

2a C C

3a C C

3b C C

4C C

5b(2)

2.Valid in case of external load dump clamp: 40V maximum referred to ground.

C C

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to

disturbance and cannot be returned to proper operation without replacing the device.

VN5050AJ-E Electrical specifications

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Electrical specifications

VN5050AJ-E

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2.4 Electrical characteristics curves

Figure 11.Off state output current Figure 12.High level input current

TBD

Figure 13.Input clamp voltage Figure 14.Input low level

Figure 15.Input high level Figure 16.Input hysteresis voltage

VN5050AJ-E

Electrical specifications

19/31 Figure 17.On state resistance vs. T case Figure 18.On state resistance vs. V CC

Figure 19.Undervoltage shutdown Figure 20.Turn-On voltage slope

Figure 21.I LIMH Vs. T case Figure 22.Turn-Off voltage slope

TBD

Electrical specifications

VN5050AJ-E

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Figure 23.CS_DIS high level voltage Figure 24.CS_DIS clamp voltage

Figure 25.CS_DIS low level voltage